JP2001024726A - Demodulation method based on digital processing of phase modulation signal and digital demodulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress enlargement of device scale by shortening the time required for carrier reproduction, even in the case the deviation of a carrier frequency in hierarchical transmission occurs. SOLUTION: In a satellite digital receiver which demodulates a phase modulation signal in heirarchical transmission, carrier reproduction is performed with the C/N ratio of a phase modulation signal in a lower layer. I and Q signals, obtained by orthogonal detection of the input phase modulation signal, are converted to digital values in the constitution from an in-phase detector 2 to a since oscillator 18. These digitized I and Q signals are multiplied by the reproduced carrier to perform complex multiplication. It is discriminated by the positions of two continuous symbols in this complex multiplication signal as to whether the values of two continuous symbols match with each other to generate serial data. The B-PSK period of a heirarchical transmission phase modulation signal is settled on the basis of the detection result of frame synchronism from this serial data, and the phase modulation signal in this period is used to reproduce a carrier, and this reproduced carrier is inputted to a complex multiplier 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation process for a digital satellite broadcast employing a hierarchical transmission system, and more particularly, to a required carrier (carrier) power / noise power (C / N).
Phase modulation with different ratio (PSK / Phase Shift Keying)
8-PSK, Q (Quadrature) -PSK, B (Binar
y) The present invention relates to a demodulation method and a digital demodulation device by digital processing of a phase modulation signal in hierarchical transmission in which -PSK is combined and repeatedly transmitted for each frame.

[0002]

2. Description of the Related Art Conventionally, in satellite digital communication and satellite digital broadcasting, it is difficult to enhance the stability of a frequency converter inside a repeater mounted on a satellite, and large frequency detuning tends to occur. Also, in a satellite digital communication / broadcast receiver, frequency conversion is performed by a simple circuit, so that frequency detuning tends to occur. For example, frequency detuning of 1.5 MHz may occur in frequency conversion in the 12 GHz band.

[0003] Therefore, in order to perform carrier regeneration for this frequency detuning, a frequency sweep (frequency sweep) of the carrier is performed. In the satellite broadcast receiver, the frequency sweep is performed after the power is turned on and after the tuning frequency is changed. In this process, when a frame synchronization signal is detected from the received signal, it is determined that the synchronization has been established, the frequency sweep is stopped, and a transition is made to the tracking state.

[0004] As BS satellite digital broadcasting, required C / N
Multiple phase modulation (PSK) schemes with different ratios, for example,
Hierarchical transmission schemes in which 8-PSK, Q-PSK, and B-PSK are combined and repeatedly transmitted for each frame are known. In such a layered transmission, the phase modulation portion of the lower layer, that is, the Q-PSK, B-PSK C
The reception performance is expanded up to the / N ratio. 8-PSK and BP
When the SK is compared, the B-PSK signal can be received at a lower C / N ratio, but is a layered transmission, so that a phase modulation portion of a lower layer under a low C / N ratio state, for example, , B-PSK, the carrier pull-in process is performed only during the B-PSK period.

FIG. 8 is a block diagram showing a configuration of a digital demodulator mounted on a conventional satellite broadcast receiver. FIG.
In this digital demodulator, a phase modulation signal input terminal 1, an in-phase detector 2, a quadrature detector 3, a local oscillator 4, a 90-degree phase shifter (shifter) 5, an A / D converters 6, 7, digital filters 8, 9, complex multiplier 10, frame synchronization detector 300, timing generator 11, frequency sweep controller 12, phase error detector 13, loop filter 14, an adder 15, a numerically controlled oscillator (NCO) 16, a cosine (COS) oscillator 17, a sine (SIN) oscillator 18, and demodulated signal output terminals 19 and 20.

FIG. 9 shows a frame synchronization detector 300 shown in FIG.
FIG. 3 is a block diagram showing the configuration of FIG. In FIG. 9, the frame synchronization detector 300 has input terminals 301 and 302.
, A 0-degree mapping converter 312a, a 45-degree mapping converter 312b, and a 90-degree mapping converter 312c.
, 135-degree mapping converter 312d, and serial-
Parallel (P / S) converters 305a, 305b, 305
c and 305d and match detection circuits 306a to 306h
, An OR circuit 307, a frame synchronization circuit 308, a synchronization pulse generation circuit 309, and output terminals 310 and 311.

Next, the operation of the digital demodulator mounted on the satellite broadcast receiver shown in FIG. 8 and the operation of the frame synchronization detector 300 shown in FIG. 9 will be described. 8 and 9, in this digital demodulator, a phase modulation signal (PSK) input to a phase modulation signal input terminal 1 is input to an in-phase detector 2 and a quadrature detector 3. The fixed-frequency oscillation signal from the local oscillator 4 and the oscillation signal
The oscillating signals shifted by 90 degrees by the phase shifter 5 are input to the detectors 2 and 3, respectively, and the I-axis and Q-axis baseband signals subjected to quadrature detection are output therefrom.

[0008] The I and Q baseband signals are A
The signals are input to the / D converters 6 and 7 and are sampled / quantized and converted into digital values. Further, the digital I and Q baseband signals are passed through digital filters 8 and 9, respectively, to shape the spectrum, and the baseband signals P and Q are output to complex multiplier 10.

[0009] Output signals (baseband signals) P and Q of the complex multiplier 10 are input to a frame synchronization detector 300 and a phase error detector 13. The phase error detector 13 detects the phase difference between the input phase modulation signal and the oscillation signal from the numerically controlled oscillator 16 described below by the modulation mode control signal imd from the timing generator 11 as described later. This phase error value pd is
Output to

The loop filter 14 is a timing generator 1
During the period when the timing signal tm from 1 is high level (logical value "1"), the phase error value pd from the phase error detector 13 is valid, and the timing signal tm is low level (logical value "0"). The phase error value pd is discarded during the period. The phase error value pd validated by the loop filter 14
Is smoothed and added by the adder 15 together with the carrier frequency offset value fd from the frequency sweep controller 12. This addition signal fc is input to the control input terminal of the numerically controlled oscillator 16.

The numerically controlled oscillator 16 is a cumulative addition circuit that does not inhibit overflow, and is oscillated by addition corresponding to the addition signal fc from the adder 15. The oscillation frequency in this case changes according to the value input to the control input terminal. An oscillation signal from the numerically controlled oscillator 16 branches and is input to the cosine oscillator 17 and the sine oscillator 18 to form a closed loop that returns to the complex multiplier 10 by performing processing based on the cosine characteristic and the sine characteristic. Carrier regeneration is performed.

The baseband signals P and Q from the complex multiplier 10 are also supplied to a frame synchronization detector 300 shown in FIG. 9, where a frame synchronization signal repeatedly superimposed on the phase modulation signal for each frame is detected. Perform The frame synchronization pulse fp from the frame synchronization detector 300
Is a timing signal that goes high when a frame synchronization signal is detected, and is input to the timing generator 11. Further, the frame synchronization detection signal sync from the frame synchronization detector 300 is a synchronization detection signal that goes to a high level when a frame synchronization signal is detected. This frame synchronization detection signal sync is input to the frequency sweep controller 12.

The timing generator 11 is in a state where frame synchronization has been established, and the phase error detector 13
When operating in modes other than PSK demodulation mode, B-PS
The modulation mode control signal imd for outputting the high-level phase error value pd to the loop filter 14 during the K period is output. Further, the timing generator 11 always outputs the high-level phase error value pd to the loop filter 14 when the phase error detector 13 operates in the 8-PSK demodulation mode regardless of the establishment of the frame synchronization. Output the modulation mode control signal imd.

The frequency sweep controller 12 outputs a carrier frequency offset value fd obtained by changing the oscillation frequency of the numerically controlled oscillator 16 at regular intervals, and receives a frame synchronization detection signal sync from the frame synchronization detector 300. In this case, the center frequency of the received signal input to the phase modulation signal input terminal 1 matches the carrier reproduction oscillation frequency, the carrier frequency offset value fd of the frequency sweep controller 12 is fixed, and the frequency sweep is performed. To stop.

The reception performance in B-PSK is 8-PS.
Reception at a C / N ratio lower than the reception performance at K is possible. Further, when receiving at a low C / N ratio, the carrier is reproduced with the phase modulation signal of the lower hierarchy. For example, a frame synchronization signal and hierarchical transmission information are modulated by B-PSK, and a video signal and an audio signal are 8-PSK, QP
Frames combined on the time axis by SK, B-PSK are repeatedly transmitted.

Therefore, when the lower layer portion is received in the layered transmission, in addition to the above-described operation, the first frequency sweep, that is, the phase error detector 13 outputs
Operate in PSK mode and use the frame sync detector 30
Until frame synchronization is detected at 0, the carrier frequency offset value fd output from the frequency sweep controller 12 changes stepwise to control the oscillation frequency of the numerically controlled oscillator 16.

After that, after the second frequency sweep, that is, the frame synchronization signal is detected by the frame synchronization detector 300, the phase error detector 13 operates in the B-PSK mode and the output from the timing generator 11 is output. Based on the timing signal tm, the loop filter 14 outputs the phase error value pd. Further, the frequency sweep controller 12 performs a frequency sweep from the carrier frequency offset value before the frame synchronization is detected in the first frequency sweep. When the frame synchronization is detected by the frame synchronization detector 300, the frequency sweep is stopped, the state shifts to the tracking state, and the demodulated signal output terminal 1
From 9 and 20, a PSK demodulated signal (baseband signal) is output.

Next, a conventional frame synchronization detecting operation will be described. FIG. 10 is a diagram for explaining IQ vectors. First, mapping in each phase modulation on the satellite transmitting side will be described. FIG. 10A shows 8-PS.
This is the symbol arrangement in K. In 8-PSK, a digital signal of 3 bits is transmitted by one symbol. The combination of these 3-bit digital signals is [000], [001]
To [111]. On the satellite transmitting side, IQ
On the vector plane, 0, 1, 2, 3, 4, 5,
6,7.

FIG. 10B shows the symbol arrangement in the case of Q-PSK. In Q-PSK, a 2-bit digital signal is transmitted with one symbol. The combination of the 2-bit digital signals is [00], [01], [10], [1]
1], and are arranged at 1, 3, 5, 7 on the IQ vector plane on the satellite transmitting side.

FIG. 10C shows the symbol arrangement in the case of B-PSK. B-PSK transmits a 1-bit digital signal with one symbol. On the satellite transmitting side, they are arranged at 0,4 on the IQ vector plane.

FIG. 11 is a diagram for explaining the carrier reproduction phase of 8-PSK. In FIG. 11, 8-PSK
In the case of (1), the signal arrangement is performed with the phase on the satellite transmitting side shown in FIG.
As shown in (1), carrier reproduction is performed in any one of eight phases.

In FIG. 11, (1) shows the same phase as the satellite transmitting side, (2) shows the phase rotated 45 degrees counterclockwise with respect to the satellite transmitting side, and (3) shows the phase. The phase on the satellite transmitting side and the phase rotated 90 degrees counterclockwise are shown. Also, (4) shows the phase on the satellite transmission side rotated 135 degrees counterclockwise, (5) shows the phase on the satellite transmission side rotated 180 degrees counterclockwise, (6) is 2 times counterclockwise with the phase on the satellite transmitter side.
The phase rotated by 25 degrees is shown. Also, (7) shows the phase on the satellite transmitting side rotated by 270 degrees counterclockwise, and (8) shows the phase on the satellite transmitting side by 3 degrees counterclockwise.
The phase rotated by 15 degrees is shown.

Next, the frame synchronization signal will be described. In the layered transmission, the frame synchronization signal has a required C
The signal is modulated with B-PSK having the lowest / N ratio. For example, 2
It is assumed that the data sequence of the frame synchronization signal composed of 0 bits is such that (b1, b2,..., B19, b20) are transmitted in the order from b1, and this data sequence is "111011".
“00110100101000” is repeated for each frame. On the satellite transmitting side, this data string is B-PSK
And is assigned to the signal arrangement of FIG. 10 (3).

The satellite broadcast receiver detects a frame synchronization signal in B-PSK. The phase-modulated signal received by this hierarchical transmission has signals other than the signal constellation points (0) and (4) of B-PSK shown in FIG. Perform Therefore, as described above, in 8-PSK, since the carrier is locked in any of the eight phases, each phase is monitored,
The determination of the symbol value “1” or “0” is performed. In addition,
The determination of “1” or “0” of the symbol is appropriately described as mapping conversion.

Next, the mapping conversion will be described in detail. FIG. 12 is a diagram for explaining a B-PSK determination boundary at the 8-PSK phase. In the case of 8-PSK, locking is performed in any of the eight phases as described above. At this time, B
In order to detect a frame synchronization signal in -PSK, it is determined whether the symbol value is "1" or "0" at the locked coordinates. FIG. 12 (1) (2) (3) (4) (5) (6)
(7) and (8) are 0 degree, 45 degree, 90 degree, respectively.
The symbol value determination regions for the 135 °, 180 °, 225 °, 270 °, and 315 ° phase rotations are shown.

For example, in the case of 45-degree phase rotation, FIG.
(2) applies. The symbol value is determined to be “1” when a symbol exists in a hatched area with the boundary line as a boundary, and the symbol value is determined to be “0” otherwise. Also, the 180-degree phase has an inverse relationship with the 0-degree phase, and similarly, the relationship between the 45-degree phase and the 225-degree phase,
Relationship between the degree phase and the 270 degree phase, and the 135 degree phase and 31
The relationship with the 5-degree phase is also the inverse relationship. In addition,
This mapping conversion can be performed by, for example, processing using a ROM.

Next, a detailed operation of the conventional frame synchronization detection 300 will be described with reference to FIG. FIG. 13 is a circuit diagram showing a detailed configuration of the match detection circuits 306a to 306d in FIG. In FIG. 9, the baseband signals P and Q output from the complex multiplier 10 are
01, 302, from which 0 degree mapping conversion circuit 312a, 45 degree mapping conversion circuit 313b, 9
The 0-degree mapping conversion circuit 312c and the 135-degree mapping conversion circuit 312d are input. Each of the mapping conversion circuits 313a to 313d determines "1" or "0", and determines that each data is serial-
Parallel (S / P) conversion circuits 307a, 307b, 30
7c and 307d, where the serial data is converted into parallel data.

Each parallel data is input to the coincidence detecting circuits 306a to 306h. Each of the coincidence detection circuits 306a to 306d has the same configuration as that shown in FIG. 13A, and includes a frame synchronization signal pattern "1110110011".
0100101000 ”is detected. On the other hand, the coincidence detection circuits 306e, 306f, 306g, and 306h
3 (2) has the same configuration as that of the frame synchronization signal, and has an inverted pattern “00010011001011010111”.
Is detected.

That is, the coincidence detecting circuit 306a detects the frame synchronization of the 0-degree phase, and
Reference numeral 06e performs frame synchronization detection with a phase of 180 degrees. Similarly, 306c to 306h respectively have a 45-degree phase, a 90-degree phase, a 135-degree phase, a 225-degree phase, and a 270-degree phase.
The frame synchronization detection is performed in the degree phase and the 315 degree phase. Each of the data input to the coincidence detection circuits 306a to 306h outputs a high level when the data coincides with the pattern of the frame synchronization signal. If they do not match, a low level is sent to the OR circuit 307.

When any one of the coincidence detecting circuits 306a to 306h outputs a high level, the OR circuit 30
The synchronization detection pulse dp of No. 7 outputs a high level and is input to the frame synchronization circuit 308 and the synchronization pulse generator 309. The frame synchronization circuit 308 outputs the synchronization detection pulse dp
Becomes a high level when it is confirmed that the signal has been received repeatedly every frame period.
Is generated and transmitted from the output terminal 310. When it is confirmed that the synchronization detection pulse dp has been repeatedly received in each frame period, the synchronization pulse generator 309 sends out a frame synchronization pulse fp which becomes a high level at the beginning of the frame period from the output terminal 311.

As described above, the conventional digital demodulator performs frame synchronization detection for eight phases in 8-PSK in order to detect a frame synchronization signal when performing carrier reproduction at a C / N ratio of a phase modulation portion of a lower hierarchy. A first frequency sweep to be performed and a second frequency sweep to perform carrier reproduction in the B-PSK mode are performed using received data in a phase modulation period of B-PSK after frame synchronization is detected.

There are a number of conventional examples relating to demodulation processing of this kind of phase modulation signal. For example, Japanese Patent Application Laid-Open No. H10-21529
No. 1 "broadcast receiver", JP-A-10-164164 "digital demodulator", JP-A-9-294151 "digital modulator / demodulator" and the like are known. In particular,
In the conventional example of No. 0-215291, the I / Q signal data of the detection output is arithmetically processed to determine the C / N ratio.
By varying the scanning step frequency based on the ratio, it is possible to receive a desired signal by high-speed AFC (automatic frequency control) with minimum scanning.

[0033]

As described above, in the above conventional example, since the frequency sweep is performed in two stages, there is a disadvantage that it takes time until the carrier reproduction is completed. Further, in the frame synchronization detection, the coincidence detection for eight phases is performed, and there is a disadvantage that the circuit scale becomes large.

The present invention solves the above-mentioned problems in the prior art. Even when a carrier frequency shift occurs in hierarchical transmission, the time required for carrier recovery can be reduced and the apparatus can be shortened. It is an object of the present invention to provide a demodulation method and a digital demodulation device by digital processing of a phase modulation signal that can suppress an increase in scale.

[0035]

In order to achieve the above object, the present invention provides a method of demodulating a phase-modulated signal by digital processing.
Digitally converting the signal, multiplying the I and Q signals by a reproduction carrier and performing complex multiplication, and based on the result of the complex multiplication, the same or the same two consecutive symbol values from two consecutive symbol positions. Determining a difference to generate serial data, determining a period of a phase modulation signal of the lowest speed transmission in the hierarchical transmission based on a detection result of frame synchronization from the serial data, and a phase in this period. Performing carrier regeneration using the modulated signal.

In order to determine whether the two consecutive symbols are the same or different, the distance between the two consecutive symbols is calculated, and the calculated distance between the symbols is compared with a preset threshold value. If the distance does not exceed the threshold value, it is determined that the symbol value is the same, or if the distance exceeds the threshold value, it is determined that the symbol value is different.

Further, as a determination of the same or a difference between the two consecutive symbols, the distance between the two consecutive symbols is calculated, and the symbol preceding the current symbol in the two consecutive symbols is rotated by 180 degrees. The distance between the symbol rotated by 180 degrees and the current symbol is calculated, the calculated two types of symbol distances are compared, and if the shortest distance is the distance of two consecutive symbols, the two consecutive symbols are the same. Or if the shortest distance is the distance between the symbol rotated by 180 degrees and the current symbol, it is determined that two consecutive symbols have different symbol values.

Further, in the frame synchronization detection, one of serial data generated by symbol determination or serial data composed of the most significant bit of the in-phase baseband signal is selected. After the frame synchronization is detected by the selected serial data, and the frame synchronization is detected by the frame synchronization detection, the frame data is detected by selecting the serial data including the most significant bit of the in-phase baseband signal. .

Further, the hierarchical transmission is performed when the carrier power /
8-PSK, Q-PSK, BP with different noise power ratios
This is hierarchical transmission by SK, and the phase modulation signal of the lowest speed transmission is B-PSK.

The digital demodulation apparatus of the present invention demodulates a phase modulated signal in hierarchical transmission, detects a quadrature detection of the input phase modulated signal, and converts the I and Q signals from the detection means into digital values. A / D conversion means for conversion, complex multiplication means for multiplying I and Q signals from the A / D conversion means by respective reproduction carriers to perform complex multiplication, and two consecutive symbols in the complex multiplication output of the complex multiplication means Symbol conversion means for determining the same or different between two consecutive symbol values from the position and generating serial data;
Frame synchronization detection means for detecting frame synchronization from the serial data from the symbol conversion means; and a period in the phase modulation signal of the lowest speed transmission in the hierarchical transmission based on the detection result of the frame synchronization detection means. And a reproduction processing unit for transmitting a reproduction carrier to the complex multiplication unit using the modulation signal.

As the symbol conversion means, two consecutive
A calculating unit for calculating the distance between two consecutive symbols for determining the same or different symbols is compared with a distance between symbols calculated by the calculating unit and a preset threshold value. A configuration is provided that includes a comparing unit for determining the same symbol value when the threshold value is not exceeded or determining a different symbol value when the threshold value is exceeded.

Further, the symbol conversion means includes: a first calculator for calculating a distance between two consecutive symbols for determining the same or different two consecutive symbols;
A second calculator for calculating a distance between the current symbol and a symbol obtained by rotating the symbol immediately before the current symbol in two consecutive symbols calculated by the calculator by 180 degrees, and a first and second calculator for calculating a distance between the current symbol and the current symbol; The two types of inter-symbol distances are compared, and if the shortest distance is the result of calculation by the first calculation unit,
A comparison unit is provided for determining that the symbols have the same symbol value, or determining that two consecutive symbols have different symbol values when the shortest distance is the result of calculation by the second calculation unit. .

Further, the frame synchronization detecting means includes a selecting section for selecting one of the serial data generated by the symbol determination or the serial data consisting of the most significant bit of the in-phase baseband signal. After the frame synchronization is detected by the frame synchronization detection, the serial data consisting of the most significant bit of the in-phase baseband signal is selected to perform the frame synchronization detection. And a selection / detection unit that performs the following.

Also, the phase modulation signal of the lowest speed transmission in the reproduction processing means is B-PSK, and the hierarchical transmission is
8-PSK with different required carrier power / noise power ratio,
The configuration is such that hierarchical transmission is performed using Q-PSK and B-PSK.

Further, a digital filtering means for shaping the spectrum of the I and Q signals from the A / D conversion means and outputting it to the complex multiplication means is further provided.

Further, the above-mentioned digital demodulation device is configured to be provided in a satellite digital receiving device for receiving satellite digital broadcasting.

The demodulation method and digital demodulation apparatus of the present invention for digitally processing a phase-modulated signal can be applied to the phase-modulated signal of the lowest-speed transmission even when frequency detuning occurs in the phase-modulated signal by hierarchical transmission. The frame synchronization signal period in (B-PSK) is detected, and this period is specified. Carrier reproduction is performed using data of the period of the phase modulation signal (B-PSK) of the lowest speed transmission. As a result, the time until carrier regeneration is reduced.

In the present invention, the frame synchronization is detected by detecting the frame synchronization of only two phases (0 degrees / 180 degrees). As a result, frame synchronization detection is facilitated, and it is possible to suppress an increase in the device scale.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a demodulation method and a digital demodulation apparatus for digitally processing a phase modulated signal according to the present invention will be described in detail with reference to the drawings. In the following text and figures, the same components as those in FIGS. 8 and 9 are denoted by the same reference numerals. In the respective drawings of this embodiment, the same functional components are denoted by the same reference numerals. FIG. 1 is a block diagram illustrating a configuration of a digital demodulation method and a digital demodulation device of a phase modulation signal according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the symbol converter 100 in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the frame synchronization detector 200 in FIG.

In FIG. 1, the digital demodulator comprises a phase modulation signal input terminal 1, an in-phase detector 2, a quadrature detector 3, a local oscillator 4, and a 90-degree phase shifter (shifter).
5, A / D converters 6, 7 and digital filters 8, 9
, A complex multiplier 10, a symbol converter 100, a frame synchronization detector 200, a timing generator 11 as reproduction processing means, a frequency sweep controller 12, a phase error detector 13, a loop filter 14, , Adder 15
, A numerically controlled oscillator (NCO) 16 and a cosine (CO
An S) oscillator 17 and a sine (SIN) oscillator 18 as well as demodulated signal output terminals 19 and 20 are provided.

In FIG. 2, the symbol converter 10 of FIG.
0 indicates baseband input terminals 101 and 102, one-symbol delay units 103a and 103b as calculation units, subtractors 104a and 104b, and multipliers 105a and 105b.
And an adder 106. Further, it has a threshold setting terminal 107, a comparator 108, a modulo 2 circuit 109, and a one-symbol delay unit 110 as a comparison unit, and further includes a serial data output terminal 111.

Referring to FIG. 3, a frame synchronization detector 200
Are input terminals 201 and 202, a selector 203 as a selection unit, a mode input terminal 204, a serial-parallel (S / P) converter 205 as a selection / detection unit,
Inverter 206, match detection circuits 207a, 207b
, An OR circuit 208, a frame synchronization circuit 209, and a synchronization pulse generation circuit 210, and further includes a synchronization detection output terminal 211 and a frame pulse output terminal 212.

FIG. 4 is a block diagram showing another configuration example (symbol converter 100A) of the symbol converter 100 of FIG. In FIG. 4, this symbol converter 100A
Baseband input terminals 101 and 102, first and second
One-symbol delay units 103a and 103b as calculation units
And subtracters 104a, 104b, 104c, 104d
And multipliers 105a, 105b, 105c, 105d
, Adders 106a and 106b, a comparator 108 as a comparing unit, a modulo 2 circuit 109,
A symbol delay unit 110 and a minus (-) 1 multiplier 11
5a, 115b, and a serial data output terminal 111.

FIG. 5 shows the symbol converter 100A shown in FIG.
It is a block diagram which shows the structure of the modification of FIG. In this example, baseband input terminals 101 and 102, one-symbol delay units 103a and 103b as calculation units, and a multiplier 105
a, 105b, and an adder 106, and includes a sign bit extraction circuit (SIGN) 112 as a comparison unit, a modulo 2 circuit 109, a one-symbol delay unit 110, and a serial data output terminal 111. Have been.

Next, the operation of this embodiment will be described. In FIG. 1, a phase modulation signal (PSK) input to a phase modulation signal input terminal 1 is input to an in-phase detector 2 and a quadrature detector 3. To the detectors 2 and 3, together with the phase modulation signal (PSK), the oscillation signal of the local oscillator 4 and the oscillation signal whose phase has been shifted by 90 degrees by the 90-degree phase shifter 5 are input. From this, quadrature detected I-axis and Q-axis baseband signals are output.

The baseband signals of the I and Q axes are A /
The baseband signals P, which are input to the D converters 6 and 7 and converted into digital values by sampling / quantization and passed through digital filters 8 and 9 to limit the band, respectively.
Q is input to the complex multiplier 10. Output signals (baseband signals) P and Q of the complex multiplier 10 are input to the symbol converter 100 and the phase error detector 13. The symbol converter 100 determines the correlation of two symbols from the inter-code distance between two consecutive symbols, generates binary serial data, and outputs the serial data to the frame synchronization detector 200.

The frame synchronization detector 200 receives the serial data sd from the symbol converter 100 and the serial data consisting of the most significant bit of the in-phase signal (baseband signal P) output from the complex multiplier 10. m
p is input, and one of the serial data sd and mp is selected by a modulation mode control signal imd from the timing generator 11 described below, and a frame synchronization signal that is repeatedly superimposed on each received frame is detected. I do.

The frame synchronization pulse fp from the frame synchronization detector 200 is a timing signal that goes high during the period when the frame synchronization signal is detected, and is input to the timing generator 11. Also, the frame synchronization detector 2
The frame synchronization detection signal sync starting from 00 is a frame synchronization detection signal that goes high when a frame synchronization signal is detected, and is output to the frequency sweep controller 12.

The timing generator 11 outputs the modulation mode control signal imd to the frame synchronization detector 200, the phase error detector 13, and the frequency sweep controller 12. The modulation mode control signal imd allows the serial data sd from the symbol converter 100 to be input as serial data to the frame synchronization detector 200 at an initial stage, that is, at the start of the carrier reproduction process after power is turned on or after the tuning frequency is switched. And the phase error detector 13 operates in the higher hierarchy mode.

Further, the timing generator 11 outputs a control signal so that the operation of the frequency sweep control unit 12 stops. Thereafter, when the frame synchronization pulse fp is input from the frame synchronization detector 200, the timing generator 11 outputs the modulation mode control signal imd. By the modulation mode control signal imd, the serial data m from the complex multiplier 10 to the frame synchronization detector 200 is output.
It is controlled to select p. Further, in response to the modulation mode control signal imd from the timing generator 11, the phase error detector 13 operates in the lower hierarchy mode, and outputs a control signal for performing the frequency sweep operation by the frequency sweep controller 12.

Further, the frequency sweep controller 12 outputs a carrier frequency offset value fd for changing the frequency of the oscillation signal in the numerically controlled oscillator 16 at regular intervals. Note that the frequency sweep controller 12 outputs a fixed value when the modulation mode control signal imd output from the timing generator 11 is in the initial stage control, and the frequency sweep controller 12 is performing a frequency sweep, And a frame synchronization detection signal s from the frame synchronization detector 200
When "ync" is input, the center frequency of the received signal input to the phase modulation signal input terminal 1 matches the carrier reproduction oscillation frequency, the output signal is fixed, and the frequency sweep operation is stopped.

On the other hand, the phase error detector 13 uses the modulation mode control signal imd from the timing generator 11 to
In addition to controlling the demodulation mode of the higher hierarchy or the lower hierarchy, a phase error value pd indicating a phase error between the received signal and the oscillation signal of the numerically controlled oscillator 16 is detected and output to the loop filter 14. The loop filter 14 validates the phase error value pd from the phase error detector 13 during a high-level period in the timing signal tm from the timing generator 11, and the phase error value pd during a period when the timing signal tm is at a low level. Is destroyed. Further, the loop filter 14 smoothes the phase error value pd and outputs it to the adder 15.

Further, the phase error value pd from the loop filter 14 and the carrier frequency offset value fd from the frequency sweep controller 12 are added by the adder 15 and input to the control input terminal of the numerically controlled oscillator 16. The oscillation signal of the numerically controlled oscillator 16 is input to a cosine oscillator 17 and a sine oscillator 18, performs processing based on cosine characteristics and sine characteristics, forms a closed loop returning to the complex multiplier 10, and performs carrier regeneration.

Next, the operation of the symbol converter 100 will be described. FIG. 6 is a diagram for explaining the operation of the symbol converter 100. In FIG. 6, two consecutive symbols here represent a symbol at time t at point A (P1, Q
1) and the symbol at time t + 1 is point B (P2, Q2)
And The rotation angle θ of two consecutive symbols is
This is caused by the frequency detuning of the center frequency of the received signal and the carrier reproduction. Considering the phase modulation of B-PSK, when the frequency detuning is zero (0), the symbol position at the time t + 1 is the same point A as the time t or the point A 'obtained by rotating the point A by 180 degrees. I do. However, the symbol position at time t + 1 is located at point B or B 'due to frequency detuning. That is, with reference to the point A at the time t, the time t +
By calculating the distance from the symbol position at 1
It is possible to determine the same or different points A and B.

Further, the operation of the symbol converter 100 is shown in FIG.
This will be described with reference to FIG. Baseband input terminals 101, 1
02 are input to the subtracter 1
04a, 104b and subtracters 104a, 104 through one symbol delayers 103a, 103b.
b. The subtraction output signals of the subtracters 104a and 104b are input to the multipliers 105a and 105b, respectively, are subjected to a square operation, and are added by the adder 106.

That is, the addition output signal of the adder 106 indicates the square value of the distance between two consecutive symbols.
The addition output signal of the adder 106 is input to a comparator 108 and compared with a threshold value th preset in a threshold value setting terminal 107. When the value of the adder 106 does not exceed the threshold value th, the comparator 108 inputs "0", and in other cases, "1" is input to the modulo 2 circuit 109, while the output symbol of the modulo 2 circuit 109 is , 1
The signal is supplied to another input terminal of the modulo 2 circuit 109 through the symbol delay unit 110.

In this case, if the distance between two consecutive symbols does not exceed the threshold th, the same symbol is output from the serial data output terminal 111 as the value one symbol before, and the distance between the two consecutive symbols is increased. When the threshold value th is exceeded, the symbol is output from the serial data output terminal 111 as an inverted value of the previous symbol. That is, even if the received signal has frequency detuning, the symbol converter 100 specifies the frame synchronization signal period and determines its BP
The SK period can be specified.

In the frame synchronization detector 200 shown in FIG. 3, the serial data sd generated by the symbol converter 100 is input to an input terminal 201, and the baseband signal P output from the complex multiplier 10 is input to an input terminal 202. Is input from the MSB. The serial data sd and the baseband signal P are supplied to the selector 203 and the mode input terminal 2
In 04, one of the serial data sd and mp is selected by the modulation mode control signal imd supplied from the timing generator 11. The serial data sd or mp selected by the selector 203 is sent to the coincidence detection circuit 207a through the serial-parallel converter 205,
Further, the coincidence detecting circuit 207b through the inverter 206
Is input to

The match detection circuits 207a and 207b output a high level when the input data matches the frame synchronization signal pattern, and output a low level to the OR circuit 208 when they do not match. Match detection 207a,
When one of 207b outputs a high level, the OR circuit 208 outputs a high level, and the frame synchronization circuit 20 outputs a high level.
9 and the frame synchronization pulse generation circuit 210.

When the frame synchronization circuit 209 can confirm that the synchronization detection pulse dp has been repeatedly received for each frame period, the frame synchronization circuit 209 outputs a high-level frame synchronization detection signal s.
The sync signal is generated and output through the synchronization detection output terminal 211. The frame synchronization pulse generation circuit 210 outputs the frame synchronization pulse fp which becomes a high level at the beginning of the frame period through the frame pulse output terminal 212 when confirming that the synchronization detection pulse dp is repeatedly received every frame period. I do.

FIG. 7 is a diagram for explaining the operation of symbol conversion 100A shown in FIG. In FIG. 7, the symbol position at time t is point A (P1, Q1) and the symbol position at time t + 1 is point B (P2, Q2). The rotation angle θ of two consecutive symbols is caused by the frequency detuning of the center frequency of the received signal and the carrier reproduction. Considering the phase modulation of B-PSK, when the frequency detuning is zero (0), the symbol position at time t + 1 is the same as point A or point A at time t by 180.
This is point A 'rotated by degrees.

Here, the time t + 1 is obtained by frequency detuning.
Is located at point B. If the symbol value of point A is “1”, A ′ obtained by rotating point A by 180 degrees
The symbol value at the point (-P1, -Q1) is "0". B
The points (P2, Q2) are point A (P1, Q1) and point A '(-
P1 or −Q1), the symbol value of the symbol B point is determined.

In FIG. 4, in symbol converter 100A, baseband signals P and Q input to baseband input terminals 101 and 102 are subtracted by subtractors 104a and 104, respectively.
b, 104c and 104d, and a subtracter 104 through one symbol delayers 103a and 103b.
a, 104b. Subtractors 104a, 104b
Are output from multipliers 105a and 105b, respectively.
, And then added by the adder 106a. That is, the addition output signal of the adder 106a indicates the square value of the distance between the two consecutive symbol A points (P1, Q2) and B (P2, Q2).

On the other hand, one-symbol delay units 103a and 103
The delayed output signal b is also input to subtracters 104c and 104d through -1 multipliers 115a and 115b.
It is squared by the multipliers 105c and 105d. Thereafter, the addition is performed by the adder 106b. That is, the addition output signal of the adder 106b is a continuous symbol A point (P1, Q
1) At point B (P2, Q2), the symbol A point is
The square value of the distance between the point A 'and the point B rotated by degrees is shown. The output signals of the adders 106a and 106b are
8 and the addition output value of the adder 106a is
If the sum is equal to or smaller than the addition output value of 06b, the comparator 108 outputs “0” to the modulo 2 circuit 109. Otherwise, “1” is output to the modulo 2 circuit 109.

On the other hand, the output signal of modulo 2 circuit 109 is passed through 1 symbol delay unit 110 to modulo 2 circuit 1
09 is input to another input terminal. That is, when the point obtained by rotating the point A by 180 degrees between two consecutive symbols A and B is defined as A ′, if “the square of the distance AB ≦ the square of the distance A′B”, the point B is obtained. Is output from the serial data output terminal 111 as the previous value, that is, the same value as the output one symbol before, from the serial data output terminal 111.
In the case of "the square of the distance A'B", the symbol value at the point B is output through the serial data output terminal 111 as the inversion of the previous value, ie, the inversion of the output one symbol before.

According to this configuration, when the received signal has frequency detuning, the period of the frame synchronization signal can be specified, and the B-PSK period can be specified.

In FIG. 5, this symbol converter 100
A is a modification of the configuration shown in FIG. The square of the two-symbol distance AB and the two of the distance A'B described in FIG.
The power value can be obtained by the following equations (1) and (2).

The square value of the distance AB = (P2−P1) ² + (Q2−Q1) ² (1) The square value of the distance A′B = (P2 + P1) ² + (Q2 + Q1) ² (2)

The processing in the comparator 108 determines the magnitude of the calculation results of (Equation 1) and (Equation 2). That is, the operation of "(Equation 1)-(Equation 2)" is performed. this is,
This is the distance difference ΔL, and this calculation is represented by the following equation (3).

ΔL = −4 × (P1 × P2 + 4 × Q1 × Q2) (3)

In the other example of the configuration of the symbol converter 100 shown in FIG. 1 shown in FIG.
It is also possible to take out the sign bit of the operation result of the above.

In FIG. 5, the baseband input terminal 10
The baseband signals P and Q from the complex multiplier 10 are input to 1, 102, respectively, from which 1-symbol delay units 103a and 103b and multipliers 105a and 105b are respectively input.
Is input to The baseband signals P and Q are passed through the one-symbol delay units 103a and 103b to the multipliers 105a and 105a.
105b. The multipliers 105a and 105b are:
Multiplication is performed on the baseband signals P and Q of two consecutive symbols, and further added by the adder 106. That is, the adder 106 performs addition corresponding to “P1 × P2 + Q1 × Q2”.

The output signal of adder 106 is input to sign bit extraction circuit (SIGN) 112. The sign bit extraction circuit (SIGN) 112 modulates “1” into a modulo 2 circuit 1 when the addition output signal of the adder 106 is “ΔL> 0”.
09, and the addition output signal of the adder 106 becomes “ΔL ≦
At the time of “0”, “0” is output to the modulo 2 circuit 109. The output signal of the modulo 2 circuit 109 is input to another input terminal of the modulo 2 circuit 109 through the one-symbol delay unit 110.

As a result, the modulo 2 circuit 109
Similarly to the above configuration, when the position obtained by rotating the point A by 180 degrees between the two consecutive symbols A and B is defined as the point A ′, “the square of the distance AB ≦ the square of the distance A′B” If,
The symbol value at point B outputs the previous value, that is, the same value as the output one symbol before, from the serial data output terminal 111. If “the square of the distance AB> the square of the distance A′B”, the modulo 2 circuit 109 inverts the symbol value of the point B to the previous value, that is, inverts the output signal one symbol before. Output from the serial data output terminal 111.

According to this configuration, when a frequency detuning occurs in the received signal, the frame synchronization signal period can be specified, and the B-PSK period can be specified.

As described above, in this embodiment, the B-PSK period is specified by detecting the frame synchronization period from the phase modulation signal in which the frequency detuning has occurred, and the BP is determined.
Carrier reproduction can be performed using the data in the SK period.

In this embodiment, the symbol converter 100 (100A) receives the baseband signal from the complex multiplier 10, but operates in the same manner even if it receives the signals from the digital filters 8 and 9. The configuration in this case is also included in the present invention.

[0088]

As is apparent from the above description, according to the demodulation method and the digital demodulation apparatus for digitally processing a phase-modulated signal of the present invention, a case where frequency detuning occurs in a phase-modulated signal by hierarchical transmission. Also, the frame synchronization signal period in the phase modulation signal of the lowest speed transmission is detected, and carrier reproduction is performed using the data of the period of the phase modulation signal of the lowest speed transmission. As a result, the time until carrier regeneration can be reduced.

In the present invention, the frame synchronization is detected by detecting the frame synchronization of only two phases (0 degrees / 180 degrees). As a result, frame synchronization detection is facilitated, and it is possible to suppress an increase in the device scale.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration according to a digital demodulation method and a digital demodulation device of a phase modulation signal according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a symbol converter in FIG.

FIG. 3 is a block diagram showing an internal configuration of a frame synchronization detector in FIG.

FIG. 4 is a block diagram showing a modification of another configuration example of the symbol converter of FIG. 1;

FIG. 5 is a block diagram showing a configuration of a modification of the symbol converter shown in FIG.

FIG. 6 is a diagram illustrating an operation of symbol conversion in the embodiment.

FIG. 7 is a diagram for explaining the operation of the symbol converter shown in FIG.

FIG. 8 is a block diagram showing a configuration of a digital demodulator mounted on a conventional satellite broadcast receiver.

FIG. 9 is a block diagram showing a configuration of a frame synchronization detector in FIG.

FIGS. 10 (1) to (3) are diagrams for explaining IQ vectors in a conventional example.

11 (1) to (8) show 8-PS in a conventional example.
FIG. 4 is a diagram for explaining a carrier reproduction phase of K.

FIGS. 12 (1) to (8) show 8-PS in a conventional example.
FIG. 9 is a diagram for explaining a B-PSK determination boundary in a K phase.

FIG. 13 is a circuit diagram showing a configuration of a match detection circuit in FIG. 9;

[Explanation of symbols]

 2,3 detector 4 local oscillator 5 90 degree phase shifter (shifter) 6,7 A / D converter 8,9 digital filter 10 complex multiplier 11 timing generator 12 frequency sweep controller 13 phase error detector 14 loop Filter 15 Adder 16 Numerically Controlled Oscillator (NCO) 17 Cosine (COS) Oscillator 18 Sine (SIN) Oscillator 100, 100A Symbol Converter 103a, 103b 1 Symbol Delayer 104a-104d Subtractor 105a-105d Multiplier 106, 106a, 106b adder 108 comparator 109 modulo 2 circuit 110 1 symbol delay unit 112 sign bit extraction circuit (SIGN) 115a, 115b -1 multiplier 200 frame synchronization detector 203 selector 205 serial-parallel converter 206 inverter 207a 207b coincidence detection circuit 208 OR circuit 209 frame synchronization circuit 210 frame synchronization pulse generation circuit dp synchronization detection pulse fd carrier frequency offset value fp frame synchronization pulse imd modulation mode control signal mp, sd serial data P, Q baseband signal pd phase error value sync frame synchronization detection signal tm timing signal

Claims (12)

[Claims] 1. A method of demodulating a phase-modulated signal by digital processing in hierarchical transmission, comprising the steps of: digitally converting I and Q signals obtained by quadrature detection of an input phase-modulated signal; Performing a complex multiplication on the basis of the result of the complex multiplication, determining the same or different values of two consecutive symbols from two consecutive symbol positions based on the result of the complex multiplication, and generating serial data; Determining a period of the phase modulation signal of the lowest speed transmission in the hierarchical transmission based on the detection result of the synchronization, and performing carrier regeneration using the phase modulation signal in this period. Demodulation method by digital processing of phase modulation signal. 2. A method for determining the identity or difference between two consecutive symbols, calculating a distance between two consecutive symbols, comparing the calculated inter-symbol distance with a preset threshold value, and comparing the symbols by this comparison. 2. The phase modulation according to claim 1, wherein if the inter-distance does not exceed the threshold value, the symbol value is determined to be the same, or if the inter-distance exceeds the threshold value, the symbol value is determined to be different. Demodulation method by digital processing of signal. 3. A method for determining whether two consecutive symbols are the same or different includes calculating a distance between two consecutive symbols and determining two consecutive symbols.
The symbol before the current symbol in the symbol is set to 180
The distance between the symbol rotated by 180 degrees and the current symbol is calculated, and the calculated distances between the two types of symbols are compared with each other. If two symbols have the same symbol value, or if the shortest distance is the distance between the symbol rotated by 180 degrees and the current symbol, it is determined that two consecutive symbols have different symbol values. 2. The demodulation method according to claim 1, wherein the phase modulation signal is digitally processed. 4. The frame synchronization detection selects either serial data generated by symbol determination or serial data consisting of the most significant bit of an in-phase baseband signal, and in the first frame synchronization detection, generates by symbol determination. And performing frame synchronization detection by selecting the selected serial data, and after detecting frame synchronization by the frame synchronization detection, selecting serial data consisting of the most significant bit of the in-phase baseband signal and performing frame synchronization detection. The demodulation method according to claim 1, wherein the phase modulation signal is digitally processed. 5. The hierarchical transmission according to claim 1, wherein the carrier power / noise power ratio differs between 8-PSK, Q-PSK, and B-PSK.
2. The demodulation method according to claim 1, wherein the phase modulation signal of the lowest speed transmission is B-PSK. 6. A digital demodulator for demodulating a phase modulated signal in hierarchical transmission, a detecting means for performing quadrature detection on the input phase modulated signal, and an A / D converter for converting I and Q signals from the detecting means into digital values. D conversion means, complex multiplication means for multiplying the I and Q signals from the A / D conversion means by reproduction carriers, respectively, and performing complex multiplication;
Symbol conversion means for determining the same or different between two consecutive symbol values from the symbol position to generate serial data; frame synchronization detection means for detecting frame synchronization from the serial data from the symbol conversion means; A reproduction processing unit that determines a period in the phase modulation signal of the lowest speed transmission in the hierarchical transmission based on the detection result of the detection unit, and sends a carrier reproduced using the phase modulation signal in this period to the complex multiplication unit, A digital demodulator characterized by comprising: 7. A calculating unit for calculating a distance between two consecutive symbols for determining the same or a difference between two consecutive symbols as the symbol conversion unit, and a distance between the symbols calculated by the calculating unit is determined in advance. To compare with a set threshold value, determine that the symbol value is the same when the distance between symbols does not exceed the threshold value, or determine that the symbol value is different when the distance exceeds the threshold value 7. The digital demodulation device according to claim 6, further comprising: a comparison unit. 8. A first calculating unit for calculating a distance between two consecutive symbols for determining whether two consecutive symbols are the same or different, as the symbol conversion unit, and a continuation calculated by the first calculating unit. A second calculator for calculating the distance between the current symbol and the symbol obtained by rotating the symbol immediately before the current symbol in the two symbols by 180 degrees, and two types of symbols calculated by the first and second calculators The distances are compared, and two consecutive symbols are determined to have the same symbol value when the shortest distance is the result of calculation by the first calculating unit, or continuous when the shortest distance is the result of calculation by the second calculating unit. The digital demodulation device according to claim 6, further comprising: a comparing unit configured to determine that two symbols have different symbol values. 9. A frame synchronization detecting means, comprising: a selection unit that selects one of serial data generated by symbol determination or serial data composed of the most significant bit of an in-phase baseband signal; After the frame synchronization is detected by the frame synchronization detection, the serial data consisting of the most significant bit of the in-phase baseband signal is selected to perform the frame synchronization detection. The digital demodulation device according to claim 6, further comprising: a selection / detection unit that performs the following. 10. The phase-modulated signal of the lowest speed transmission in the reproduction processing means is B-PSK, and the hierarchical transmission is performed by using 8-PSK, QP having different carrier power / noise power ratios.
7. The digital demodulation device according to claim 6, wherein the transmission is layered transmission using SK and B-PSK. 11. The digital demodulation device according to claim 6, further comprising digital filtering means for shaping the spectrum of the I and Q signals from said A / D conversion means and outputting the result to a complex multiplication means. . 12. The method according to claim 6,7,8,9,10,1.
A digital demodulation device, wherein the digital demodulation device according to 1 is provided in a satellite digital reception device for receiving satellite digital broadcasting.