JP2001022575A - Microcomputer with external bus control function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer which can eliminate the redundant waiting time between a CPU and a BCU and improves its total processing throughput. SOLUTION: A CPU 10 is prepared to issue an instruction with a single clock pitch together with a BCU 20 including a bus clock generation means 24 which inputs a CPU clock to be supplied to the CPU 10 as a BCU drive clock signal and then generates and outputs a bus clock BUSCLK having a cycle of >=2 times and also an integer multiple as much as the BCU drive clock signal. The means 24 outputs the bus clock only in its bus cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to an information processing apparatus such as a microcomputer, and more particularly, to a microcomputer having a bus control unit.

[0002]

2. Description of the Related Art Bus control unit
t; abbreviated as “BCU”) will be described with reference to FIG. Referring to FIG. 4, this conventional microcomputer has a CP
CPU 10 configured to issue an instruction in one clock period of U clock, and two clock cycles of CPU 10
And a bus control unit ("BCU") 20A for driving the external bus at a cycle of an integral multiple of twice or more.

A clock generator 30 generates and outputs a clock for driving the CPU 10 (referred to as “CPU clock”). A signal obtained by dividing the CPU clock output from the clock generator 30 by a frequency divider 35 is It is supplied to the BCU 20A as a clock for driving the BCU (referred to as “BCU drive clock”).

The CPU 10 accesses the external bus 40 via the BCU 20A, and accesses the external memory 60 or the I / O device 70 via the external circuit input / output control device 50 connected to the external bus 40. A signal obtained by dividing the CPU clock output from the clock generator 30 by the frequency divider 35 is supplied to the external circuit input / output control device 50 as its drive clock (CLKOUT).

[0005] The BCU 20A includes a BCU control unit 21A,
The CPU 10 includes a data / address control unit 22 and a bus cycle start (BCYST) signal generation unit 23.
When the bus cycle request 13 is input to the BCU control unit 21A, the bus cycle start signal generation unit 23 indicates the start of the bus cycle in synchronization with the BCU drive clock under the control of the BCU control unit 21. The bus cycle start signal (BCYST) is supplied to the external circuit input / output control device 50.
Output to Thus, the bus clock (CLKOU)
T) is a microcomputer whose cycle is an integral multiple of at least twice the cycle of the internal clock (CPU clock),
For example, a document (“User's Manual V830 ^TM 3
2-bit microprocessor hardware μP
D705100 ", December 1997 (NEC).

The CPU 10 shown in FIG. 4 is a CPU of a pipeline control system having an instruction decoder 11 and an execution unit 12. As typical pipeline control, for example, as schematically shown in FIG. 6, the operation is fetched in an instruction fetch (IF) stage and stored in an instruction queue or the like, and in an instruction decode (ID) stage, The instruction is taken out of the instruction queue and decoded, and in the instruction execution (EX) stage, the decoded instruction is executed and, if necessary, an effective address is calculated based on the address field of the operand of the instruction code (“ Calculation CPU pipeline),
In the next memory access (MEM) stage, memory access or I / O device access is performed (also referred to as a “bus access CPU pipeline”), and in the write back (WB) stage, an ALU operation instruction, a load instruction, etc. The execution result is set in an internal register. For the pipeline, for example, refer to the literature (JL Hennessy &
DA Patterson, "COMPUTER ARCHTECTURE A QUANTA
TIVE APPROACH ", MORGAN KAUFMANN PUBLISHERS, INC.
1990, p. 252). As shown in FIG. 6, the preceding instruction and the next instruction are executed simultaneously in different pipeline stages, thereby speeding up the processing.

[0007]

By the way, in this conventional microcomputer system, the CPU 10
When accessing the external memory 60 or the I / O device 70 from the CPU 10, since the BCU 20A is driven by a clock obtained by dividing the CPU clock, the CPU 10
While the bus cycle request is issued to the BCU 20A in the clock period, the BCU 20A receives the bus cycle request and then starts executing the bus cycle control.
According to the phase of the drive clock, it is necessary to wait for at least one clock cycle of the CPU clock, and a redundant idle cycle is consumed. This will be described in detail below.

FIG. 5 is a timing chart showing an example of a bus access timing operation of the microcomputer shown in FIG. Referring to FIG. 5, in a clock cycle t1, the CPU 10 executes the load instruction input to the EX stage (operational CPU pipeline stage) of the pipeline to execute the bus from the execution unit 12 at the timing (a). Access request 1
3 is output to the BCU 20A.

The BCU drive clock is a clock obtained by dividing the CPU clock by 4 by the frequency divider 35, and is a BCU 20A
Captures the bus access request 13 output from the CPU 10 at the falling edge of the BCU driving clock, and therefore captures the bus access request 13 at the falling edge of the BCU driving clock at the start of the clock cycle t5 ((( b)), a clock cycle t5 starts a bus cycle, in this case, a read operation corresponding to a load instruction.

That is, the BC at the timing (b) in FIG.
The bus cycle start signal generation circuit 24 outputs a bus cycle start (BCYST) signal in synchronization with the falling edge of the U drive clock.

The external circuit input / output control unit 50 driven by the clock CLKOUT output from the frequency divider 35
Is the clock CLKOUT at the start of clock cycle t7
The bus cycle start (BCYST) signal is detected to be active at the rising edge of timing (timing (c) in FIG. 5), and the bus cycle operation is started.
The read operation is performed for a total of six clock cycles from cycle t6 to t12 in units of clock.

In this read operation, an address signal output from the CPU 10 is sent to the address bus of the external bus 40 via the BCU control unit 21A and the data / address control unit 21 of the BCU 20A, and the external circuit input / output control unit 50 Fetches an address signal, accesses the external memory 60 or the I / O device 70 based on the address signal, and transfers data read from the external memory 60 or the I / O device 70 to the data bus of the external bus 40. The BCU 20A is connected to the external bus 40
From the BCU control unit 21A to the CPU
The data is passed to 10.

By the way, as is apparent from FIG.
The execution of the load instruction in the stage (CPU pipeline stage for operation) causes a bus access request to be sent to the CPU 10.
(Timing (a)) and before the BCU detects this and starts the bus cycle (timing (b)), a redundant idle period of up to three clock cycles measured by the CPU clock (T2, t3, t
4) is inserted.

That is, the load instruction input to the arithmetic CPU pipeline stage (EX stage) in clock cycle t1 cannot be input to the bus access CPU pipeline stage in the next clock cycle, and is the longest. After waiting for a redundant idle period (t2, t3, t4) for three clock cycles in the CPU pipeline stage for operation, the clock cycle t5
Is input to the bus access CPU pipeline stage, and the read operation by the bus access CPU pipeline stage (MEM stage) is performed until the clock cycle t12.

As a result, the data by the load instruction is transferred to CP
In the case where the data is taken into the U side, each time, the CPU clock waits for three cycles at the maximum, and on average waits for 1.5 cycles, thereby lowering the throughput of the entire processing.

As described above, when the CPU accesses the external memory and the I / O device via the external bus, the CP
The configuration is such that the BCU is driven by a clock obtained by dividing the U clock.
Even if a bus cycle request is issued to U, if there is a deviation in the timing of the BCU drive clock, a redundant idle cycle for queuing is consumed, and as a result,
This delays the start of execution of the external bus cycle,
CPU throughput decreases.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and a main object of the present invention is to provide a microcomputer which eliminates redundant waiting time between a CPU and a BCU and improves the throughput of the entire processing. Is to do. Other objects, features, advantages, etc. of the present invention will be readily apparent to those skilled in the art from the following description.

[0018]

In order to achieve the above object, a bus control device according to the present invention receives a clock signal supplied to a CPU as a drive clock signal, and has a period of at least twice the period of the drive clock signal; A bus clock generating means for generating and outputting a bus clock having a cycle that is an integral multiple of the cycle is provided, and the bus clock is supplied to an input / output control circuit connected to the bus. In the present invention, the bus clock generating means outputs the bus clock only during a bus cycle.

Further, an information processing apparatus according to the present invention comprises: a CPU;
A bus clock generating means for inputting a CPU clock supplied to the CPU as a drive clock signal and generating and outputting a bus clock having a cycle that is at least twice the cycle of the drive clock signal and an integral multiple of the cycle; A bus control unit.

In the present invention, the bus clock generating means outputs the bus clock only during a bus cycle. Further, the bus clock generating means, when a bus cycle request is output from the CPU, outputs a bus clock that is at least twice the cycle of the drive clock signal and has a cycle that is an integral multiple of the cycle, The bus clock is
The logic value is set to a predetermined logic value at the start of the bus cycle and at the end of the bus cycle.

In the present invention, the bus control unit includes a bus cycle start signal generating means for outputting a bus cycle start signal in synchronization with the drive clock when receiving a bus access request from the CPU.

Further, in the present invention, the CPU comprises:
The pipeline is configured to issue an instruction in one clock period of the CPU clock, and the bus cycle starts from the CPU clock cycle after the bus access request is output from the CPU.

[0023]

Embodiments of the present invention will be described. In a preferred embodiment of the present invention, the bus control unit (referred to as "BCU") (20) transmits a CPU clock supplied to the CPU (10) capable of issuing an instruction in one clock period to a driving clock signal ("BCU"). And a bus clock generating means (24) for generating and outputting a bus clock (BUSCLK) having a cycle of at least twice the cycle of the BCU drive clock signal and an integral multiple of the cycle. . The bus clock generating means (24) preferably outputs a bus clock (BUSCLK) only during a bus cycle.

The BCU (20) includes a bus cycle start signal generating means (23) for outputting a bus cycle start signal in synchronization with the BCU drive clock when receiving a bus access request from the CPU (10).

In the present invention, the bus clock (BUSCLK) from the bus clock generating means (24) is connected to the external bus (40), and performs input / output with the external memory (60) and the input / output device (70). The bus cycle start signal from the bus cycle start signal generating means (23) is supplied as a drive clock for the external circuit input / output control device (50) to be controlled.
0) and is used for defining the operation timing from the beginning of the bus cycle in the external circuit input / output control device (50).

In the present invention, a bus cycle start (BCYST) signal is output from the next CPU clock cycle after the bus access request is output from the CPU (10), and the bus cycle is started. As in the prior art described with reference to FIGS. 4 and 5, there is no redundant cycle for phase alignment, and the execution performance of load / store instructions and the like is improved.

Further, the microcomputer of the present invention has a C
The PU (10) and the BCU (2) which control sending of address signals and data signals from the CPU to the external bus (40) and control of taking in of data from the external bus (40).
0), the BCU (20) is a microcomputer that accesses an external memory (60) and an input / output device (70) via an external circuit input / output control device (50) connected to an external bus (40). , A CPU supplied from a clock generation means (30) to the CPU (10)
The clock is directly input as a drive clock signal, and a bus clock (BUSCLK) having a cycle that is at least twice the cycle of the drive clock signal and an integral multiple of the cycle is generated, and during the bus cycle period, the bus clock is generated. A bus clock generating means (24) for supplying a drive clock to an external circuit input / output control device (50), and a CPU (10)
When a bus access request (13) is received from the CPU, the bus cycle start signal (BCYS) is synchronized with the drive clock.
Bus cycle start signal generating means (23) for outputting T)
And.

In a preferred embodiment of the microcomputer of the present invention, the bus clock generating means (2)
4) includes a frequency dividing means for generating a clock having a cycle that is twice or more the cycle of the BCU driving clock signal and an integral multiple of the cycle during the bus cycle period and outputting the generated clock as a bus clock; The output of the means, that is, the bus clock (BUSCLK) is set to a predetermined logical value (fixed value) at the start and end of the bus cycle.

In a preferred embodiment of the microcomputer of the present invention, the CPU (10)
The pipeline configuration is such that an instruction is issued at one clock period of a clock, and a bus cycle is started from a CPU clock cycle next to a time point when a bus access request is output from the CPU.

[0030]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, in one embodiment of the present invention, a clock generator 30 for generating a clock (referred to as a “CPU clock”) to be supplied to a CPU
The same clock as the clock supplied to the CPU 10 is supplied as it is to the U20 as a drive clock (hereinafter, referred to as “BCU drive clock”).

The BCU 20 has a BCU control unit 21 which interfaces with the CPU and controls the entire BCU.
, A data / address control unit 22, and a bus clock (C
LKOUT) and a bus that generates a bus cycle start signal that is activated in synchronization with the beginning of the bus cycle to notify the external circuit input / output control device 50 and the like of the start timing of the bus cycle. A cycle start signal generator 23.

The bus clock (BUS) from the bus clock generation unit 24 and the bus cycle start signal generation unit 23
CLk) signal, bus cycle start signal (BCYS)
T) is input to the external circuit input / output control device 50, and the external circuit input / output control device 50 receives the bus clock (BUSCL).
K) The input bus cycle start signal (BCYST) driven by the signal is used to specify the elapsed time from the start of the bus cycle, and executes a predetermined processing operation at predetermined timing from the start of the bus cycle. I do.

In one embodiment of the present invention, an external memory 60 and / or an I / O device 70 are connected to the external circuit input / output control device 50 as in the configuration shown in FIG.
The CPU 10 accesses the external memory 60 or the I / O device 70 via the BCU 20, the external bus, and the external circuit input / output control device 50.

In one embodiment of the present invention, BCU2
0 is driven by a BCU drive clock having the same cycle as the input CPU clock.
A bus clock signal having a cycle of an integral multiple of two or more CU drive clock cycles is generated and output to the external circuit input / output control device 50.

FIG. 3 is a diagram showing an example of the configuration of the bus clock generator 24 in one embodiment of the present invention. Referring to FIG. 3, bus clock generation unit 24 receives an enable signal output from BCU control unit 21 that has received bus cycle request 13 output from CPU 10 and is active during the bus cycle period, and generates a BCU drive clock. A gate circuit 24-1 that passes the
And a frequency dividing circuit 24-2 which receives the BCU drive clock transmitted through the input port and divides the clock to output a bus clock (BUSCLK).

In this embodiment, the frequency dividing circuit 24-2 has
It is configured as a quaternary counter that divides the CU drive clock by 4, that is, a first counter that receives the BCU drive clock as an input
, And a second toggle flip-flop which receives an output of the first toggle flip-flop as an input, and a bus clock (BUSCLK) is output from the output of the second toggle flip-flop. The toggle flip-flop is a JK flip-flop in which the J and K terminals are set to “1”, or
It is composed of a D-type flip-flop or the like that feedback-inputs the inverted output terminal Q # to the data input terminal (D) and outputs the non-inverted output terminal Q.

When the frequency divider circuit 24-2 receives the bus cycle request 13, its output is set to "1" at the start of the bus cycle by the set signal output from the BCU controller 21. , CPU clock (BCU)
Each time two driving clocks are input, the value is inverted, and the BCU controller 2
1 by the set signal output from the frequency dividing circuit 24-2.
Is set to "1" again. The frequency dividing circuit 24-2 forcibly set by the set signal is configured by connecting two stages of a JK flip-flop with a preset function (which functions as a T-type flip-flop) that inputs a set signal to a preset terminal.

The enable signal output from the BCU control unit 21 to the bus clock generation unit 24 is active during the bus cycle, and the BCU control unit 21
10 when the bus cycle request 13 is output, and
A set signal is output when the bus cycle ends. In the case where the number of clock cycles of the bus cycle is determined in advance in the BCU control unit 21, the count may be counted by a counter and an enable signal may be output during the bus cycle. When the ready signal is output, the end of the bus cycle may be detected and the enable signal may be set to inactive.

Thus, the bus clock generator 24
Is the bus clock (BUSC) only during the bus cycle operation.
LK) and not output except for bus cycle operation.
It outputs a so-called intermittent clock.

The bus cycle request signal is sent to the CPU 10
The bus cycle start signal generation circuit 23 receives a signal from the BCU control unit 21 input from the CPU and outputs a bus cycle start signal (BCYST). The bus cycle start signal generation circuit 24 can be composed of, for example, a one-shot pulse signal generation circuit.

FIG. 2 is a timing chart for explaining the timing operation of one embodiment of the present invention. In addition,
The CPU 10 shown in FIG.
As a typical pipeline configuration, as in the conventional CPU described with reference to FIGS. 4 and 6, an IF stage for fetching instructions, an ID stage for decoding instructions, EX stage for calculation (referred to as “CPU pipeline for operation”), ME for memory access or access to I / O device
The description will be made assuming that the M stage (referred to as “CPU pipeline for bus access”), a write back (WB) stage for setting the execution result of an ALU operation instruction and a load instruction in an internal register.

Referring to FIG. 2, clock cycle t1
Then, the load instruction is input to the arithmetic execution CPU pipeline stage, and the bus access request 13 is output to the BCU 20 at the timing (a). The BCU drive clock is a clock having the same cycle and the same phase as the CPU clock, and the BCU control unit 21 of the BCU 20 captures the bus access request output from the CPU 10 at the rising edge of the BCU drive clock.

As shown in FIG. 2, at the start of the next clock cycle t2 when the bus access request is output, that is, at the timing of the rising edge of the BCU drive clock (timing (b) in FIG. 2), the BCU controller 21 of the BCU 20 operates.
Captures the bus access request 13, the load instruction shifts to the bus access CPU pipeline stage from clock cycle t 2, and the bus cycle (read operation corresponding to the load instruction in this case) starts from clock cycle t 2.

At the rising edge (b) of the BCU driving clock, the bus cycle start signal generating circuit 23 outputs a bus cycle start signal (BCYST) consisting of a one-shot pulse.

The external circuit input / output control device 50 that operates on the bus clock (BUSCLK) outputs a clock cycle t4.
At the falling edge (c) of the bus clock (BUSCLK), the bus cycle start signal (BCYST) is detected to be active, the bus cycle operation is started, and six clock cycles from the clock cycle t4 to t9 are performed. A read operation is performed. That is, the CPU 10
From the BCU controller 2 of the BCU 20
1. External bus 40 via data / address control unit 22
Of the external circuit I / O controller 5
0 fetches an address signal, and the external memory 60 or I
Access to the I / O device 70 and the external memory 6
0 or data read from the I / O device 70 is sent to the data bus of the external bus 40, the BCU 20 fetches the data, and transfers the read data to the CPU 10.

In one embodiment of the present invention, as shown in FIG. 2, when a bus access request is output from CPU 10 by execution of a load instruction (clock cycle t).
The bus cycle starts immediately from the clock cycle (t2) following 1), and there is no idle period, thereby improving the throughput of the entire process.

That is, the load instruction input to the arithmetic CPU pipeline stage at clock cycle t1 is changed to the bus access CP at clock cycle t2.
There is no waiting time (redundant idle period) as shown in FIG. 5 between the input to the U pipeline stage and the issuance of the bus cycle request to the start of the bus cycle, and the processing performance is improved.

The bus clock (BUSCLK) is
It is reset to “0” at the start of the bus cycle, and the external circuit input / output control device 50 sets the bus clock (BUCLK)
At the rising edge of the bus cycle start signal.

The BCU driving clock for driving the BCU may have the same cycle as the CPU clock and may have a phase opposite to that of the CPU clock.

According to one embodiment of the present invention, even if the CPU issues a bus cycle request to the BCU in one clock period, no deviation occurs between the phase of the BCU driving clock and the phase timing of the start of the external bus cycle. Therefore, as in the related art, the redundant cycle from the issuance of the bus cycle request to the start of the bus cycle is deleted, and the processing performance is improved.

[0052]

As described above, according to the present invention,
There is an effect that a redundant cycle does not occur at the timing of issuing a bus cycle request and starting a bus cycle, thereby improving processing performance.

The reason is that, in the present invention, the CP
This is because a CPU clock supplied to U is input as a driving clock signal, and a bus clock generating means for generating and outputting a bus clock having a cycle that is twice or more and an integral multiple of the cycle of the driving clock signal is provided.

Further, according to the present invention, since the bus clock is supplied to the external circuit input / output control device only during the bus cycle, there is an effect that the power consumption of the system is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining a bus cycle operation according to one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a bus clock generation circuit according to one embodiment of the present invention.

FIG. 4 is a diagram showing a system configuration of a conventional microcomputer.

FIG. 5 is a timing chart showing a bus cycle operation of a conventional microcomputer.

FIG. 6 is a schematic diagram for explaining a pipeline operation.

[Explanation of symbols]

 Reference Signs List 10 CPU 11 Instruction decoder 12 Instruction execution unit 13 Bus cycle request (signal) 20 BCU 21 BCU control unit 22 Data address control unit 23 Bus cycle start signal generation unit 24-1 Gate 24-2 Divider (counter) 24 Bus clock Signal generator 30 Clock generator 40 External bus 50 External circuit input / output controller 60 External memory 70 I / O device

Claims (11)

[Claims] 1. A bus clock for inputting a clock signal supplied to a CPU as a drive clock signal and generating and outputting a bus clock having a cycle that is at least twice the cycle of the drive clock signal and an integral multiple of the cycle. A bus control device comprising: generating means for supplying the bus clock to an input / output control circuit connected to a bus. 2. The bus control device according to claim 1, wherein said bus clock generating means outputs said bus clock only during a bus cycle. 3. A CPU and a CPU supplied to the CPU
A bus control unit including a bus clock generating means for inputting a clock as a drive clock signal and generating and outputting a bus clock having a cycle that is at least twice the cycle of the drive clock signal and an integral multiple of the cycle. An information processing apparatus, characterized in that: 4. The information processing apparatus according to claim 3, wherein said bus clock generating means outputs said bus clock only during a bus cycle. 5. The CPU according to claim 1, wherein said bus clock generating means includes a CPU.
Outputs a bus clock that is at least twice the cycle of the drive clock signal and has a cycle that is an integer multiple of the cycle when the bus cycle request is output from the bus cycle request. 5. The information processing apparatus according to claim 3, wherein a logic value is set to a predetermined logic value at the end of the cycle. 6. A bus cycle start signal generating means for outputting a bus cycle start signal in synchronization with the drive clock when the bus control unit receives a bus access request from the CPU. The information processing apparatus according to any one of claims 3 to 5. 7. A drive clock for an input / output control device connected to a bus to which the bus control unit is connected and for controlling input / output with an external memory and an input / output device. And a bus cycle start signal from the bus cycle start signal generating means is supplied to the input / output control device, and is used for defining an operation timing from the beginning of the bus cycle in the input / output control device. 7. The information processing apparatus according to claim 6, wherein: 8. A pipeline configuration in which the CPU issues an instruction at one clock period of a CPU clock,
C at the time when the bus access request is output from the CPU
8. The information processing apparatus according to claim 3, wherein a bus cycle is started from a CPU clock cycle subsequent to the PU clock cycle. 9. A CPU, a bus control unit for controlling transmission of an address signal and a data signal from the CPU to an external bus, and control of taking in of data from the external bus,
A microcomputer that accesses an external memory and an input / output device via an external circuit input / output control device connected to the external bus, wherein the bus control unit is supplied to the CPU from a clock generation unit. The CPU clock is directly input as a drive clock signal, and a bus clock having a cycle that is at least twice the cycle of the drive clock signal and an integral multiple of the cycle is generated. Bus clock generation means for supplying a drive clock for an external circuit input / output control device; and bus cycle start signal generation means for outputting a bus cycle start signal in synchronization with the drive clock when receiving a bus access request from the CPU. And a microcomputer comprising: 10. The bus clock generating means generates a clock having a cycle that is twice or more the cycle of the drive clock signal and an integral multiple of the cycle during a bus cycle, and outputs the clock as the bus clock. 10. The microcomputer according to claim 9, further comprising frequency dividing means, wherein an output of said frequency dividing means is set to a predetermined logical value at a start time of a bus cycle and an end time of a bus cycle. 11. A pipeline structure in which the CPU issues an instruction at one clock period of a CPU clock, and a bus is issued from a CPU clock cycle following a CPU clock cycle at the time when a bus access request is output from the CPU. 10. The microcomputer according to claim 9, wherein a cycle is started.