JP2001021612A - Manufacture of semi-conductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out inspection by activating the logic circuit of a semi-conductor chip by increasing the power cycle. SOLUTION: This semiconductor device is constituted of an aging substrate 3 for loading plural semi-conductor packages 1 through sockets, an aging signal impressing part 4 for transmitting a pulse signal 4a for aging through a connecting material 3a provided at the aging substrate 3, a power source impressing part 5 for transmitting a pulse signal 5a for a power source through the connecting terminal 3a to the aging substrate 3, a pulse oscillator 6 for oscillating the pulse signal, and a deceleration counter 7 for switching the pulse signal with high frequencies to that with low frequencies, and the power source impression is carried out by the pulse signal 5a for a power source, and a logic circuit 2d of the semiconductor chip 2 is activated so that the aging of the semiconductor chip 2 can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to an increase in the number of power cycles in an aging process.

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

In an aging step, for example, in an inspection step of a semiconductor manufacturing process, an aging device (also called a burn-in device) is used to screen for initial failure of a logic circuit of a semiconductor chip by aging in a power cycle.

In this aging device, a power cycle is generated every few minutes.

That is, for example, aging is performed while switching the power on / off of the DC power supply at intervals of several minutes using a timer or the like.

In the semiconductor device defect inspection process, a static power supply current test (this is also called an I _DDQ test) is performed. At this time, the potential of the input pin of the semiconductor chip is set to H level.
When the power supply is turned on and off repeatedly as a pseudo standby state fixed to any state of (high level) / L (low level), a static power supply current may flow for the first time at the hundredth on.

It can be inferred that a defect at a deep portion of the logic circuit is first activated to either H / L at that time.

[0008] The aging device is described in, for example, "Electronic Materials November Issue,
Ultra LSI Manufacturing / Testing Equipment Guidebook <1999 Edition>, published November 25, 1998, pages 197 to 199.

[0009]

However, in the aging device of the above-mentioned technology, a timer or the like is used to
For example, aging is performed for a total of 48 hours while switching on / off the input by the DC power supply at a cycle of 3 minutes.

In this case, the number of power-on operations during 48 hours is 960. Considering that the quiescent power supply current flows for the first time at the hundredth turn-on in the quiescent power supply current test, aging for screening is performed. The problem is that the number of power-on times in the device is extremely small.

In other words, when the number of power-on operations is about 960 after aging for 48 hours, insufficient screening is required, especially for aging of a semiconductor chip having a large-scale logic circuit.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a power cycle is increased to activate a logic circuit of a semiconductor chip to perform a test.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a method of manufacturing a semiconductor device according to the present invention includes a step of applying a test pulse signal to a signal electrode of a semiconductor chip and a step of applying a power pulse signal to a power electrode of the semiconductor chip. In addition, a power supply is applied by the power supply pulse signal to activate a logic circuit of the semiconductor chip, thereby inspecting the semiconductor chip.

As a result, since the power cycle is repeated in a short cycle by the pulse signal, an H / L state can be formed even in a cell or the like on the circuit in order. Therefore, the signal is transmitted to a deep cell in the logic circuit of the semiconductor chip. Can be reached.

As a result, the activation rate of the logic circuit of the semiconductor chip can be improved.

Further, the method of manufacturing a semiconductor device according to the present invention includes a step of applying an aging pulse signal to a signal electrode of a semiconductor chip, and a step of applying a power pulse signal to a power supply electrode of the semiconductor chip. And performing an aging test on a logic circuit of the semiconductor chip by applying power using the power pulse signal.

Further, a method of manufacturing a semiconductor device according to the present invention
The frequency of the inspection pulse signal is a high frequency, and the frequency of the power supply pulse signal is a low frequency that is much lower than the frequency of the inspection pulse signal.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a conceptual diagram showing an example of a configuration of a main part of an aging device used in a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention, and FIG.
FIG. 3 is a conceptual diagram showing an example of an arrangement state of semiconductor packages on an aging substrate used in the aging apparatus shown in FIG. 3, and FIG. 3 is a process flowchart showing an example of a manufacturing process of the semiconductor device of the present invention.

The aging device used in the method of manufacturing a semiconductor device according to the first embodiment is also called a burn-in device. In the inspection process of the semiconductor manufacturing process, as shown in FIG. It is used in the burn-in process between the sorting and the secondary sorting.

The configuration of the aging apparatus shown in FIG. 1 will be described. An aging board (inspection board) 3 on which a plurality of (for example, 12 in FIG. 2) semiconductor packages (semiconductor devices) 1 can be mounted via a socket 8. An aging signal applying unit 4 for transmitting an aging pulse signal (inspection pulse signal) 4a to the aging substrate 3 via a connection terminal 3a provided on the aging substrate 3, and a power supply pulse to the aging substrate 3 via the connection terminal 3a A power supply applying unit 5 for transmitting a signal 5a, a pulse oscillator 6 for oscillating a pulse signal, and a deceleration counter 7 for switching a high-frequency pulse signal to a low frequency. The aging test of the semiconductor chip 2 is performed by activating the second logic circuit 2d.

As shown in FIG. 2, a plurality of (here, 12) semiconductor packages 1 (for example, SOP (Small Outline Package) and QFP)
(Semiconductor devices such as a Quad Flat Package), so that a corresponding number of sockets 8 are attached, and similar electrical signals (eg, aging pulse signal 4a and power pulse signal 5a) are mounted on each socket 8. Wiring and electrical connection are performed so that an electrical signal of the

That is, the signal electrode 2a, the power supply electrode 2b and the GND electrode 2c of each semiconductor chip 2 are connected via the signal pin 1a, the power supply pin 1b and the GND pin 1c which are external terminals of each semiconductor package 1, respectively. The semiconductor package 1 is electrically connected to the aging substrate 3, whereby the 12 semiconductor packages 1 can be aged at the same time.

The logic circuit 2d of the semiconductor chip 2
A group of a plurality of logic cells 2e and a flip-flop 2f
It is composed of

The aging device according to the first embodiment activates the logic circuit 2d of the semiconductor chip 2 by applying the power pulse signal 5a to the power electrode 2b of the semiconductor chip 2, thereby activating the logic circuit of the semiconductor chip 2. The signal is made to reach the cell 2e at a deep portion of the circuit 2d, and as a result, the activation rate of the logic circuit 2d of the semiconductor chip 2 is improved to perform the inspection.

In the aging device, for example,
A high-frequency pulse signal having a period of several us to several ns is oscillated from the pulse oscillator 6, and the high-frequency pulse signal directly enters the aging signal application unit 4 and is aged as it is as an aging pulse signal 4 a (inspection pulse signal). It is transmitted to the substrate 3 (FIG. 1 shows three types of high-frequency signals as an example of the aging pulse signal 4a).

On the other hand, the power supply unit 5 includes a pulse oscillator 6
Is converted by the deceleration counter 7 into a low-frequency signal having a period of several ms (for example, 10 Hz).
It is transmitted to the aging substrate 3 as a.

Therefore, the aging pulse signal 4a
And the power supply pulse signal 5a
Is set as the low frequency which is much lower than the frequency of the aging pulse signal 4a. At the time of aging, the high frequency aging pulse signal 4a and the low frequency power supply pulse signal 5a are transmitted.

For example, assuming that the frequency of the power supply pulse signal 5a is 10 Hz, aging for 48 hours is 173.
You can power on 10,000 times.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to a flow chart of manufacturing steps shown in FIG.

The method for manufacturing the semiconductor device is described in FIG.
The following aging device is used.

First, in the pre-process of step S1 shown in FIG.
Is performed on which a wafer is formed.

Thereafter, a probe test shown in step S2 is performed.

Subsequently, a post-process (step S3) in the semiconductor manufacturing process is performed to assemble the semiconductor package 1 including the semiconductor chip 2.

Further, the primary sorting shown in step S4 is performed to remove the defective semiconductor package 1.

Thereafter, a burn-in test shown in step S5, that is, aging is performed on the semiconductor package 1 determined to be non-defective in the primary sorting.

First, the semiconductor package 1 incorporating the semiconductor chip 2 is placed on an aging substrate 3 (inspection substrate). That is, the semiconductor package 1 is attached to the socket 8 of the aging board 3.

Thereafter, aging is started.

In the aging, the aging pulse signal 4a is applied from the aging signal applying section 4 to the signal electrode 2a of the semiconductor chip 2 in the semiconductor package 1, and the power applying section 5 is applied to the power supply electrode 2b of the semiconductor chip 2.
From the power supply pulse signal 5a.

At this time, in the aging device of the first embodiment, a high-frequency pulse signal having a period of several us to several ns is oscillated from the pulse oscillator 6, and the high-frequency pulse signal is directly input to the aging signal application unit 4. Is transmitted to the aging substrate 3 as the aging pulse signal 4a as it is.

On the other hand, the power supply unit 5 includes a pulse oscillator 6
A high-frequency pulse signal with a period of several us to several ns input from the
z) is converted into a low frequency, and this low frequency is transmitted to the aging substrate 3 as a power supply pulse signal 5a.

Therefore, the aging pulse signal 4a
And the power supply pulse signal 5a
Is set to the low frequency which is much lower than the frequency of the aging pulse signal 4a, and at the time of aging, the high frequency aging pulse signal 4a and the low frequency power supply pulse signal 5a are transmitted.

Thus, for example, the power pulse signal 5
If the frequency of a is 10 Hz and aging is performed for 48 hours, power-on (power-on) can be performed 1.73 million times.

As a result, by using the aging device shown in FIG. 1, power is applied by the power pulse signal 5a, so that the logic circuit 2d of the semiconductor chip 2 is activated to perform aging of the semiconductor chip 2. it can.

The semiconductor package 1 is screened by the aging.

That is, the semiconductor package 1 having a latent defect can be removed.

Thereafter, a non-defective semiconductor package 1 is selected (acquired) by performing the secondary selection shown in step S6.

According to the method of manufacturing a semiconductor device of the first embodiment, the following operational effects can be obtained.

That is, the power supply electrode 2b of the semiconductor chip 2
By applying the power supply pulse signal 5a to the power supply, the logic circuit 2d of the semiconductor chip 2 can be activated by applying the power supply by the power supply pulse signal 5a, and the semiconductor chip 2 can be inspected. Since the power cycle of the power supply is repeated in a short cycle by the signal 5a, an H (high level) / L (low level) state can be sequentially formed in the cells 2e and the like on the circuit, whereby the logic circuit 2d of the semiconductor chip 2 can be formed. Deep cell 2
e can reach the signal.

As a result, the logic circuit 2d of the semiconductor chip 2
Activation rate can be improved.

The frequency of the aging pulse signal 4a (inspection pulse signal) is, for example, a high frequency of several us to several ns, and the frequency of the power pulse signal 5a is
For example, the number of power cycles of the power supply in the inspection can be greatly increased by using a low frequency having a period of several ms (for example, about 10 Hz) which is much lower than the frequency of the aging pulse signal 4a.

Therefore, the inspection of the semiconductor chip 2 is an aging inspection as in the first embodiment. For example, when a conductive foreign substance or the like exists between wirings of a deep portion of the logic circuit 2d of the semiconductor chip 2, the inspection is performed. It is possible to increase the probability that the wiring at both ends can be activated to be at the H / L potential.

As a result, an electrical short circuit occurs between the wirings, and as a result, the product can be removed as a defect in the electrical characteristic test in the next step.

Therefore, it is possible to efficiently screen a defect at a deep portion of the logic circuit 2d as an initial failure.

In particular, it is possible to sufficiently screen the semiconductor chip 2 having the large-scale (for example, mega-gate or higher) logic circuit 2d.

As a result, the quality of the semiconductor chip 2 or the semiconductor package (semiconductor device) 1 having the same can be improved.

In the method of manufacturing a semiconductor device according to the first embodiment, the case of a cell 2e provided in a deep portion of a logic circuit 2d which is activated for the first time by powering on thousands or tens of thousands of times is described. The voltage stress application time becomes extremely short, but by raising the power supply or raising the temperature within a range that does not destroy the circuit, it is possible to compensate for the occurrence of defects not to be reduced.

(Embodiment 2) FIG. 4 is a conceptual diagram showing an example of a configuration of a main part of an aging apparatus for wafer burn-in used in a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention, and FIG. FIG. 5 is an enlarged partial cross-sectional view illustrating an example of a probe needle contact state during aging using the aging device illustrated in FIG. 4.

The aging apparatus of the first embodiment is for aging the semiconductor package (semiconductor device) 1 after assembling, whereas the aging apparatus of the first embodiment is used for a method of manufacturing a semiconductor device of the second embodiment. The aging apparatus shown in FIG. 4 ages the semiconductor chips 2 on the semiconductor wafer 9.

That is, aging is performed at the wafer level before dicing.

The semiconductor wafer 9 to be aged in the second embodiment may be one in which individual semiconductor chips 2 cut by dicing are assembled into a semiconductor package 1 or may be a semiconductor wafer in a previous step. 9
May be assembled into a semiconductor device called a wafer process package in which a redistribution layer is formed on the surface of the substrate and bump electrodes serving as external terminals are further formed.

The configuration of the aging device according to the second embodiment shown in FIG. 4 will be described.

In the aging device shown in FIG. 4, the aging signal application unit 4, the power supply application unit 5, the pulse oscillator 6, and the deceleration counter 7 are the same as those of the first embodiment.
Since it is the same as the aging device described in the above section, the description thereof will not be repeated.

Therefore, the aging apparatus shown in FIG. 4 comprises a wafer stage (inspection stage) 10 on which a semiconductor wafer 9 can be mounted, a plurality of probe needles 11 which are brought into contact with the electrodes of the semiconductor wafer 9 during aging, and a plurality of probe needles. And a probe needle support board 12 for supporting the probe needle 11.

As a result, the aging device of the second embodiment applies the power pulse signal 5 to each semiconductor chip 2 in the wafer state, similarly to the aging device of the first embodiment.
a of the logic circuit 2 of the semiconductor chip 2
The aging test of the semiconductor chip 2 is performed by activating d.

The wafer stage 10 has a function that can set a high temperature.

The other structure of the aging device used in the method of manufacturing the semiconductor device of the second embodiment shown in FIG. 4 is the same as that of the aging device shown in FIG. 1 described in the first embodiment. Duplicate description is omitted.

In the method of manufacturing a semiconductor device according to the second embodiment, only differences from the method of manufacturing a semiconductor device of the first embodiment will be described.

First, among the steps shown in FIG. 3, for example,
In the probe inspection shown in step S2, as shown in FIG. 4, on the wafer stage 10 set at a predetermined temperature,
A semiconductor wafer 9 on which a plurality of semiconductor chips 2 are formed is arranged.

Thereafter, as shown in FIG. 5, a plurality of probe needles 11 attached to the probe needle support board 12 are connected to each surface electrode 2 of the semiconductor chip 2 on the semiconductor wafer 9.
g (bump electrode which is an external terminal in the case of the wafer process package).

In this state, aging is performed on each semiconductor chip 2 of the semiconductor wafer 9 placed on the wafer stage 10 by applying power using the power pulse signal 5a, as in the first embodiment. .

Thus, similar to the first embodiment,
For example, when the frequency of the power supply pulse signal 5a is 10 Hz, aging for 48 hours enables power-on (power-on) of 1.730 million times.

As a result, by using the aging device of the second embodiment shown in FIG.
Since the power supply is performed by a, the logic circuit 2d (see FIG. 1) of the semiconductor chip 2 in the wafer state can be activated to age the semiconductor chip 2.

The other method in the method of manufacturing the semiconductor device according to the second embodiment is the same as that described in the first embodiment, and the description thereof will not be repeated.

Further, the operation and effect obtained by the method of manufacturing a semiconductor device according to the second embodiment are the same as those of the method of manufacturing a semiconductor device according to the first embodiment, and thus redundant description will be omitted.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the first and second embodiments, the case where the inspection is aging has been described. However, the inspection may be a failure analysis of the semiconductor chip 2 other than the aging.

That is, as the failure analysis, for example,
When using a liquid crystal analysis method for analyzing I _DDQ current leak failure or an analysis method using an emission microscope, power is applied by the pulse signal described in the first and second embodiments.

At this time, a failure analysis pulse signal is applied as a test pulse signal to the signal electrode 2 a of the semiconductor chip 2, and a power supply pulse signal 5 a is applied to the power supply electrode 2 b of the semiconductor chip 2. Perform failure analysis.

Thus, even in the case of the failure analysis, the inspection can be performed by activating the logic circuit 2d of the semiconductor chip 2.

In the first and second embodiments,
A case has been described in which a pulse signal is input from one pulse oscillator 6 to both the aging signal application unit 4 and the power supply application unit 5, but pulse signals may be input from separate pulse oscillators 6 respectively. By using a pulse oscillator 6 that oscillates a pulse signal of a low frequency of about 10 Hz as a member for sending a pulse signal to the power supply unit 5, the power supply unit can be directly supplied from the pulse oscillator 6 without using the deceleration counter 7 shown in FIG. A low frequency pulse signal of about 10 Hz may be input to 5.

[0084]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1). By applying a power pulse signal to the power electrode of the semiconductor chip, it is possible to activate the logic circuit of the semiconductor chip by applying power by the power pulse signal and to inspect the semiconductor chip. In such a case, an H / L state can be formed, so that a signal can reach a deep cell in a logic circuit of a semiconductor chip. As a result, the activation rate of the logic circuit of the semiconductor chip can be improved.

(2). By setting the frequency of the inspection pulse signal to a high frequency and setting the frequency of the power supply pulse signal to a low frequency that is much lower than the frequency of the inspection pulse signal, wiring at a deep portion of a logic circuit of a semiconductor chip during an aging inspection is performed. When there is a conductive foreign substance or the like in between, it is possible to increase the probability that the wiring at both ends can be activated to be at the H / L potential. As a result, an electrical short circuit occurs between the wirings, and as a result, the product can be removed as a defect in an electrical characteristic test in the next step.

(3). According to the above (2), it is possible to efficiently screen a defect at a deep part of the logic as an initial failure. As a result, it is possible to improve the quality of the semiconductor chip or the semiconductor device having the same.

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram illustrating an example of a configuration of a main part of an aging device used in a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a configuration conceptual diagram showing an example of an arrangement state of semiconductor packages on an aging substrate used in the aging device shown in FIG.

FIG. 3 is a process flow chart showing an example of a manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a conceptual diagram showing an example of a configuration of a main part of an aging device for wafer burn-in used in a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

5 is an enlarged partial sectional view showing an example of a probe needle contact state during aging using the aging device shown in FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 semiconductor package (semiconductor device) 1a signal pin 1b power supply pin 1c GND pin 2 semiconductor chip 2a signal electrode 2b power supply electrode 2c GND electrode 2d logic circuit 2e cell 2f flip-flop 2g surface electrode 3 aging substrate (inspection substrate) 3a connection terminal 4 Aging signal application unit 4a Aging pulse signal (inspection pulse signal) 5 power supply unit 5a power pulse signal 6 pulse oscillator 7 deceleration counter 8 socket 9 semiconductor wafer 10 wafer stage (inspection stage) 11 probe needle 12 probe needle support board

 ────────────────────────────────────────────────── ─── Continued on the front page F-term (reference) 2G003 AA07 AA10 AB05 AB18 AC01 AE06 AF06 AG01 AG04 AH10 2G011 AA02 AA16 AE03 AF07 2G032 AA01 AB02 AB20 AD01 AE14 AF02 AG01 AG07 AJ07 AK03 AL11 4M106 AA01 BA01AC

Claims (7)

[Claims] A step of applying a test pulse signal to a signal electrode of a semiconductor chip; and a step of applying a power pulse signal to a power electrode of the semiconductor chip. And activating a logic circuit of the semiconductor chip to inspect the semiconductor chip. A step of applying a pulse signal for aging to a signal electrode of the semiconductor chip; and a step of applying a pulse signal for power to a power electrode of the semiconductor chip. Performing an aging test of a logic circuit of the semiconductor chip. A step of applying a failure analysis pulse signal to a signal electrode of the semiconductor chip; and a step of applying a power supply pulse signal to a power supply electrode of the semiconductor chip. Performing a failure analysis inspection of the semiconductor chip by activating the logic circuit of the semiconductor chip. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device provided with the semiconductor chip is arranged on an inspection board, and wherein the semiconductor device is provided on the inspection board. Inspecting the semiconductor chip incorporated in the semiconductor device by applying the power supply using the power supply pulse signal. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor wafer on which the plurality of semiconductor chips are formed is arranged on an inspection stage, and the semiconductor wafer is arranged on the inspection stage. Inspecting the semiconductor chip of the semiconductor wafer by applying the power by the power pulse signal. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the frequency of the power supply pulse signal is set lower than the frequency of the inspection pulse signal. Semiconductor device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the frequency of the inspection pulse signal is a high frequency and the frequency of the power supply pulse signal is the inspection. A method for manufacturing a semiconductor device, wherein the frequency is much lower than the frequency of a pulse signal for use.