JP2001016045A - Bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a bias circuit which makes the amplitude variation of a high-frequency signal small, when the high-frequency signal is amplified. SOLUTION: In this bias circuit which comprises an NPN type transistor(TR) 14, etc., and supplies a bias voltage to a drain terminal D of a field effect transistor 11, a circuit including a capacitor Ca and resistances R1 and R2 is connected to the base terminal of the NPN type TR 14 and the time constant determined by the capacitor Ca, and resistances R1 and R2 is matched with the time constant of the heat of the field effect transistor 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit for a power amplifier for amplifying a high-frequency signal or the like.

[0002]

2. Description of the Related Art When amplifying a high frequency signal such as a pulse signal for radar, for example, a field effect transistor (hereinafter referred to as FE)
T) is used. When operating the power amplifier circuit, a bias voltage is applied to the drain terminal of the FET from the bias circuit.

Here, with respect to a conventional bias circuit, F
An example of a power amplifier circuit using ET will be described with reference to FIG. Reference numeral 61 denotes an FET. The FET 61 is provided with a drain terminal D, a source terminal S, and a gate terminal G. An input terminal IN for inputting a high-frequency signal is connected to the gate terminal G, and an output terminal OUT is connected to the drain terminal D.
Is connected. The source terminal S is grounded, and the gate terminal G is connected to a negative constant voltage power supply 62 for generating a bias voltage. A drain bias circuit 63 is connected to the drain terminal D.

A bias circuit 63 includes an NPN transistor 64 serving as a current amplifying element and a positive constant voltage power supply 6.
5 and the like. The transistor 64 is provided with an emitter terminal e, a base terminal b, and a collector terminal c, and a positive constant voltage power supply 65 is connected to the collector terminal c. The emitter e is connected to the drain terminal D of the FET 61. A control terminal 66 for inputting a control signal for controlling the transistor 64 to a conductive state or a non-conductive state is connected to the base terminal b.

[0005]

In the above configuration, the bias voltage is applied from the constant voltage power supply 62 to the gate terminal G of the FET 61 so that the current flowing between the drain terminal D and the source terminal S has a predetermined value. Applied. Then, the high-frequency signal is input to the FET 61 through the input terminal IN. In this state, a pulse-like control signal as shown by a symbol A in FIG. 7A is applied to the control terminal 66 of the bias circuit 63, and the transistor 64 is turned on. At this time, a bias voltage having the same waveform as that of FIG. 7A is applied to the drain terminal D (point B) of the FET 61,
The amplified high-frequency pulse signal is output to the output terminal OUT.

In this case, if the pulse width of the bias voltage applied to the drain terminal D of the FET 61 becomes longer, for example, if the pulse width becomes longer than the time constant of the heat between the channel of the FET 61 and the heat radiation surface, FIG. ), The temperature of the channel of the FET 61 rises. As a result, the saturated output power of the FET 61 decreases as shown by the curve C in FIG. 7C, and the amplitude of the high-frequency pulse signal output from the FET 61 changes within the pulse as shown by the curve D in FIG. And a pulse signal of constant power cannot be obtained. The horizontal axis in FIG. 7 indicates time t.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a bias circuit in which the amplitude fluctuation of a high-frequency signal is reduced when a high-frequency signal is amplified.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a bias circuit having a current amplifying element and a constant voltage power supply for supplying a bias voltage to a drain terminal of a field effect transistor. Wherein the time constant determined by the capacitor and the resistor is adjusted to the heat time constant of the field effect transistor.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG.

Reference numeral 11 denotes an FET constituting a power amplifier circuit.
The FET 11 has a drain terminal D, a source terminal S,
A gate terminal G is provided. The gate terminal G is connected to an input terminal IN for inputting a high-frequency signal having a constant amplitude, and the drain terminal D is connected to an output terminal OUT for outputting an amplified high-frequency pulse signal. The source terminal S is grounded. The gate terminal G is connected to a negative constant voltage power supply 12 for applying a bias voltage. A drain bias circuit 13 is connected to the drain terminal D.

The bias circuit 13 includes an NPN transistor 14 as a current amplifying element, a positive constant voltage power supply 15, and the like. The transistor 14 is provided with an emitter terminal e, a base terminal b, and a collector terminal c,
The positive constant voltage power supply 15 is connected to the collector terminal c. Further, the emitter terminal e is connected to the drain terminal D of the FET 11. The control terminal 16 is connected to the base terminal b. The control terminal 16 is supplied with a pulse-like control signal for controlling the transistor 14 to a conductive state or a non-conductive state.

A first resistor R1 is connected between the base b of the transistor 14 and the control terminal 16, and a capacitor Ca and a second resistor R2 are connected in series between the base b and the ground GND. The time constant of the values of the first resistor R1, the second resistor R2, and the capacitor Ca is as follows.
It is set to match the heat time constant of

In the configuration described above, a predetermined bias voltage is applied from the constant voltage power supply 12 to the gate terminal G of the FET 11 so that the current flowing between the drain terminal D and the source terminal S of the FET 11 has a predetermined value. You. Then, a high-frequency signal having a constant amplitude is supplied from the input terminal IN to the FET1.
Enter 1 In this state, the control terminal 16 is connected to FIG.
When a pulse-like control signal as indicated by the symbol A in (a) is applied, the transistor 14 is turned on. At this time, the output voltage of the voltage power supply 15 is applied to the drain terminal D (point B) of the FET 11 via the emitter terminal e of the transistor 14. Thus, the amplified high-frequency pulse signal is output to the output terminal OUT.

Here, a case where a control signal having a pulse width of about 2.5 times longer than the heat time constant of the FET 11 and applied to the control terminal 16 will be described. At this time, the current charged in the capacitor Ca and the first resistor R1
2 changes as indicated by the symbol B in FIG. For this reason, the voltage at the base terminal b (point A) of the transistor 14 and the voltage at the drain terminal D (point B) of the FET 11 change as indicated by the symbol C in FIG. In this case, at the beginning of the control signal, FET1
1 decreases, and the saturation output power of the FET 11 decreases. As a result, the amplitude of the high-frequency pulse signal output from the FET 11 is made uniform as indicated by the symbol D in FIG. 2D, and the output power becomes substantially constant. The horizontal axis in FIG. 2 indicates time t.

Note that the resistance value of the first resistor R1 is Ra,
The resistance value of the resistor R2 is Rb, the capacitance value of the capacitor Ca is C, the voltage value of the control signal is Vin, the value of the bias voltage applied to the drain terminal at the beginning of the control signal is Vds,
Assuming that the voltage value between the base b and the emitter e of the NPN transistor 14 is Vbe and the heat time constant of the FET 11 is τ,
These values have the following relationship. τ = (Ra + Rb) × C (1) Vds = Vin × [Rb / (Ra + Rb)] − Vbe (2) For example, the width of the control signal is 750 μs, and the voltage value is 10.
6V, the resistance value of the first resistor R1 is 100Ω, the second resistor R2
Is 900Ω and the capacitance of the capacitor Ca is 0.3
μF, the heat time constant of the FET 11 is 300 μs, and the time constant of the first resistor R1, the second resistor R2 and the capacitor Ca is 3
In the thermal equilibrium state, the temperature difference between the channel and the heat radiation surface of the FET 11 is 50 ° C., and the temperature fluctuation of the saturation output power of the FET 11 is −0.01 dB / ° C.

In this case, at the end of the control signal, F
The saturation output power of ET11 is about 0. 4 higher than the beginning of the control signal due to the rise in the channel temperature of FET11.
Decrease by 5 dB. However, the voltage at the drain terminal (point B in FIG. 1) is about 9 V at the beginning of the control signal, and the voltage at the drain terminal (point B in FIG. 1) is about 10 V at the end of the control signal. For this reason, the saturation output power of the FET 11 increases by about 0.5 dB at the end of the control signal compared to the start of the control signal due to the rise in the voltage at the drain terminal. As a result, the output power of the output high-frequency pulse signal becomes substantially constant as shown in FIG.

Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be partially omitted. In the case of this embodiment, the circuit connected to the base b of the NPN transistor is different from that of FIG. So, base b
The following description focuses on the circuit connected to.

For example, a first inductor L1 is connected between the base b of the transistor and the control terminal 16, and a second inductor L2 and a resistor connected in series between the base b of the transistor and ground GND. R3 is connected.
In this case, the time constant of the first inductor L1, the second inductor L2, and the resistor R3 is adjusted to the heat time constant of the FET 11.

According to the above configuration, the control terminal 16
FIG. 2 (a) having a width 2.5 times the thermal time constant of the FET.
Even if a pulse-like control signal such as the symbol A is input,
The voltage between the terminals of the first inductor L1 is denoted by a symbol B in FIG.
It changes like Therefore, point A in FIG.
The voltage at the base terminal b of the N-type transistor 14 and the voltage at the point B in FIG.
It changes like the code C of (c). As a result, at the beginning of the control signal, the bias voltage of the drain of the FET 11 decreases. As a result, the saturation output power of the FET 11 decreases, and the high-frequency pulse signal output from the FET has a uniform amplitude as a whole as indicated by a symbol D in FIG.

Here, the value of the first inductor L1 is La,
The value of the second inductor L2 is Lb, the resistance value of the resistor R3 is R, the voltage value of the control signal is Vin, the drain voltage value at the beginning of the control signal is Vds, the base terminal b of the NPN transistor 14 and the emitter. Vbe, FE
Assuming that the heat time constant of T11 is τ, these values have the following relationship. τ = (La + Lb) / R (3) Vds = Vin × [Lb / (La + Lb)] − Vbe (4) For example, the pulse width of the control signal is 750 μs and the voltage value is 1
0.6V, the value of the first inductor L1 is 0.03H,
The value of the inductor L2 is 0.27H, the resistance value of the resistor R3 is 1000Ω, the thermal time constant of the FET is 300 μs, the time constant of the first inductor L1, the second inductor L2, and the resistor R3 is 300 μs. The temperature difference between the heat radiating surfaces is 50 ° C., and the temperature fluctuation of the saturation output power of the FET 11 is −0.01 dB / ° C. In this case, the saturation output power of the FET 11 is lower by about 0.5 dB at the end of the control signal than at the start of the control signal due to the temperature rise of the channel. However, FIG.
The drain voltage at point B is about 9 V at the beginning of the control signal and about 10 V at the end of the control signal.
For this reason, the saturation output power of the FET 11 is increased by about 0.5 dB at the end of the control signal compared to the start of the control signal due to the increase in the drain voltage. As a result, the output high-frequency pulse signal has a uniform amplitude as indicated by the symbol D in FIG. 3D, the amplitude fluctuation in the pulse is reduced, and the output power is substantially constant.

Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 4, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be partially omitted.

In the above two embodiments, the FET is used as an amplifying element for amplifying a high frequency signal. In this embodiment, a bipolar transistor is used as an amplifying element.

Reference numeral 41 denotes an NP used as an amplifying element.
The transistor 41 is provided with an emitter terminal e, a base terminal b, and a collector terminal c. Then, the collector terminal c is connected to the bias circuit 13 and the output terminal OUT, respectively. The base terminal b has a positive constant current power supply 42 and an input terminal IN.
Are connected respectively. The emitter terminal e is grounded. In this case, the time constant of the first resistor R1, the second resistor R2, and the capacitor Ca is set to match the heat time constant of the NPN transistor 41.

According to the above configuration, a control signal having a pulse width longer than the time constant of heat of the NPN transistor 41, for example, 2.5 times as long as the symbol A in FIG. 2B, the current charged in the capacitor Ca and the voltage between the terminals of the first resistor R1
As shown by B in FIG. Therefore, point A in FIG. 4, that is, the base terminal b of the NPN transistor, and
The point B in FIG. 4, that is, the voltage of the collector terminal c of the NPN transistor 41 changes as indicated by the symbol B in FIG. 2B. As a result, at the beginning of the control signal, the saturation output power of the NPN transistor 41 decreases due to the voltage drop at the collector terminal. On the other hand, at the end of the control signal, the voltage at the collector terminal of the NPN transistor 41 increases, and the saturation output power of the NPN transistor 41 increases. Therefore, the high-frequency pulse signal output from the NPN transistor 41 is as shown in FIG.
, The amplitude becomes uniform, and the output power becomes substantially constant.

Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. 5, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and duplicate description will be partially omitted. Also in this embodiment, a bipolar transistor is used as an amplifying element for amplifying a high-frequency signal.

Reference numeral 51 denotes an NP used as an amplifying element.
In the N-type transistor, the transistor 51 is provided with an emitter terminal e, a base terminal b, and a collector terminal c. Then, the collector terminal c is connected to the bias circuit 13 and the output terminal OUT, respectively. The positive constant current power supply 52 and the input terminal IN are connected to the base terminal b. The emitter terminal e is grounded. In this case, the first inductor L1 and the second inductor L
The time constant of the NPN transistor 51
It is adjusted to the heat time constant of

According to the above configuration, a control signal having a pulse width longer than the time constant of heat of the NPN transistor 51, for example, 2.5 times as long as the symbol A in FIG. , The voltage between the terminals of the first inductor L1 changes as indicated by the symbol B in FIG. 2B. For this reason, the voltage at point A in FIG. 5, that is, the base terminal b of the NPN transistor, and the voltage at point B in FIG. 5, that is, the collector terminal c of the NPN transistor 51, are respectively denoted by reference character B in FIG. It changes like As a result, at the beginning of the control signal, the saturation output power of the NPN transistor 51 decreases due to the voltage drop of the collector terminal c. On the other hand, at the end of the control signal, the voltage of the collector terminal of the NPN transistor 51 rises,
The saturation output power of the type transistor 51 increases. As a result, the high-frequency pulse signal output from the NPN transistor 51 has a uniform amplitude as shown by a symbol D in FIG. 2D, and the output power is substantially constant.

[0028]

According to the present invention, when amplifying a high-frequency signal, it is possible to realize a bias circuit in which the amplitude fluctuation of the high-frequency signal is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram for explaining another embodiment of the present invention.

FIG. 4 is a circuit configuration diagram for explaining another embodiment of the present invention.

FIG. 5 is a circuit configuration diagram for explaining another embodiment of the present invention.

FIG. 6 is a circuit configuration diagram for explaining a conventional example.

FIG. 7 is a waveform chart for explaining a conventional example.

[Explanation of symbols]

 11 FET 12 Negative constant voltage power supply 13 Bias circuit 14 NPN transistor 15 Positive constant voltage power supply 16 Control terminal D FET drain terminal G FET gate terminal S FET source terminal c Collector terminal of transistor e: Emitter terminal of transistor b: Base terminal of transistor R1: First resistor R2: Second resistor Ca: Capacitor

Continued from the front page F-term (reference) 5J090 AA01 AA54 AA58 CA02 CA04 CA22 CA81 CN01 CN04 FA08 FA10 FN06 FN07 FN09 HA02 HA09 HA25 HA29 HA33 HA39 HN02 HN06 HN15 HN21 KA05 KA11 KA12 KA25 KA30 KA48 A01 TA06 CA02 CA04 CA22 CA81 FA08 FA10 HA02 HA09 HA25 HA29 HA33 HA39 KA05 KA11 KA12 KA25 KA30 KA48 KA53 MA23 SA16 TA01 TA04 TA06 UW02 UW08 5J098 AA02 AA03 AA11 AA14 AB11 AD05 EA01

Claims (8)

[Claims] A bias circuit having a current amplification element and a constant voltage power supply for supplying a bias voltage to a drain terminal of a field effect transistor, wherein a circuit including a capacitor and a resistor is connected to an input terminal of the current amplification element; A bias circuit, wherein a time constant determined by a capacitor and the resistor is matched with a heat time constant of the field effect transistor. 2. A bias circuit having a current amplifying element and a constant voltage power supply for supplying a bias voltage to a drain terminal of a field effect transistor, wherein a circuit including an inductor and a resistor is connected to an input terminal of the current amplifying element. A bias circuit, wherein a time constant determined by an inductor and the resistance is matched with a heat time constant of the field effect transistor. 3. A bias circuit having a current amplifying element and a constant voltage power supply and supplying a bias voltage to a collector terminal of a bipolar transistor, wherein a circuit including a capacitor and a resistor is connected to an input terminal of the current amplifying element. And a time constant determined by the resistance is adjusted to a time constant of heat of the bipolar transistor. 4. A bias circuit having a current amplifying element and a constant voltage power supply for supplying a bias voltage to a collector terminal of a bipolar transistor, wherein a circuit including an inductor and a resistor is connected to an input terminal of the current amplifying element. And a time constant determined by the resistance is adjusted to a time constant of heat of the bipolar transistor. 5. An NPN transistor having first to third terminals, a constant voltage power supply connected to a first terminal of the transistor, and a control signal for setting the transistor to a conductive state or a non-conductive state. A control terminal for supplying the output of the constant voltage power supply to a drain terminal of the field effect transistor as a bias voltage through a third terminal. A first resistor is connected between the first terminal and the control terminal, a capacitor and a second resistor are connected in series between a second terminal of the transistor and ground, and the first resistor and the second resistor are connected in series. Wherein the time constant of the resistor and the capacitor is adjusted to the time constant of heat of the field effect transistor. 6. An NPN transistor having first to third terminals, a constant voltage power supply connected to a first terminal of the transistor, and a control signal for setting the transistor to a conductive state or a non-conductive state. A control terminal for supplying the output of the constant voltage power supply to a drain terminal of the field effect transistor as a bias voltage through a third terminal. A first inductor is connected between the first terminal and the control terminal, a second inductor and a resistor are connected in series between a second terminal of the transistor and ground, and the first inductor and the second A time constant of the inductor and the resistor according to a thermal time constant of the field effect transistor. . 7. An NPN transistor having first to third terminals, a constant voltage power supply connected to a first terminal of the NPN transistor, and setting the NPN transistor to a conductive state or a non-conductive state. A control terminal for supplying a control signal to the second terminal of the NPN transistor to supply the output of the constant voltage power supply as a bias voltage to the collector terminal of the bipolar transistor through a third terminal. The NPN
Connecting a first resistor between a second terminal of the transistor and the control terminal, connecting a capacitor and a second resistor in series between a second terminal of the NPN transistor and ground, and A bias circuit, wherein a time constant of a resistor, the second resistor, and the capacitor is adjusted to a heat time constant of the field-effect transistor. 8. An NPN transistor having first to third terminals, a constant voltage power supply connected to a first terminal of the NPN transistor, and setting the NPN transistor to a conductive state or a non-conductive state. A control terminal for supplying a control signal to the second terminal of the NPN transistor to supply the output of the constant voltage power supply as a bias voltage to the collector terminal of the bipolar transistor through a third terminal. The NPN
A first inductor is connected between a second terminal of the transistor and the control terminal, a second inductor and a resistor are connected in series between a second terminal of the NPN transistor and ground, and A bias circuit, wherein a time constant of the inductor, the second inductor, and the resistor is adjusted to a heat time constant of the bipolar transistor.