JP2001014874A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable utilizing a non-volatile semiconductor memory as a memory of less number of times of guarantee even if the number of times of guarantee of specifications of a product is not satisfied by storing the number of times of processing of writing and erasing data and a limit value of the number of times of guarantee set based on and a test result for the finite number of times of processing, and outputting an external output signal when the number of times of processing is equalized to the limit value. SOLUTION: A counter 2 counts up every time a non-volatile semiconductor memory 1 is written or erased, and outputs a count up signal 52. A limit value holding non-volatile memory 6 stores a limit value write-in signal 61 of the number of times of guarantee for write-in and erasion based on a test result from an erasion/write-in circuit 4, and outputs a limit value signal 62. A comparator 5 compares the limit value signal 62 with the count up signal 52, when they are equalized, an external output signal 53 is outputted to an output terminal 26 for monitor and a write-in circuit 7. A non-volatile storing section 3 stores the number of times of cumulative erasion and write-in.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable and writable nonvolatile semiconductor memory device.
In particular, the present invention relates to a nonvolatile semiconductor memory device in which a guaranteed value of the number of times of erasing and writing is recorded.

[0002]

2. Description of the Related Art An electrically erasable and writable nonvolatile semiconductor memory device performs erasing and writing of data by applying a high voltage. Therefore, stress due to the high voltage is accumulated in the nonvolatile semiconductor memory. If this stress exceeds a certain value, data cannot be erased or written. Here, this stress is proportional to the total time during which a high voltage is applied, and the total time during which the high voltage is applied is the product of the data erasing time and the number of times of erasing, and the data per time. It is equal to the sum of the product of the write time and the number of write operations.

Conventionally, for a nonvolatile semiconductor memory device having such characteristics, a technique disclosed in Japanese Patent Application Laid-Open No. 1-220300 discloses a technique in which the stress accumulated in a nonvolatile semiconductor memory is a constant value (hereinafter, referred to as appropriate). , A stress value has been abbreviated as a stress value.

A conventional nonvolatile semiconductor memory device will be described with reference to the drawings. FIG. 5 is a schematic block diagram of a conventional nonvolatile semiconductor memory device. In the figure, reference numeral 10c denotes a nonvolatile semiconductor memory device having a configuration including a nonvolatile semiconductor memory 1, a counter 2, a nonvolatile storage unit 3, an erasing circuit 4a, a limit value retaining nonvolatile memory 6, and a comparator 5.

[0005] The nonvolatile semiconductor memory 1 is an electrically erasable nonvolatile semiconductor memory and can perform data writing and erasing.
Unlimited writing and erasing cannot be performed.
That is, the number of times of data writing and erasing is finite.

Therefore, the nonvolatile semiconductor memory device 10
As for c, the number of guarantees for the number of times of data writing and erasing set based on the product specification is set as a limit value, and this limit value is stored in the limit value holding nonvolatile memory 6 in advance. Specifically, for example, if the guaranteed number of product specifications is 100,000, 100,000 is stored as the limit value in the nonvolatile semiconductor memory device 10c. The limit value holding nonvolatile memory 6 is the same type of nonvolatile semiconductor memory as the nonvolatile semiconductor memory 1.

The internal terminal 41 is connected to the erasing circuit 4a. The erasing circuit 4a receives a signal from the internal terminal 41 and outputs an initialization signal 42 to the nonvolatile storage unit 3 by Er (erase).
Output to the terminal to initialize the nonvolatile storage unit 3. This initialization is performed only once before the nonvolatile semiconductor memory 1 is driven with respect to the nonvolatile storage unit 3 that stores the number of times of writing and erasing of the nonvolatile semiconductor memory 1. Generally, by this initialization, 0 is stored in the nonvolatile storage unit 3.
The (zero) value is stored. Note that the non-volatile storage unit 3
This is a nonvolatile semiconductor memory of the same type as the nonvolatile semiconductor memory 1.

The nonvolatile storage unit 3 has a Dout terminal connected to the In terminal of the counter 2, and transfers an initialized zero value from the Dout terminal of the nonvolatile storage unit 3 to the In terminal of the counter 2 using an n-bit signal. (N is a natural number). The counter 2 counts up each time the nonvolatile semiconductor memory 1 is written and erased with respect to the zero value.
Abbreviated as count value. ) Is output from the Out terminal to the comparator 5 as an n-bit count-up signal 52. Here, it goes without saying that even if the nonvolatile semiconductor memory 1 is erased, the nonvolatile storage unit 3 is not erased.

The counter 2 detects that the power has been turned off, and outputs the count value of the counter 2 from the Out terminal to the Din terminal of the nonvolatile storage unit 3, and the nonvolatile storage unit 3 stores the count value. I do. In addition, the nonvolatile storage unit 3
Detects that the power has been turned on, outputs the stored numerical value to the counter 2 in the same manner. Then, the counter 2 similarly counts up the numerical value input from the nonvolatile storage unit 3 and outputs the count value to the comparator 5 as a count-up signal 52 in the same manner.

In this manner, the nonvolatile semiconductor memory 1
The number of times of writing and erasing, which is the sum of the total number of times of writing and erasing, is stored in the nonvolatile memory 3, and the number of times of writing and erasing is output to the comparator 5 as a count-up signal 52. Here, the number of times of erasing can be counted up as the number of times of writing. In this case, only the number of times of writing needs to be counted up, so that the circuit configuration can be simplified.

The comparator 5 compares the limit value input as the n-bit limit value signal 51 from the limit value holding nonvolatile memory 6 with the cumulative writing and erasing times input as the count-up signal 52 to determine the cumulative writing and erasing times. When the number of times of erasure becomes equal to the limit value, the external output signal 53 is output to the output terminal 26 for monitoring. As described above, in the conventional nonvolatile semiconductor memory device 10c, it is possible to monitor that the cumulative number of times of writing and erasing has exceeded the limit value, so that writing and erasing of the nonvolatile semiconductor memory 1 are electrically effective. Can be guaranteed.

[0012]

However, with the recent increase in the performance of the nonvolatile semiconductor memory device, the write / erase characteristics of the nonvolatile semiconductor memory device change due to slight variations in the manufacturing conditions in the manufacturing process. However, the time required for writing and erasing may be long. As described above, in the nonvolatile semiconductor memory device, when the time required for one writing and erasing is long, a high voltage is applied to the nonvolatile semiconductor memory for a long time, and a large amount of stress is accumulated at one time. The guaranteed number of times of the specification cannot be satisfied, and the product fails the inspection.

Here, for example, if a customer needs a nonvolatile semiconductor memory device whose number of guarantees is 80,000,
For a non-volatile semiconductor memory device whose original product specifications are guaranteed 100,000 times, the limit value is 8 even for a non-volatile semiconductor memory device whose test result is only guaranteed 90,000 times.
If it is 10,000 times, it can be used enough.

However, in the conventional nonvolatile semiconductor memory device 10c, the limit value holding nonvolatile memory stores 100,000 times as the limit value, and this limit value cannot be changed. For this reason, it is not possible to guarantee that the writing and erasing are performed electrically for 90,000 to 100,000 times. There is a problem that the semiconductor memory device is discarded because it cannot be used because it has failed the inspection.

The present invention has been made in order to solve the above-mentioned problem. By inputting a guaranteed number of times set based on a test result as a limit value to a limit value holding nonvolatile memory, the original product is provided. It is an object of the present invention to provide a nonvolatile semiconductor memory device that can be used as a nonvolatile semiconductor memory device having a low guaranteed number of times even if the guaranteed number of times of the specifications is not satisfied.

As a technique related to the present invention, EE disclosed in Japanese Patent Application Laid-Open No. H10-64290 is disclosed.
There are PROM write guarantee methods and microcomputer system technologies. However, this technique issues a warning when the number of times of writing exceeds the guaranteed number of times of writing, and prohibits new writing, and cannot solve the problem of the present invention.

Further, as a technique related to the present invention, there is a technique of a nonvolatile semiconductor memory device with an exchange display function disclosed in Japanese Patent Application Laid-Open No. 6-236695. However, this technique is a technique for displaying a replacement time when the number of times of writing reaches the guaranteed number of times of writing, and cannot solve the problem of the present invention.

Further, as a technique related to the present invention, there is a technique of a storage system using a flash memory disclosed in Japanese Patent Application Laid-Open No. 10-207784.
However, this technique is a technique for over-erasing data, and cannot solve the problem of the present invention.

[0019]

In order to achieve the above object, a nonvolatile semiconductor memory device according to claim 1 of the present invention comprises a nonvolatile semiconductor memory having a finite number of times of data writing and erasing, and A counter that counts up the number of times of processing, a nonvolatile storage unit that stores the counted number of times of processing, a limit value holding nonvolatile memory that stores a guaranteed number of times for the finite number of times of processing as a limit value, A nonvolatile semiconductor memory device having at least a comparator that outputs an external output signal when the number of times of processing performed becomes equal to the stored limit value, wherein the nonvolatile storage unit and the limit value holding nonvolatile memory are initialized. And an erasing / writing circuit for writing the limit value in the limit value holding nonvolatile memory. For example, there the limit value, as a set based on the test results of the non-volatile semiconductor memory.

As described above, by inputting the guaranteed number of times set based on the test result as the limit value into the limit value holding nonvolatile memory, the nonvolatile semiconductor memory device which does not satisfy the guaranteed number of times in the original product specification can be used. Even if the number of guarantees is low, the yield of the nonvolatile semiconductor memory device can be improved because it can be used as a nonvolatile semiconductor memory device having a low guaranteed number of times.

According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory in which the number of times of data writing and erasing is finite, a counter for counting up the number of times of processing, and a guaranteed number of times for the finite number of times of processing. In a nonvolatile semiconductor memory device having at least a limit value holding nonvolatile memory to store as a limit value and a comparator that outputs an external output signal when the counted number of processes is equal to the stored limit value,
An erase / write circuit that initializes the nonvolatile storage unit and the limit value holding nonvolatile memory, and writes the limit value to the limit value holding nonvolatile memory and outputs a divided signal; and the erase / write circuit. When the division signal is input from the above, the nonvolatile semiconductor memory is divided into a plurality of blocks, and a write circuit for writing and erasing the data for each block, and storing the counted number of processes, When the erase / write circuit outputs the divided signal, all of the nonvolatile storage units store the counted number of times of processing and store the limit value holding nonvolatile memory. Setting the limit value written to the nonvolatile memory based on a test result of the nonvolatile semiconductor memory Are you.

By doing so, for example, the nonvolatile semiconductor memory has a memory capacity of 10 kbytes and the test result is less than the guaranteed value of 100,000 times, which is a passing value, and is only 90,000 times. Even a non-volatile semiconductor memory device having no memory is used as a non-volatile semiconductor memory device having a limit value of 90,000 times or a memory capacity of 5 Kbytes and a guaranteed number of times of 180,000 times. Therefore, the yield of the nonvolatile semiconductor memory device can be further improved.

According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the nonvolatile storage unit is formed of two nonvolatile storage units, and the number of times of processing counted up is alternated. Is stored.

Thus, the non-volatile memory section is usually a non-volatile semiconductor memory of the same type as the non-volatile semiconductor memory. For example, the test result of the non-volatile semiconductor memory is less than the pass value of 100,000 guarantees. Even if the number of guarantees is at least 90,000, the count-up can be reliably performed up to 180,000 by providing two non-volatile storage units, thereby improving the reliability of the count-up. be able to.

According to a fourth aspect of the present invention, in the non-volatile semiconductor memory device according to any one of the first to third aspects, the time required for writing and erasing the non-volatile semiconductor memory is reduced by the non-volatile memory. The configuration is a test result of a semiconductor memory.

In this manner, since the stress due to the high voltage accumulated in the nonvolatile semiconductor memory can be accurately simulated, it is possible to obtain a reliable number of times of writing and erasing with high reliability.

According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fourth aspects, the write circuit is connected to the comparator and the nonvolatile memory, and Is counted up and reaches the limit value, a signal output from the comparator is input, and a signal for inhibiting new writing and erasing is output to the nonvolatile memory.

In this way, when the number of times of writing and erasing reaches the limit value, new writing and erasing are automatically prohibited in the nonvolatile memory, which is preferable for use.

According to a sixth aspect of the present invention, in the nonvolatile semiconductor memory device according to any one of the first to fifth aspects, the nonvolatile semiconductor memory is a flash PROM.

By doing so, it is possible to improve the yield of flash PROMs under strict management conditions in the production process.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device according to each embodiment of the present invention will be described with reference to the drawings. First, the structure and operation of the nonvolatile semiconductor memory device according to the first embodiment will be described. FIG.
1 shows a schematic block diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. In the figure,
Reference numeral 10 denotes a nonvolatile semiconductor memory device, which includes a nonvolatile semiconductor memory 1, a counter 2, a nonvolatile storage unit 3, an erase / write circuit 4, a limit value holding nonvolatile memory 6, a comparator 5, and a write circuit 7. .

The nonvolatile semiconductor memory 1 is an electrically erasable nonvolatile semiconductor memory, and cannot perform writing and erasing of data without limitation. here,
More specifically, the nonvolatile semiconductor memory device 10
ROM, flash PROM and the like.

The internal terminal 41 is connected to the erasing / writing circuit 4, and the erasing / writing circuit 4 is connected to the Er terminal of the nonvolatile storage unit 3 and the limit value holding nonvolatile memory 6. Here, the erasing / writing circuit 4 which has received a signal from the internal terminal 41 can output the initialization signal 42 to initialize the nonvolatile storage unit 3 and the limit value holding nonvolatile memory 6.

In the nonvolatile storage unit 3, the Dout terminal is connected to the In terminal of the counter 2, and the counter 2
The t terminal is connected to the Din terminal of the nonvolatile storage unit 3 and the comparator 5. Here, the nonvolatile storage unit 3
The initialized zero value is output from the Dout terminal of the nonvolatile storage unit 3 to the In terminal of the counter 2 as an n-bit signal, and the counter 2 counts up each time the nonvolatile semiconductor memory 1 is written and erased. Then, the count value is output from the Out terminal to the comparator 5 as an n-bit count-up signal 52.

The nonvolatile memory 6 for holding the limit value is connected to the comparator 5, and the comparator 5 is connected to the output terminal 26 and the write circuit 7. Here, the limit value holding nonvolatile memory 6 inputs and stores the guaranteed number of times of the number of times of writing and erasing based on the test result from the erasing / writing circuit 4 as the limit value writing signal 61.

The comparator 5 compares the limit value input as the n-bit limit value signal 62 from the limit value holding non-volatile memory 6 with the cumulative number of times of writing and erasing input as the count-up signal 52 to determine the cumulative number. When the number of times of writing and erasing becomes equal to the limit value, an external output signal 53 is output to the monitor output terminal 26 and the writing circuit 7.

The write circuit 7 is connected to the non-volatile semiconductor memory 1 and, when an external output signal 53 is input, outputs a prohibition signal 72 for prohibiting the non-volatile semiconductor memory 1 from newly writing and erasing. Memory 1
Output to Other structures and operations are the same as those of the conventional nonvolatile semiconductor memory device 10c.

Next, the operation of the nonvolatile semiconductor memory device 10 according to the first embodiment will be described. First, a signal is input from the internal terminal 41 to the erase / write circuit 4,
The erase / write circuit 4 is driven. The erase / write circuit 4 outputs an initialization signal 42 to the nonvolatile storage unit 3 to initialize the count value, and outputs an initialization signal 42 to the limit value holding nonvolatile memory 6 to initialize the limit value.

Here, preferably, a signal input from the internal terminal 41 to the erasing / writing circuit 4 is set under a certain condition,
For example, a stable signal controlled by a test mode or a special register may be used. This makes it possible to more reliably prevent a malfunction or the like. In addition, the nonvolatile storage unit 3 that stores the count value and the limit value holding nonvolatile memory 6 that holds the limit value of the number of times of writing and erasing are not erased even if the nonvolatile semiconductor memory 1 is erased. is there.

Next, the limit value for the nonvolatile semiconductor memory 1 calculated based on the erase test and the write test of the nonvolatile semiconductor memory 1 is written to the limit value holding nonvolatile memory 6. Here, the nonvolatile semiconductor memory 1 is exposed to a high voltage when erasing or writing is performed, and the longer the exposure time to the high voltage, the more the stress due to the high voltage is accumulated and the shorter the life is. Based on this characteristic, the limit value of the number of times of writing and the number of times of erasing of the nonvolatile semiconductor memory 1 can be calculated.

More specifically, statistical data is collected in advance on the correlation between the writing time and the erasing time and the number of writings and the erasing times, and the number of writings and the erasing times for the measurement results of the writing time and the erasing time are collected from the statistical data. Is calculated, and this guaranteed value is set as the limit value. Then, this limit value is inputted to the internal terminal 41, and the erasing / writing circuit 4 which has inputted this signal outputs a limit value writing signal 61 to the limit value holding nonvolatile memory 6,
The limit value is written to the limit value holding nonvolatile memory 6.

Next, when detecting that the power is turned on, the non-volatile storage section 3 outputs the stored value (zero value when initialized) to the counter 2. Here, this signal is an n-bit signal. Counter 2
Counts up each time erasing and writing to the nonvolatile semiconductor memory 1 are performed.

Thereafter, when it is detected that the power has been turned off, the contents of the counter 2 are written into the nonvolatile storage unit 3. When detecting that the power has been turned on, the contents of the nonvolatile storage unit 3 are output to the counter 2. In this way, the counter is incremented once each time the nonvolatile semiconductor memory 1 is erased and written, and the total number of times of erasing and writing to the nonvolatile semiconductor memory 1, that is, the cumulative number of times of erasing and writing is stored in the nonvolatile memory 3. Is done.

The latest accumulated erase count and write count are stored in the counter 2. When this value becomes equal to the limit value of the limit value holding nonvolatile memory 6, the output of the comparator 5 changes. Then, this change is output to the output terminal 26 as an external output signal 53. Then, if the external output signal 53 from the output terminal 26 is monitored, it can be easily known from the outside.

Preferably, the limit value is set by inputting the external output signal 53 of the comparator 5 to the writing circuit 7 and driving the writing circuit 7 to stop the writing and erasing operations of the nonvolatile semiconductor memory 1. Excessive writing and erasing can be automatically prohibited. Other operations are the same as those of the conventional nonvolatile semiconductor memory device 10c.

As described above, the nonvolatile semiconductor memory device 10 according to the first embodiment writes the guaranteed number of times calculated based on the test result as the limit value in the limit value holding nonvolatile memory 6, thereby obtaining the original value. Even if the nonvolatile semiconductor memory device 10 does not satisfy the guaranteed number of times of the product specifications, the nonvolatile semiconductor memory device 1 with a small number of guaranteed times
Since it can be used as 0, the yield of the nonvolatile semiconductor memory device 10 can be improved. Also,
The nonvolatile semiconductor memory device 10 is a flash PROM
In the case of (1), since the management conditions in the production process of the flash PROM are strict, the yield of the nonvolatile semiconductor memory device 10 can be significantly improved.

Next, the structure and operation of the nonvolatile semiconductor memory device according to the second embodiment will be described. FIG.
Shows a schematic block diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. In the figure,
Reference numeral 10a denotes a nonvolatile semiconductor memory device, which is a nonvolatile semiconductor memory that can be divided into two blocks, nonvolatile storage units 3a and 3b corresponding to the two blocks, a counter 2, an erase / write circuit 4, and a limit value holding. The configuration includes a nonvolatile memory 6, a comparator 5, and a writing circuit 7.

The erase / write circuit 4 is connected to the Er terminals of the nonvolatile storage sections 3a and 3b, the limit value holding nonvolatile memory 6, and the write circuit 7. Here, when the erasing / writing circuit 4 receives a signal indicating that the nonvolatile semiconductor memory 1 is to be divided and used, the nonvolatile memory section 3a,
3b, outputs an initialization signal 42 and a limit value write signal 61 to the limit value holding nonvolatile memory 6, and outputs a division signal 43 to the write circuit 7.

The nonvolatile semiconductor memory 1 stores the divided signal 43
Is input, the write circuit 7 divides the data into two blocks, and data writing and erasing are sequentially performed for each block.

That is, when the divided signal 43 is input to the write circuit 7, for example, the nonvolatile semiconductor memory 1
When it has a storage capacity of k bytes, it is divided into an A block 1a and a B block 1b each having a storage capacity of 5 k bytes, the first write is performed on the A block 1a, and the second write is performed on the B block 1b. Writing and erasing are performed in order, such as performed on the block 1b and the third write is performed on the A block 1a again.

When the non-volatile semiconductor memory 1 is divided and used, the non-volatile storage section 3a stores an initialization signal 4
2 of the nonvolatile semiconductor memory 1
For the block 1a, the counted up numerical values of the writing and erasing are stored. In addition, the nonvolatile storage unit 3
b, when the nonvolatile semiconductor memory 1 is divided and used, the initialization signal 42 is inputted, and the counted up number of writing and erasing is stored in the B block 1 b of the nonvolatile semiconductor memory 1. I do.

When the nonvolatile semiconductor memory 1 is divided and used, the counter 2 inputs the initialized count value from the nonvolatile storage units 3a and 3b and sends the divided count values to the divided A block 1a and B block 1b. On the other hand, the count value counted up by writing and erasing is represented by Out
From the terminal as a signal of n + 1 bits
a and 3b and to the comparator 5 as an n-bit count-up signal 52.

When the nonvolatile semiconductor memory 1 is divided and used, the limit value holding nonvolatile memory 6 inputs a limit value write signal 61 including two limit values for the A block 1a and the B block 1b.

When the nonvolatile semiconductor memory 1 is divided and used, the comparator 5 receives the two limit values input as the limit value signal 62 from the limit value holding nonvolatile memory 6 and the count-up signal 52. When the cumulative writing and erasing times become equal to the two limit values, the external output signal 53 is output to the monitor output terminal 26 and the writing circuit 7.

The write circuit 7 includes an erase / write circuit 4
, The nonvolatile semiconductor memory 1 is divided into an A block 1a and a B block 1b.
When writing and erasing are performed alternately and the external output signal 53 is input, the A block 1a and the B block 1
b is prohibited from newly writing and erasing. Other structures and operations are the same as those of the nonvolatile semiconductor memory device 10 of the first embodiment.

Next, the operation of the nonvolatile semiconductor memory device 10a according to the second embodiment will be described. First, a signal is input from the internal terminal 41 to the erasing / writing circuit 4, and when this signal is a signal indicating that the nonvolatile semiconductor memory 1 is not divided and used, the erasing / writing circuit 4 is driven, The count value of the storage unit 3a and the limit value of the limit value holding nonvolatile memory 6 are initialized. Then, the nonvolatile semiconductor memory device 10a performs the same operation as the nonvolatile semiconductor memory device 10 of the first embodiment without using the nonvolatile storage unit 3b.

Next, when a signal indicating that the nonvolatile semiconductor memory 1 is to be divided and used is input to the erase / write circuit 4 from the internal terminal 41, the erase / write circuit 4 is driven and the count value is stored. The count value of the non-volatile storage units 3a and 3b and the limit value of the limit value holding non-volatile memory 6 are initialized. Further, a division signal 43 is output to the write circuit 7, and the write circuit 7 divides the nonvolatile semiconductor memory 1 into the A block 1a and the B block 1b, and performs writing and erasing alternately.

Next, the two limit values for the A block 1a and the B block 1b calculated based on the erase test and the write test of the nonvolatile semiconductor memory 1 are written to the limit value holding nonvolatile memory 6. Here, normally, A block 1
The limit values of a and B block 1b are the same since they are manufactured under the same manufacturing conditions.

Next, when the nonvolatile storage units 3a and 3b detect that the power is turned on, they output the stored value (zero value when initialized) to the counter 2. . Here, this signal is an n + 1 bit signal. The counter 2 counts up each time erasing and writing to the A block 1a and the B block 1b.

Thereafter, when it is detected that the power supply has been turned off, the count value of the counter 2 is stored in the nonvolatile storage unit 3.
a and 3b, respectively. When detecting that the power is turned on, the counter 2 outputs the count value of the nonvolatile storage units 3a and 3b to the counter 2. In this way, the counter is incremented once each time the A block 1a and the B block 1b are erased and written, and the total erase and write times for the A block 1a and the B block 1b, that is, the cumulative erase and write times are non-volatile. Memory 3
a and 3b.

The latest accumulated number of times of erasing and writing is input to the counter 2 as a count-up signal 52. When this value becomes equal to the two limit values set in the limit value holding nonvolatile memory 6, Changes the output of the comparator 5 and outputs the change to the output terminal 26 as an external output signal 53. Then, if the external output signal 53 from the output terminal 26 is monitored, it can be easily known from the outside. Other operations are the same as those of the nonvolatile semiconductor memory device 10 of the first embodiment.

As described above, in the nonvolatile semiconductor memory device 10a according to the second embodiment, for example, the nonvolatile semiconductor memory 1 has a memory capacity of 10 kbytes and the test result is a pass value of 100,000 times. Even if the nonvolatile semiconductor memory device 1a has only 90,000 guarantees less than the guaranteed number of times, by setting the limit value to 90,000 times,
The memory capacity is 5 kbytes and the guaranteed number of times is 1
It can be used as the nonvolatile semiconductor memory device 1a for 80,000 times, and the yield of the nonvolatile semiconductor memory device 10a can be improved. Further, the nonvolatile semiconductor memory device 10a can be used as the nonvolatile semiconductor memory device 10a having a memory capacity of 10 kbytes and a guaranteed number of times of 90,000.

If the test result is guaranteed 100,000 times, it is used as a non-volatile semiconductor memory device of the original product specification (memory capacity 10 kbytes and guaranteed write / erase 100,000 times). can do. Further, as the second embodiment, the nonvolatile semiconductor memory 1 is divided into two, but the present invention is not limited to two, and it can be divided into three or more.

Next, the structure and operation of the nonvolatile semiconductor memory device according to the third embodiment will be described. FIG.
Shows a schematic block diagram of a nonvolatile semiconductor memory device according to a third embodiment of the present invention. In the figure,
Reference numeral 10b denotes a nonvolatile semiconductor memory device having a nonvolatile semiconductor memory 1, nonvolatile storage units 3c and 3d, a counter 2, an erase / write circuit 4, a limit value holding nonvolatile memory 6, a comparator 5, and a write circuit 7. There is.

The erasing / writing circuit 4 includes the Er terminals of the nonvolatile storage units 3c and 3d and the limit value holding nonvolatile memory 6
Connected to Here, the erasing / writing circuit 4 to which a signal is input from the internal terminal 41 is connected to the non-volatile storage units 3c and 3c.
d, and outputs the initialization signal 42 and the limit value write signal 61 to the limit value holding nonvolatile memory 6.

The nonvolatile storage units 3c and 3d have a Dout terminal, a Din terminal, an Er terminal, and a CS terminal.
Each Dout terminal and CS terminal are respectively connected to the counter 2
Are connected to the In1, In2, CS1, and CS2 terminals. In addition, the nonvolatile storage units 3c and 3d
Outputs the stored count value to the counter 2 from each Dout terminal as an n + 1 bit signal. In addition, the nonvolatile storage units 3c and 3d include a CS1 terminal of the counter 2,
The select signal 21 output from the S2 terminal is input to each CS terminal.

The counter 2 has an Out terminal connected to the Din terminals of the nonvolatile storage units 3c and 3d and the comparator 5, counts up each time the nonvolatile semiconductor memory 1 is written or erased, and counts this count value. ,
From the Out terminal, an n-bit count-up signal 52 is output to the comparator 5 and the select signal 2 is output.
1, n is stored in one of the nonvolatile storage units 3c and 3d.
It is output alternately as a + 1-bit count-up signal 52. Therefore, in the nonvolatile storage units 3c and 3d, when the nonvolatile semiconductor memory 1 performs the writing and erasing 2m times (m is a natural number), the writing and the erasing are performed m times in half.

The limit value holding nonvolatile memory 6 inputs and stores the guaranteed number of times of the number of times of writing and erasing based on the test result from the erasing / writing circuit 4 as one limit value.

The comparator 5 compares one limit value input as the n-bit limit value signal 62 from the limit value holding nonvolatile memory 6 with the cumulative write and erase count input as the n-bit count-up signal 52. hand,
When the number of times of cumulative writing and erasing becomes equal to the limit value, an external output signal 53 is output to the output terminal 26 for monitoring and the writing circuit 7. Other structures and operations are described in the nonvolatile semiconductor memory device 10 of the first embodiment.
Same as

Next, the operation of the nonvolatile semiconductor memory device 10b according to the third embodiment will be described. A signal is input from the internal terminal 41 to the erasing / writing circuit 4, and the erasing / writing circuit 4 is driven, and the nonvolatile storage units 3c, 3d
And the limit value of the limit value holding nonvolatile memory 6 are initialized.

Next, when the nonvolatile storage units 3c and 3d detect that the power is turned on, they output the stored value (zero value when initializing) to the counter 2. . Each time the writing and erasing of the nonvolatile semiconductor memory 1 are performed, the counter 2 stores the data in the nonvolatile storage units 3c and 3c.
Writing is performed alternately on d.

This mechanism will be described with reference to the drawings. FIG. 4 is a schematic circuit diagram for performing write control of the count value of the nonvolatile semiconductor memory device 1b according to the third embodiment of the present invention. In FIG.
Are the counter element 201, the selector element 202, and the EXN
An OR (non-exclusive OR) element 203, an INV1 (inverter 1) element 204, and an INV2 (inverter 2) element 205 are provided.

In the nonvolatile memories 3c and 3d, all bit values are set to 0 by initialization, and the nonvolatile memories 3c and 3d
The bit for switching d is the n + 1th bit of the most significant bit. The (n + 1) -bit signal output from the Dout terminal of the nonvolatile memory 3 c
1 terminal, and similarly, the non-volatile memory 3d
N + 1 bit signal output from the Dout terminal of
It is input to the In2 terminal of the counter 2.

Here, the lower n bits of the signals input to the In1 terminal and the In2 terminal correspond to the selector element 20 respectively.
2 and the signal line 105 and the signal line 106 of the (n + 1) th bit are EX as inputs of a logical element of a non-exclusive OR.
Connected to NOR element 203. EXNOR output 107
Is 1, a signal line of 0 to n bits of the signal input to the In1 terminal is selected and output to the counter element 201,
A count-up operation is performed, and EXNOR output 107 becomes 0
In this case, a signal line of 0 to n bits of the signal input to the In2 terminal is selected and output to the counter element 201 to perform a count-up operation.

The EXNOR output 107 is input to the CS2 terminal for selecting the nonvolatile memory 3d, and the inverted value is input to the CS1 terminal via the INV1 element 204. Further, the value of the (n + 1) th bit of the signal input to the In1 terminal is input to the INV2 element 205, and the output signal line 10 of the INV2 element 205
8 is output to the Out terminal as the (n + 1) th bit data of each of the nonvolatile storage units 3c and 3d as the value of the most significant bit of the output 109 from the counter element 201.

That is, when the power is turned on for the first time, n + 1 of the signals input to the In1 and In2 terminals
Since the value of the bit is both 0, EXNO
The EXNOR output 107 of the R element 203 becomes 1, and In
The value of 0 to n bits of the signal input to one terminal is output to the counter element 201. At this time, since the CS2 terminal is selected, the writing of the count value when the power is turned off is written to the nonvolatile storage unit 3d, and the (n + 1) th bit of the nonvolatile storage unit 3d is input to the In1 terminal. The inverted value 0 of the (n + 1) th bit of the signal thus written is written.

Next, when the power is turned on, In1
Since the value of the (n + 1) th bit of the signal input to the terminal and the terminal In2 becomes 0 and 1, respectively, the EXNOR element 20
The EXNOR output 107 of the counter element 3 becomes 0, and the counter element 2
In 01, the value of the signal input to the In2 terminal, which is the output of the nonvolatile storage unit 3d, is read. At this time, CS1
Since the terminal is selected, the writing of the count value when the power is turned off is written to the non-volatile storage unit 3c, and the In + 1 bit of the non-volatile storage unit 3c is In1.
The inverted value 1 of the (n + 1) th bit of the signal input to the terminal is written.

Next, when the power is turned on, In1
Since the value of the (n + 1) th bit of the signal input to the terminal and the terminal In2 is both 1, the EXNOR output 107 of the EXNOR element 203 becomes 1, and the counter element 201
The value of the signal input to the In1 terminal, which is the output of the non-volatile storage unit 3c, is read into. At this time, since the CS2 terminal is selected, the writing of the count value when the power is turned off is written to the non-volatile storage unit 3d, and the n + 1th bit of the non-volatile storage unit 3c includes the signal input to the In1 terminal. Of the (n + 1) th bit is written.

Next, when the power is turned on, In1
Since the value of the (n + 1) th bit of the signal input to the terminal and the terminal In2 becomes 1 and 0, respectively, the EXNOR element 20
The EXNOR output 107 of the counter element 3 becomes 0, and the counter element 2
In 01, the value of the signal input to the In2 terminal, which is the output of the nonvolatile storage unit 3d, is read. At this time, CS1
Since the terminal is selected, the writing of the count value when the power is turned off is written to the non-volatile storage unit 3c, and the In + 1 bit of the non-volatile storage unit 3c is In1.
The inverted value 1 of the (n + 1) th bit of the signal input to the terminal is written.

Thus, the value of the (n + 1) th bit of the signal input to the In1 terminal and the In2 terminal is
The sequence is repeated in the order of 0 and 0, 0 and 1, 1 and 1 and 1 and 0, and is alternately read from the non-volatile storage units 3c and 3d to the counter element 201 and the count value is written to the non-volatile memories 3c and 3d. It is. Therefore, if the number of times of writing to the non-volatile memories 3c and 3d is 2m, the number of times of writing to the non-volatile semiconductor memory 1 is 2m, which is half of the number of times, and the reliability of the count value can be improved. Other operations are the same as those of the nonvolatile semiconductor memory device 10 according to the first embodiment.

As described above, the nonvolatile semiconductor memory device 10b according to the third embodiment includes the nonvolatile memory 3
Since the number of times of writing and erasing to c and 3d can be reduced to half of the number of times of writing and erasing to the nonvolatile semiconductor memory 1, for example, the test result of the nonvolatile semiconductor memory is less than the guaranteed value of 100,000 times of the pass value. Even if the number of guarantees is 90,000, the count-up can be reliably performed up to 180,000 by having two non-volatile storage units, thereby improving the reliability of the count-up. Can be.

[0082]

As described above, the non-volatile semiconductor memory device according to the present invention is guaranteed even if the number of times of writing and erasing is smaller than the originally guaranteed number of times due to the dispersion of the management conditions in the manufacturing process. Since the limit value of the number of times can be changed and used based on the test result, the yield of the nonvolatile semiconductor memory device can be improved.

Although the storage capacity is reduced, the limit value of the number of times of writing and erasing can be increased.
Since the range of use is expanded, the yield of the nonvolatile semiconductor memory device can be further improved. Further, since the number of times of writing and erasing the nonvolatile memory unit can be made smaller than the number of times of writing and erasing the nonvolatile semiconductor memory, the reliability of the nonvolatile memory unit is improved, and as a result, In addition, the reliability of the nonvolatile semiconductor memory device can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a schematic block diagram of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a schematic circuit diagram for performing write control of a count value in a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 5 is a schematic block diagram of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 1 nonvolatile semiconductor memory 1a A block 1b B block 2 counter 3 nonvolatile storage unit 3a nonvolatile storage unit 3b nonvolatile storage unit 3c nonvolatile storage unit 3d nonvolatile storage unit 4 erase / write circuit 4a erase circuit 5 comparator 6 limit Value holding nonvolatile memory 7 Write circuit 10 Nonvolatile semiconductor memory device 10a Nonvolatile semiconductor memory device 10b Nonvolatile semiconductor memory device 10c Nonvolatile semiconductor memory device 26 Output terminal 41 Internal terminal 42 Initialization signal 43 Divided signal 51 Limit value signal 52 Count-up signal 53 External output signal 61 Limit value write signal 62 Limit value signal 72 Inhibit signal 105 Signal line 106 Signal line 107 EXNOR output 108 Output signal line 109 Output 201 Counter element 202 Selector element 203 EX OR element 204 INV1 element 205 INV2 element

Claims (6)

[Claims] A nonvolatile semiconductor memory having a finite number of times of data writing and erasing, a counter for counting up the number of times of processing, a non-volatile memory for storing the counted number of times of processing, and a finite number of times. A non-volatile memory having at least a limit value holding nonvolatile memory for storing the guaranteed number of times for the number of processes as a limit value and a comparator for outputting an external output signal when the counted number of processes becomes equal to the stored limit value. The nonvolatile semiconductor memory device, comprising: an erasing / writing circuit that initializes the nonvolatile storage unit and the limit value holding nonvolatile memory, and writes the limit value to the limit value holding nonvolatile memory; The non-volatile memory is set based on a test result of the non-volatile semiconductor memory. Conductor memory device. 2. A nonvolatile semiconductor memory having a finite number of data write and erase processes, a counter for counting up the number of processes, and a limit value holding nonvolatile memory for storing a guaranteed number of times for the finite number of processes as a limit value. A nonvolatile memory having at least a nonvolatile memory and a comparator that outputs an external output signal when the counted up number of processes becomes equal to the stored limit value, wherein the nonvolatile storage unit and the limit value holding nonvolatile An erase / write circuit that initializes a volatile memory, and writes the limit value to the limit value holding nonvolatile memory, and outputs a divided signal; and inputs a divided signal from the erase / write circuit, the nonvolatile semiconductor memory. Divide memory into multiple blocks,
A write circuit for writing and erasing the data for each of the blocks; and a nonvolatile storage unit for storing the counted number of times of processing, the same number of the plurality of blocks as the plurality of blocks, When the signal is output,
All the nonvolatile storage units store the counted number of times of processing, and the limit value written to the limit value holding nonvolatile memory is set based on a test result of the nonvolatile semiconductor memory. Nonvolatile semiconductor memory device. 3. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile storage section is formed of two non-volatile storage sections, and the counted number of processes is alternately rewritten and stored. A nonvolatile semiconductor memory device characterized by the above-mentioned. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a time required for writing and erasing the nonvolatile semiconductor memory is determined by a test result of the nonvolatile semiconductor memory. A nonvolatile semiconductor memory device characterized by the following. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said write circuit is connected to said comparator and said nonvolatile memory, and said count value is counted up. A non-volatile semiconductor memory device, wherein a signal output from the comparator is input when a limit value is reached, and a signal for inhibiting new writing and erasing is output to the non-volatile memory. 6. The non-volatile semiconductor memory device according to claim 1, wherein said non-volatile semiconductor memory is a flash PROM.