KR101125390B1 - Nonvolatile memory, memory control unit, memory control system, and nonvolatile memory controlling method - Google Patents

Abstract

An object of the present invention is to improve the reliability of data.

The nonvolatile memory 1 includes a memory cell array 2, a first sense amplifier 3, a second sense amplifier 4, and a recording unit 5. The memory cell array 2 includes a plurality of memory cells having floating gates. The first sense amplifier 3 determines the magnitude of the voltage value of the floating gate and the first threshold value for identifying the write state and erase state of the memory cell. The second sense amplifier 4 determines the magnitude of the voltage value of the floating gate and the second threshold value larger than the first threshold value. In the second sense amplifier 4, the recording unit 5 again writes data of the memory cell having the floating gate, which is determined that the second threshold value is larger than the voltage value of the floating gate.

Description

Nonvolatile Memory, Memory Control Device, Memory Control System, and Nonvolatile Memory Control Method {NONVOLATILE MEMORY, MEMORY CONTROL UNIT, MEMORY CONTROL SYSTEM, AND NONVOLATILE MEMORY CONTROLLING METHOD}

The present invention relates to a nonvolatile memory, a memory control device, a memory control system, and a control method of a nonvolatile memory. In particular, the present invention relates to a nonvolatile memory, a memory control device, a memory control system, and a nonvolatile memory. It relates to a control method.

Background Art In recent years, memory devices using nonvolatile memories such as USB (Universal Serial Bus) memories and flash memory cards have become widespread for reasons such as large capacities, nonvolatile and low power consumption.

These memory devices are required to have reliability for storing data for a long time.

In addition, by increasing the capacity of data such as images and videos, a larger capacity memory device is required, and the reduction of processes for nonvolatile memories is being actively made.

33 is a circuit diagram showing a basic cell structure of a NAND type nonvolatile memory.

The nonvolatile memory 90 has a configuration in which a plurality of NAND cells (memory transistors) 92 constituting the NAND cell group 91 are connected in series.

Designation of the NAND cell 92 is made by a select gate 93. In addition, erasing is performed for each NAND cell group 91.

Each NAND cell 92 includes a control gate 92a and a floating gate 92b, respectively.

34 is a diagram showing an aspect of data writing and erasing of the nonvolatile memory.

Fig. 34A is a diagram showing an aspect of data recording of the nonvolatile memory.

The floating gate 92b is insulated from the control gate 92a and the substrate 92c by a gate oxide 92d, and is electrically floating.

However, when a high voltage is applied between the control gate 92a and the substrate 92c, electric charge is injected from the substrate 92c to the floating gate 92b through the gate oxide film 92d by the Fowler-Nordheim (FN) tunnel phenomenon. can do.

Since the floating gate 92b is electrically floating, the electric charge can be retained even when the power supply is cut. The injection of electric charge is generally referred to as "write" or "program."

In addition, as shown in FIG. 34B, when a high voltage in the opposite direction to the recording is applied, similarly, the charge injected into the floating gate 92b by the FN tunnel phenomenon is transferred through the gate oxide film 92d. The release can be performed at 92c. The release of electric charge is generally referred to as "erasing" or "erasing".

In general, in the NAND type nonvolatile memory, a state in which charge is injected is written (logical "0"), and a state in which charge is released is erased (logical "1").

[Patent Document 1] Japanese Unexamined Patent Publication No. 2007-164937

Since the NAND type nonvolatile memory performs the writing and erasing of data using the FN tunnel current, the memory cell is degraded every time the writing and erasing is performed.

35 is a diagram illustrating deterioration of the gate oxide film due to the FN tunnel phenomenon.

In the FN tunnel phenomenon, charge can be transferred through the gate oxide film 92d by applying a high voltage, but some charge is trapped in the gate oxide film 92d.

For this reason, as the number of rewrites increases, the degradation of the gate oxide film 92d and the leakage current increase (Increase of Leak Current).

Due to the deterioration of the gate oxide film 92d, the leakage current between the floating gate 92b and the substrate 92c increases, so that charge cannot be maintained.

This phenomenon generally limits the number of times of write / erase (hereinafter referred to as the number of rewrites) to the nonvolatile memory, and reduces the data holding capability in proportion to the number of rewrites.

36 is a graph showing the relationship between the elapsed time and the voltage change of the floating gate. As an example, the voltage level of the floating gate in the erased state of the NAND type nonvolatile memory is 4V, and the setting value of the sense amplifier SA for identifying the write state and the erased state is 1V.

As described above, due to the leakage current between the floating gate and the substrate, the voltage level of the floating gate gradually decreases with time.

In Fig. 36, the sense amplifier determines the logic "1" and "0" of the data depending on whether or not the voltage of the floating gate is 1 V or more. For this reason, as time passes, the logic of the NAND cell is reversed, resulting in a read error.

37 is a graph showing the relationship between the number of rewrites and the data holding time.

When the number of times of rewriting is 10,000, the data holding time decreases as the number of times of rewriting increases, while the data can be held for about 20 years. After about 100,000 rewrites, the data can only be kept for 0.5 years when the rewrite frequency is 1 million times for about 10 years.

Although the manufacturing process is miniaturized for the purpose of low cost and high capacity, the thickness of the gate oxide film does not change significantly, and the voltage required for writing or erasing does not change significantly.

For this reason, there is a problem that the voltage applied to the gate oxide film becomes relatively high, deterioration becomes remarkable as the process becomes smaller, and the data holding capability deteriorates.

Therefore, in a nonvolatile memory requiring low cost, large capacity, and long term data storage, the deterioration of the data storage capacity by miniaturizing the manufacturing process should be prevented.

SUMMARY OF THE INVENTION The present invention has been made in view of this point, and an object thereof is to provide a nonvolatile memory, a memory control device, a memory control system, and a control method of a nonvolatile memory that can improve data reliability.

In order to achieve the above object, a memory cell array having a plurality of memory cells having a floating gate, and a magnitude between a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell are determined. A first sense amplifier to determine, a second sense amplifier to determine the magnitude of the voltage value of the floating gate and a second threshold value greater than the first threshold value, and the second threshold value in the second sense amplifier. And a writing unit for rewriting data of the memory cell having the floating gate that is determined to be greater than the voltage value of the floating gate.

According to the disclosed nonvolatile memory, memory control device, and memory control system, data reliability can be improved.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment is described in detail with reference to drawings.

First, the nonvolatile memory of the embodiment will be described, and then the embodiment will be described in more detail.

1 is a diagram showing an outline of a nonvolatile memory of an embodiment.

The nonvolatile memory 1 shown in FIG. 1 includes a memory cell array 2, a first sense amplifier 3, a second sense amplifier 4, and a recording unit 5.

The memory cell array 2 includes a plurality of memory cells having floating gates. The first sense amplifier 3 determines the magnitude of the voltage value of the floating gate and the first threshold value for identifying the write state and erase state of the memory cell.

The second sense amplifier 4 determines the magnitude of the voltage value of the floating gate and the second threshold value larger than the first threshold value.

In addition, the first threshold value and the second threshold value may be input from the outside as shown in FIG. 1, or may be generated inside the nonvolatile memory 1.

In the second sense amplifier 4, the recording unit 5 again writes data of the memory cell having the floating gate, which is determined that the second threshold value is larger than the voltage value of the floating gate.

By the nonvolatile memory 1, since the write state of the memory cell having a voltage value lower than the second threshold value is maintained, the reliability of data can be improved.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment is described more concretely.

2 is a diagram illustrating a hardware configuration example of the module of the embodiment.

In the module 10, the entire apparatus is controlled by a central processing unit (CPU) 11. A chip set 12 is connected to the CPU 11.

Chipset 12 includes a North Bridge 12a and a South Bridge 12b.

The north bridge 12 is connected with peripheral devices operating at a relatively high speed, and exchanges data with these devices. In FIG. 2, a memory 13, a PCI Express 14, and a display 15 are connected.

The memory 13 temporarily stores at least a part of an OS (Operating System) program or an application program to be executed by the CPU 11. The memory 13 also stores various data necessary for processing by the CPU 11.

The north bridge 12a causes an image to be displayed on the screen of the display 15 in accordance with an instruction from the CPU 11.

Peripheral devices operating at a relatively low speed are connected to the south bridge 12b. In Fig. 2, an audio interface (Audio I / F) 16, a USB / PCI 17, a BIOS 18, a LAN interface 19, and a nonvolatile module 20 are connected.

The nonvolatile module 20 is referred to as a NAND controller 21 and a NAND flash memory IC 22 connected to the NAND controller 21 (hereinafter, simply referred to as "nonvolatile memory"). It includes).

The NAND controller 21 selects an arbitrary area of the nonvolatile memory 22 and confirms that the data in that area is correct. For checking whether the data is correct, ECC information included in the data of the management area associated with the selected area is used.

The nonvolatile memory 22 stores an OS and an application program. The nonvolatile memory 22 also stores program files.

In addition, the north bridge 12a and the south bridge 12b may be comprised by one chip, without being limited to the structure of FIG. The NAND controller 21 and the nonvolatile memory 22 may be configured separately.

In addition, a hard disk driver (HDD) (not shown) may be installed separately from the nonvolatile module 20.

By the hardware configuration as described above, the processing function of the present embodiment can be realized.

3 is a block diagram showing the configuration of a NAND controller.

The NAND controller 21 includes a host interface unit 211, a control register 212, a power management unit 213, a buffer 214, And an ECC processing unit 215 and a NAND interface unit 216.

The host interface unit 211 communicates with the CPU 11.

The control register 212 holds the instruction from the CPU 11 and indicates the state of the NAND controller 21.

The power control unit 213 supplies power to the entire NAND controller 21.

The buffer 214 temporarily stores data exchanged between the CPU 11 and the nonvolatile memory 22.

The ECC processing unit 215 generates an ECC from the data and performs encoding / decoding of the ECC code and error correction processing.

The NAND interface unit 216 communicates with the nonvolatile memory 22.

4 is a block diagram showing a configuration of a nonvolatile memory.

The nonvolatile memory 22 includes an I / O buffer circuit 221, a command register 222, a control logic 223, and an address register. 224, a NAND Flash Array 225, an X Decoder 226, a Y Decoder 227, and a Sense Amp Circuit 228).

The I / O buffer circuit 221 receives various commands, address signals, data to be written to the NAND flash array 225, and the like, and outputs data read and latched from the NAND flash array 225.

The command register 222 latches the input command and determines the internal operation from the contents of the input signal.

In addition, "/" is attached to the signal of Lo active in front of the signal name.

The signal / CL is a signal for selecting the command register 222 or the controller 223.

The signal / AL is a signal for selecting the address register or data register of the nonvolatile memory 22.

The signal / CE is a signal for selecting any one of an active mode and a standby mode of the nonvolatile memory 22.

The signal / RE is a signal for outputting data.

The signal / WE is a read / write designation signal, and becomes the write mode when it is active.

The signal / WP is a signal forcibly prohibiting write and erase operations.

The signal / SES is a signal that controls which of the main sense amplifier and the sub sense amplifier described later is valid.

The controller 223 reads, writes, erases, etc. each memory cell in the nonvolatile memory 22 based on each input signal.

In addition, the controller 223 includes a high voltage generator 223a. This high voltage generation circuit 223a supplies driving voltages to the X decoder 226 and the NAND flash array 225.

The control unit 223 also outputs a signal R / B informing the outside of the operation of the internal state of the control unit 223.

The address register 224 generates a row address and a column address for reading, writing and erasing based on the input address signal, and automatically increments the address in the page mode.

The X decoder 226 decodes the row address output from the address register 224 to select a word line (not shown) of the memory cells of the NAND flash array 225.

The Y decoder 227 decodes the column address output from the address register 224, and writes and reads data into the memory cell through the selected data line (not shown).

The sense amplifier circuit 228 is selected through column selection, receives the data in the memory cell at the intersection with the row selected word line to the main sense amplifier described later, and sends it to the I / O buffer circuit 221. Also in the case of writing, the word line of the row selected in the manner described above, and the memory cell connected to the sense amplifier circuit 228 selected by the Y decoder 226 are selected, and from the data line through the data input circuit. The received information is written to the memory cell of the NAND flash array 225.

5 is a block diagram showing the configuration of a sense amplifier circuit.

The sense amplifier circuit 228 includes a main reference cell 2231, a sub reference cell 2228, a main sense amplifier 2283, and a sub sense amplifier. (Second sense amplifier) 2284 and a logic circuit 2285 are included.

The main reference cell 2231 supplies a voltage of 1 V to the main sense amplifier 2283.

The sub reference cell 2228 supplies a voltage of 2 V (voltage higher than the voltage supplied by the main reference cell 2231) to the sub sense amplifier 2284.

The main sense amplifier 2283 is a current detection type sense amplifier and is used for reading, writing, and erasing data stored in the NAND flash array 225. For example, in the data read operation, the output current of the NAND flash array 225 is compared with the current flowing through the main reference cell 2231, and the logic of the comparison result is output to the logic circuit 2285. Specifically, if the output current of the NAND flash array 225 is large or each current is equal, the logic "1" is output. If the current flowing through the main reference cell 2231 is large, the logic "0" is output.

The sub sense amplifier 2284 is a current detection type sense amplifier and is used for margin measurement. The sub sense amplifier 2284 compares the output current of the NAND flash array 225 with the current flowing through the sub reference cell 2228 and outputs the logic of the comparison result to the logic circuit 2285. Specifically, if the output current of the NAND flash array 225 is large or each current is the same, the logic "1" is output. If the current flowing through the sub reference cell 2228 is large, the logic "0" is output.

The logic circuit 2285 selects one of the output signal of the main sense amplifier 2283 and the output signal of the sub sense amplifier 2284 in accordance with the input of the signal / SES, and outputs the selected signal Data-0. As a result, normal reading, writing, erasing and margin measurement can be switched. That is, the normal sense amplifier 2283 is selected for normal read, write, and erase, and the sub sense amplifier 2284 is periodically selected to check the voltage level of the floating gate.

When the voltage level of the floating gate is lower than the voltage of 2 V of the sub-reference cell 2228, data is retained by rewriting.

In addition, the process of this subsense amplifier 2284 is performed by the refresh process mentioned later.

Next, an example of setting a status register included in the NAND controller 21 will be described.

6 is a diagram illustrating an example of setting a status register.

Status register 30 is an 8-bit register. In FIG. 6, a value indicating that the refresh process is being executed is set (set) in the first bit REFR of the status register 30. For example, if the value of REFR is "1", the refresh process is executed. If it is "0", the refresh process is not performed.

In addition, the fifth bit DWF is set to " 1 " when a write error occurs in the nonvolatile memory 22. FIG.

Next, the data configuration of the NAND flash array 225 will be described.

The interior of the NAND flash array 225 is managed in units of a plurality of blocks. And one block contains multiple pages.

7 and 8 are diagrams showing the structure of a page.

The recording unit of the nonvolatile memory 22 is 2 KBytes. This recording unit includes four pages in which one page consists of 528 bytes. One page includes 512 bytes of sector and 16 bytes of spare.

Four sectors A, B, C, and D are assembled to form a data field of 2 K bytes. In addition, four spares a, b, c, and d are assembled to form a 64 byte spare field.

Spare a is a spare area of sector A, spare b is a spare area of sector B, spare c is a spare area of sector C, and spare d is a spare area of sector D.

Here, at the time of data recording, the logic of the first byte of the sector A is recorded in a manner of fixing to "0". User data is recorded in the second to 512 bytes, respectively. The refresh process is performed by checking the voltage value of the first byte of sector A.

Thus, by fixing the logic of a 1st byte to "0", the cell of this position deteriorates stably (at constant speed). As a result, the margin with higher accuracy can be measured.

As shown in Fig. 8, each spare (a spare a in Fig. 8) has a Logical Sector Number (LSN), Data Validity (DV), Bad Block Information (BBI), ECC Code for Data Field (ECC), and ECCS (ECC). Setting areas such as Code for Spare Field (RSV), Reserved Area (RSV), and Refresh Counter (RC) are included.

Among these, the refresh counter of the eighth byte stores the number of times the refresh processing is performed.

9 is a diagram showing a command function to be given to a nonvolatile memory.

In the command function table 40, a column of a function, a first cycle (1 ^st cycle), and a second cycle (2 ^nd cycle) is set. The information in the transverse column is related to each other.

The command is input in series to the I / O buffer circuit 221 divided into two circuits, a first cycle and a second cycle. The command serially input to the I / O buffer circuit 221 is transferred to the command register 222. As a result, any one of the main sense amplifier 2283 and the sub sense amplifier 2284 can be selected without adding an input terminal to the external terminal.

Specifically, the read operation of the main sense amplifier 2283 (Read with Main SA) is performed by the command code "00h" is issued in the first cycle and the command code "30h" is issued in the second cycle.

The read operation (Read with Sub SA) of the sub sense amplifier 2284 is performed by issuing a command code "00h" in the first cycle and a command code "31h" in the second cycle.

The command codes "30h" and "31h" are examples, and different codes can also be assigned.

Next, according to the instruction of the NAND controller 21, the refresh process which the nonvolatile memory 22 performs is demonstrated.

10 is a flowchart showing a refresh process determination process.

First, the NAND controller 21 measures the elapsed time by a clock or the like of the CPU 11 (step S1).

Then, it is determined whether or not the elapsed time prepared beforehand (whether or not the refresh processing needs to be executed) is determined (step S2). This elapsed time is, for example, the elapsed time from the time when the previous refresh process is executed.

If the elapsed time prepared beforehand is not reached (No in step S2), the process proceeds to step S1, and the process after step S1 is continued.

On the other hand, when the elapsed time prepared beforehand is reached (Yes in step S2), the value of "REFR" of the status register 30 is set to "1" (step S3).

Next, a refresh process is performed (step S4).

After completion of the refresh processing, the value of "REFR" in the status register 30 is set to "0" (step S5).

This concludes the description of the refresh processing determination process.

It is also possible to instruct the CPU 11 to execute the refresh processing at a predetermined timing without executing the above processing.

11 and 12 are flowcharts showing a refresh process.

First, data of the NAND flash array 225 (for example, data of the data configuration shown in Fig. 7 or 8) is read using the main sense amplifier 2283 (step S11).

Next, an ECC is generated from the read data (step S12).

Next, it is determined whether an ECC error has occurred (step S13).

If an ECC error has occurred (Yes in step S13), a read error signal is sent to the CPU 11 (step S14). After that, the process ends.

On the other hand, when no error occurs (No in step S13), the data of the NAND flash array 225 is read out using the subsense amplifier 2284 (step S15).

Next, an ECC is generated from the read data (step S16).

Next, it is determined whether an ECC error has occurred (step S17).

If no ECC error occurs (No in step S17), the process ends (assuming that the voltage margin of the floating gate is sufficiently secured).

If an ECC error has occurred (Yes in step S17), the data of the NAND flash array 225 is read again using the main sense amplifier 2283 (assuming that the margin is insufficient) (step S18).

Then, an ECC is generated from the read data (step S19).

Next, it is determined whether an ECC error has occurred (step S20).

If an ECC error has occurred (Yes in step S20), the process proceeds to step S14, and a read error signal is sent to the CPU 11 (step S14). After that, the process ends.

If no ECC error occurs (No in step S20), the data read out by the main sense amplifier 2283 is written again to the block at this address of the NAND flash array 225 (step S21).

Next, the value of "DWF" in the status register 30 of the NAND flash array 225 is read (step S22).

Then, it is judged whether or not a recording error has occurred (step S23).

If no recording error occurs (No in step S23), the processing ends.

If a write error occurs (Yes in step S23), a write error signal is sent to the CPU 11 (step S24). After that, the process ends.

This is the end of the explanation of the refresh processing.

In addition, in this embodiment, although the process of step S3 was performed after the process of step S2, the process of step S3 may be performed first and the process of step S2 may be performed after that.

It is a figure which shows the effect of a refresh process.

The horizontal axis of the graph shown in FIG. 13 represents elapsed time or the number of write and read cycles, and the vertical axis represents the voltage value of the floating gate.

In addition, in Fig. 13, the "refresh process" shows the timing at which it is determined whether or not rewriting is necessary.

When the voltage level of the floating gate is 2 V or more, since there is sufficient margin, it is not rewritten.

On the other hand, when the voltage level of the floating gate is 2 V or less, the margin is insufficient, so that data is rewritten to retain data.

Thus, when the voltage value of the floating gate is located between the voltage of 1 V supplied by the main reference cell 2231 and the voltage of 2 V supplied by the sub-reference cell 2228, the floating gate is refreshed and rewritten to perform the rewriting. When the voltage margin of the gate is sufficiently secured, data can be recorded again.

The voltage value of the sub-reference cell 2228 is not particularly limited, but is preferably set to be closer to the voltage value of the main reference cell 2231 than the voltage value to be written. As a result, the number of writes can be reduced again, and the life of the nonvolatile memory 22 can be extended.

As stated above, according to the module 10, even when the data holding performance of the NAND flash array 225 is degraded by the deterioration of the insulating film by performing the refresh processing, it is possible to continue the data by rewriting the data. .

In addition, the byte which always maintains a recording state was prepared in the 1st byte of sector A, and this byte was used for margin measurement. This makes it possible to measure high-precision margins, thereby increasing the reliability of the data.

It goes without saying that the configuration of the present embodiment can be easily applied as long as it is a nonvolatile memory provided with a plurality of sense amplifiers in advance.

By the way, you may display on the display 15 that a refresh process is currently being performed.

14 is a flowchart showing processing when displaying on the display that the refresh processing is currently being executed.

The CPU 11 refers to "REFR" in the status register 30 of the NAND controller 21 (step S31).

Then, it is determined whether or not the value of "REFR" is "1" (step S32).

If the value of "REFR" is "0" (No in step S32), the processing ends.

On the other hand, when the value of "REFR" is "1" (Yes in step S32), since the refresh process is executed, it notifies the CPU 11. The CPU 11 displays a message on the display 15 indicating that the refresh processing is being executed (step S33). After that, the process ends.

As a result, the user can easily grasp whether or not the refresh process is currently being executed.

In addition, a screen for prompting replacement of the nonvolatile memory 22 may be displayed on the display 15.

Fig. 15 is a flowchart showing processing when displaying on the display a screen prompting replacement of the nonvolatile memory.

The CPU 11 refers to the value "C" of the refresh counter of the nonvolatile memory 22 (step S41).

Then, the value "C" of the refresh counter is compared with the value "M" (for example, M = 100) prepared in advance, and it is determined whether the value "C" is larger than the value "M" (step S42).

If the value "C" is less than the value "M" (No in step S42), the process ends.

On the other hand, when the value "C" is larger than the value "M" (Yes in step S42), it is determined that the nonvolatile memory 22 needs to be replaced, and the CPU 11 is notified. The CPU 11 displays a message on the display 15 prompting the exchange of the nonvolatile memory 22 (step S43). After that, the process ends.

As a result, the user can easily grasp the replacement timing of the nonvolatile memory 22.

≪ Second Embodiment >

Next, the system of 2nd Embodiment is demonstrated.

Hereinafter, the system of 2nd Embodiment is demonstrated centering on difference with the system of 1st Embodiment mentioned above, and the description is abbreviate | omitted about the same matter.

In the system of the second embodiment, the configuration of the sense amplifier circuit is different from that of the sense amplifier circuit 228 of the first embodiment, except for the same as in the first embodiment.

Fig. 16 is a block diagram showing the structure of the sense amplifier circuit of the second embodiment.

The sense amplifier circuit 228a is not provided with a logic circuit 2285. Instead, the signal / SES specifying the sense amplifier for outputting the signal Data-0 is directly input to the main sense amplifier 2283 and the sub sense amplifier 2286.

The subsense amplifier 2286 is provided with an inverting input terminal for inverting the logic of the signal / SES and inputting the same. Thereby, the signal whose logic is "1" is input to either one, and the signal which is "0" is input to the other. As a result, the signal of one selected sense amplifier is output as the signal Data-O.

According to the system of this second embodiment, the same effects as those of the system of the first embodiment can be obtained.

≪ Third Embodiment >

Next, the system of 3rd Embodiment is demonstrated.

Hereinafter, the system of 3rd Embodiment is demonstrated centering on difference with the system of 1st Embodiment mentioned above, and the description is abbreviate | omitted about the same matter.

The system of the third embodiment is different from the first embodiment in the configuration of the nonvolatile memory, and is otherwise the same as the first embodiment.

17 is a block diagram showing a nonvolatile memory of the third embodiment.

The control unit 223 of the nonvolatile memory 22a of the third embodiment reads data of a block of an address (hereinafter, referred to as a "rewrite address") from the outside and stores it in the I / O buffer circuit 221. Then, after erasing data of the block of this address, a rewrite circuit 223b for rewriting the data stored in the I / O buffer circuit 221 into the block of this address is included.

Fig. 18 is a diagram illustrating a command function of the nonvolatile memory of the third embodiment.

In the command function table 40a, a command (rewrite command) for rewriting data for a block of a rewrite address is added.

Rewriting of data to a block of a rewrite address is performed by issuing command code "50h" in the first cycle and issuing command code "10h" in the second cycle.

Next, the refresh process of 3rd Embodiment is demonstrated.

19 is a flowchart illustrating a refresh process of the third embodiment.

Hereinafter, the description will be mainly given of parts different from the refresh processing of the first embodiment.

If an ECC error occurs (Yes in step S17), a rewrite command is issued to the nonvolatile memory 22 (assuming that the margin is insufficient). As a result, the rewrite circuit 223b of the nonvolatile memory 22 performs a rewrite process (step S18a).

Thereafter, the flow advances to step S22 to perform the processing after step S22.

Next, the rewriting process of step S18a is demonstrated.

20 is a flowchart showing a rewrite process.

First, the command register 222 receives the refresh command 81h of the first cycle from the NAND controller 21 (step S51).

Next, the address register 224 receives the rewrite address from the NAND controller 21 (step S52).

Next, the command register 222 receives the refresh command 10h of the second cycle from the NAND controller 21 (step S53).

Next, data is read from the NAND flash array 225 to the I / O buffer circuit 221 (step S54).

Next, in the state where data is held in the I / O buffer circuit 221, the data of the block of this address is erased (step S55).

Next, it is judged whether or not an erase error has occurred (step S56).

If an erase error occurs (Yes in step S56), a flag indicating that an error has occurred is set in "DWF" in the status register 30 (step S57). After that, the process ends.

On the other hand, when an erase error has not occurred (No in step S56), the data held by the I / O buffer circuit 221 is written to the block of the rewrite address (step S58).

Next, it is judged whether or not a recording error has occurred (step S59).

If a recording error has occurred (Yes in step S59), the process proceeds to step S57 and the process subsequent to step S57 is performed.

On the other hand, if no recording error occurs (No in step S59), the processing ends.

In addition, in this embodiment, although the process shown by step S53 was performed after the process shown by step S52, you may perform the process shown by step S52 after the process shown by step S53.

According to the system of this third embodiment, the same effects as in the system of the first embodiment can be obtained.

≪ Fourth Embodiment &

Next, the system of 4th Embodiment is demonstrated.

Hereinafter, the system of 4th Embodiment is demonstrated centering on difference with the system of 3rd Embodiment mentioned above, and the description is abbreviate | omitted about the same matter.

The system of the fourth embodiment is different from that of the third embodiment in the configuration of the nonvolatile memory, and is otherwise the same as the third embodiment.

Fig. 21 is a block diagram showing a nonvolatile memory of the fourth embodiment.

The nonvolatile memory 22b reads the data of the block of the rewrite address and stores it in the I / O buffer circuit 221. In addition to the I / O buffer circuit 221, a replacement register 229 for rewriting data in a block having an address different from this externally designated address (hereinafter referred to as a "substitution address") is provided. Include.

Fig. 22 is a diagram illustrating a command function of the nonvolatile memory of the fourth embodiment.

In the command function table 40b, a command (replace command) for rewriting data in a block of replacement addresses is added.

Rewriting of data for a block of replacement addresses is performed by issuing command code "83h" in the first cycle and issuing command code "10h" in the second cycle.

Next, the refresh process of 4th Embodiment is demonstrated.

The refresh process of the fourth embodiment is different from the third embodiment in the rewrite process in step S18a shown in FIG.

The rewrite process of the fourth embodiment will be described below.

23 is a flowchart showing the rewrite process of the fourth embodiment.

First, the command register 222 receives the replace command 83h of the first cycle from the NAND controller 21 (step S61).

Next, the address register 224 receives the address to be rewritten from the NAND controller 21 (step S62).

Subsequently, the substitution register 229 receives the substitution address from the NAND controller 21 (step S63).

Next, the command register 222 receives the replace command 10h of the second cycle from the NAND controller 21 (step S64).

Next, data is read into the I / O buffer circuit 221 from the block of the designated rewrite address of the NAND flash array 225, and the data is held in the I / O buffer circuit 221 (step S65).

Next, the control unit 223 switches the address to the replacement address, and writes data held by the I / O buffer circuit 221 into the block of the replacement address (step S66).

Next, it is judged whether or not a recording error has occurred (step S67).

If a write error occurs (Yes in step S67), a flag indicating that an error has occurred is set in "DWF" in the status register 30 (step S68). After that, the process ends.

On the other hand, when no write error occurs (No in step S67), the data of the block of the rewrite address is erased (step S69).

Next, it is judged whether or not an erase error has occurred (step S70).

If an erase error has occurred (Yes in step S70), the flow advances to step S68 to perform the processing after step S68.

On the other hand, when an erase error has not occurred (No in step S70), the mapping table describing the relationship between the logical address and the physical address is updated based on the instruction of the NAND controller 21 (step S71). After that, the process ends.

Hereinafter, the updating process of the mapping table which the NAND controller 21 performs is demonstrated.

24 is a flowchart showing an update process of a mapping table.

First, a replace command is sent to the nonvolatile memory 22 to read the bit contents of the status register 30 (step S81).

Next, it is judged whether or not a recording error has occurred (step S82).

If a write error occurs (Yes in step S82), a write error is sent to the CPU 11 (step S83). After that, the process ends.

If no recording error occurs (No in step S82), the mapping table is updated (step S84). Specifically, the physical address corresponding to the logical address is replaced with the replacement address from the address from which data is read. Thereafter, the processing ends.

According to the system of this fourth embodiment, the same effects as in the system of the third embodiment can be obtained.

In addition, since the deterioration proceeds when the nonvolatile memory 22 repeatedly writes and erases the same address block, it is preferable that the rewrite times of all addresses be averaged.

According to the system of the fourth embodiment, the number of rewrites can be averaged by rewriting the data in a block of an address different from the address from which the data is read. As a result, the lifespan of the nonvolatile memory 22 is long, and reliability can be further improved.

Fifth Embodiment

Next, the system of 5th Embodiment is demonstrated.

Hereinafter, the system of 5th Embodiment is demonstrated centering on difference with the system of 1st Embodiment mentioned above, and the description is abbreviate | omitted about the same matter.

In the system of the fifth embodiment, the configuration of the NAND controller is different from that of the first embodiment, except for the same as in the first embodiment.

FIG. 25 is a block diagram showing the structure of the NAND controller according to the fifth embodiment. FIG.

The NAND controller 21a includes a refresh interval register 217 in which a threshold for determining whether the predetermined number of times has been exceeded can be set by the CPU 11.

The NAND controller 21a also records, as access count information, the number of times any one of read, erase, and write is performed on the nonvolatile memory at a predetermined position (described later) of the nonvolatile memory.

Then, the NAND controller 21a performs the refresh process when the access count information read from the nonvolatile memory 22 exceeds the value set in the refresh interval register 217.

Fig. 26 is a diagram illustrating an example of setting access count information.

In the fifteenth and sixteenth bytes of the spares a, b, c, and d, an access counter (AC) for recording access count information is set. 26 shows an example of setting spare a as an example.

Next, the refresh process necessity determination process of 5th Embodiment is demonstrated.

Fig. 27 is a flowchart showing the refresh process necessity determination process according to the fifth embodiment.

First, the access count information is read with reference to the access counter of the NAND flash array 225 (step S91).

Next, the access count information value "A" is compared with the previously prepared value "N" (for example, N = 1000), and it is determined whether the access count information value "A" is larger than the value "N" (step S92). .

If the value "A" is less than the value "N" (No in step S92), the process ends.

On the other hand, when the value "A" is larger than the value "N" (Yes in step S92), the value of "REFR" of the status register 30 is set to "1" (step S93).

Next, a refresh process is performed (step S94). In addition, the content of a refresh process is the same as that of the refresh process shown in FIG.

After the completion of the refresh processing, the value of "REFR" in the status register 30 is set to "0" (step S95).

After that, the process ends.

This concludes the description of the refresh processing determination process.

According to the system of this fifth embodiment, the same effects as in the system of the first embodiment can be obtained.

According to the system of the fifth embodiment, since the refresh processing is performed based on the actual number of times of access, the reliability of data can be further improved.

Sixth Embodiment

Next, the system of 6th Embodiment is demonstrated.

Hereinafter, the system of 6th Embodiment is demonstrated centering on difference with the system of 5th Embodiment mentioned above, and the description is abbreviate | omitted about the same matter.

In the system of the sixth embodiment, the function of the CPU 11 is different from that of the fifth embodiment, except for the same as in the fifth embodiment.

The CPU 11 of the sixth embodiment reads the counter value of the refresh counter from the nonvolatile memory 22, and when the value exceeds a predetermined value, the refresh interval register 217 of the NAND controller 21a. Change the value.

28 is a flowchart showing a refresh interval changing process.

First, the counter value is read with reference to the refresh counter of the NAND flash array 225 (step S101).

Next, the counter value "Co" of the refresh counter and the previously prepared value "P" (for example, P = 10) are compared to determine whether the counter value "Co" is larger than the value "P" (step S102).

If the counter value "Co" is less than the value "P" (No in step S102), the processing ends.

On the other hand, when the counter value "Co" is larger than the value "P" (Yes in step S102), the value "I" of the refresh interval register 217 of the NAND controller 21 is read (step S103).

Next, the refresh interval is changed (step S104). Specifically, for example, by setting "X = 0.5", the read value "I" is made into half.

Next, the value of the register changed in step S104 is written to the refresh interval register 217 (step S105). After that, the process ends.

29 is a diagram illustrating the effect of the refresh interval changing process.

By performing the refresh interval changing process, the timing at which the refresh processing for the second to third and third to fourth times is performed is made half of the first to second times.

According to the system of this sixth embodiment, the same effects as those of the system of the fifth embodiment can be obtained.

According to the system of the sixth embodiment, even when the number of writes increases and the period in which the data can be retained due to deterioration of the insulating film is shortened, the reliability of data is further improved by shortening the interval for performing the refresh process. Can be.

Seventh Embodiment

Next, the system of 7th Embodiment is demonstrated.

Hereinafter, the system of 7th Embodiment is demonstrated centering on difference with the system of 1st Embodiment mentioned above, and the description is abbreviate | omitted about the same matter.

The system of the seventh embodiment is different from that of the first embodiment in the configuration of the NAND controller, and is otherwise the same as the first embodiment.

30 is a block diagram showing the configuration of a NAND controller according to a seventh embodiment.

The NAND controller 21b also includes an I2C interface unit 218 for acquiring current date / time information from a real-time clock IC (not shown) included in the module 10.

The NAND interface unit 216 sets the current date and time information acquired by the I2C interface unit 218 in a predetermined area of the nonvolatile memory 22.

31 is a diagram for explaining setting of current date and time information in a nonvolatile memory.

In the fifteenth and sixteenth bits of the spares a, b, c, and d, a LRD (Latest Refresh Date) for storing the date and time of the last refresh processing is set. 31 shows an example of setting spare a as an example.

Next, the refresh necessity determination process of the seventh embodiment will be described.

32 is a flowchart showing a refresh process determination process according to the seventh embodiment.

First, the I2C interface unit 218 reads the current date / time information "Cu" from the real-time clock IC (step S111).

Next, the date and time information "L" stored in the LRD is read (step S112).

Then, the value "Cu-L" obtained by subtracting the date and time information "L" from the current date and time information "Cu" is compared with the predetermined value "Q" (for example, Q = 7 days), and the value "Cu-L" is a value. It is judged whether or not it is larger than "Q" (step S113).

If the value "Cu-L" is less than the value "Q" (No in step S113), the process ends.

On the other hand, when the value "Cu-L" is larger than the value "Q (Yes in step S113), the value of" REFR "of the status register 30 is set to" 1 "(step S114).

Next, a refresh process is performed (step S115). In addition, the content of a refresh process is the same as that of the refresh process shown in FIG.

After the completion of the refresh processing, the value of "REFR" in the status register 30 is set to "0" (step S116).

After that, the process ends.

This concludes the description of the refresh processing determination process.

According to the system of this seventh embodiment, the same effects as in the system of the first embodiment can be obtained.

According to the system of the seventh embodiment, it is possible to reliably prevent the potential from falling and the logic being reversed as time passes even without data access. This can further increase the reliability.

As mentioned above, although the control method of the nonvolatile memory, the memory control apparatus, the memory control system, and the nonvolatile memory of this invention was demonstrated based on embodiment illustrated, this invention is not limited to this, The structure of each part May be replaced with any configuration having the same function. In addition, other arbitrary components or processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (characteristics) of the above-described embodiments.

In addition, although each embodiment mentioned above demonstrated using the computer system, this invention is applicable also to information processing apparatuses, such as a mobile telephone and a PDA.

Regarding the above first to seventh embodiments, the following bookkeeping is further disclosed.

(Book 1)

A memory cell array having a plurality of memory cells having a floating gate;

A first sense amplifier for determining the magnitude of the voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell;

A second sense amplifier for determining the magnitude of the voltage value of the floating gate and a second threshold value greater than the first threshold value;

In the second sense amplifier, a recording unit for rewriting the data of the memory cell having the floating gate determined that the second threshold value is greater than the voltage value of the floating gate

Nonvolatile memory comprising a.

(Book 2)

The determination of the second sense amplifier is made after the first sense amplifier determines that the first threshold value is larger than the voltage value of the floating gate.

(Supplementary Note 3)

The nonvolatile memory according to Appendix 1, wherein one of the output of the first sense amplifier and the output of the second sense amplifier is selected based on the input selection signal.

(Note 4)

And a selection circuit for selecting any one of an output of said first sense amplifier and an output of said second sense amplifier based on said selection signal.

(Note 5)

And a command register for receiving a command and outputting said selection signal in accordance with said command.

(Note 6)

A data reading unit which reads data of a block of a specified address of the memory cell array;

A temporary storage unit for temporarily storing the read data;

The data reading unit reads the data, which is determined to be greater than the voltage value of the floating gate, in units of blocks, and stores the data in the temporary storage unit.

The recording unit erases the data of the block of the address, and then writes the data stored in the temporary storage unit to the block of the address again.

(Appendix 7)

A data reading unit which reads data of a block of a specified address of the memory cell array;

A temporary storage unit for temporarily storing the read data;

The data reading unit reads the data, which is determined to be greater than the voltage value of the floating gate, in units of blocks, and stores the data in the temporary storage unit.

The recording unit erases the data of the block of the address, and then writes the data stored in the temporary storage unit again to a block of an address different from that of the block of the address.

(Appendix 8)

When writing data to a block of addresses of the memory cell array, the predetermined memory cell of the block is set to a write position which always writes data,

And the second sense amplifier determines the magnitude of the voltage value of the floating gate of the memory cell at the write position and the second threshold value.

(Note 9)

A memory cell array having a plurality of memory cells having a floating gate, a first sense amplifier for determining the magnitude of a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell; A non-volatile memory having a second sense amplifier for determining the magnitude of a voltage value of the floating gate and a second threshold value larger than the first threshold value, and a recording unit for writing the indicated data to the memory cell, And a write instruction instructing, in the second sense amplifier, data writing of the memory cell having the floating gate, the second threshold value being greater than the voltage value of the floating gate, to the recording unit. Memory control unit.

(Book 10)

The nonvolatile memory further includes a data reading unit reading data of a block of a designated address of the memory cell array, and a temporary storage unit reading and temporarily storing data of a block of a designated address of the memory cell array,

The write instruction section reads the data of the block of the address including the data determined that the second threshold value is greater than the voltage value of the floating gate, into the temporary storage unit to read the data of the block of the address. The memory control apparatus according to Appendix 9, wherein after the data is erased, the recording unit causes the data stored in the temporary storage unit to be written again into the block of the address.

(Note 11)

The nonvolatile memory further includes a data reading unit reading data of a block of a designated address of the memory cell array, and a temporary storage unit reading and temporarily storing data of a block of a designated address of the memory cell array,

The write instruction section reads the data of the block of the address including the data determined that the second threshold value is greater than the voltage value of the floating gate, into the temporary storage unit to read the data of the block of the address. After erasing the data, the recording unit causes the data stored in the temporary storage unit to be written again to a block having an address different from that of the address block.

(Appendix 12)

And a table for managing a logical address of the block and a physical address for the logical address,

The recording instruction unit causes the recording unit to write data stored in the temporary storage unit again to the block of the address, and to update the recorded physical address corresponding to the logical address of the data in the table again. The memory control device according to Appendix 11.

(Appendix 13)

And the write instructing unit instructs the recording unit to write data in a predetermined position of the block when writing data to a block of a specified address of the memory cell array.

(Book 14)

The nonvolatile memory further includes a register in which a temporary elapsed time threshold for determining whether a predetermined date and time has elapsed is set,

The recording instruction unit instructs the recording unit to record the date and time when the determination process is performed at a predetermined position of the nonvolatile memory each time the second sense amplifier performs the determination process,

The memory control according to Appendix 9, wherein the determination processing of the second sense amplifier is performed when the difference between the current date and time and the date and time recorded at the predetermined position exceeds the temporary elapsed time determination threshold value. Device.

(Supplementary Note 15)

And a register in which an access count determination threshold for determining the number of accesses of the memory cell is set.

The recording instruction unit instructs the recording unit to record the number of times of access to the nonvolatile memory at a predetermined position of the nonvolatile memory,

The memory control apparatus according to Appendix 9, wherein the determination processing of the second sense amplifier is performed when the number of accesses exceeds the threshold for determining the number of accesses.

(Appendix 16)

The memory control device according to note 9, further comprising a register for setting a flag indicating that the second sense amplifier is performing processing.

(Note 17)

And the recording instructing unit instructs the recording unit to record the number of times the recording instruction unit instructs the recording in the recording unit at a predetermined position of the nonvolatile memory.

(Note 18)

A memory cell array having a plurality of memory cells having a floating gate, and a first sense amplifier for determining the magnitude of a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell; And a non-volatile memory having a second sense amplifier for determining the magnitude of the voltage value of the floating gate and a second threshold value larger than the first threshold value, and a recording unit for writing the indicated data to the memory cell.

A write instruction unit for instructing, in the recording unit, data writing of the memory cell including the floating gate, wherein the second threshold is greater than the voltage value of the floating gate in the second sense amplifier. Having a memory control device,

A display control unit which displays an operation state of the memory control device on a display device

Memory control system comprising a.

(Note 19)

The memory control device further includes a register for setting a flag indicating that the write instruction unit is instructing recording,

The display control unit reads a flag set in the register, and if the flag is set, displays on the display device that the write instruction unit is instructing recording to maintain the logic of the floating gate. The memory control system described in annex 18.

(Note 20)

The nonvolatile memory includes a portion for storing the number of times that the recording instruction instructs the recording in the recording unit,

When the number of times exceeds a predetermined number of times, the time after the next time from the time of performing this determination processing, rather than the time interval from the time of performing the previous determination processing of the second sense amplifier to the time of performing this determination processing, The memory control system according to Appendix 18, wherein the interval of time for performing the determination process is shortened.

(Book 21)

The nonvolatile memory includes a portion for storing the number of times that the recording instruction instructs the recording in the recording unit,

The memory control system according to Appendix 18, wherein the screen for prompting replacement of the nonvolatile memory is displayed when the number of times exceeds the predetermined number of times.

(Supplementary Note 22)

A memory cell array having a plurality of memory cells having a floating gate, a first sense amplifier, a second sense amplifier, and a recording unit, comprising:

Determining, by the first sense amplifier, a magnitude between a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell;

Determining, by the second sense amplifier, a magnitude between a voltage value of the floating gate and a second threshold value greater than the first threshold value;

Rewriting, by the writing unit, data of the memory cell including the floating gate in which the second sense amplifier determines that the second threshold value is greater than the voltage value of the floating gate;

Control method of a nonvolatile memory, comprising a.

1 is a diagram showing an outline of a nonvolatile memory of an embodiment.

2 is a diagram illustrating a hardware configuration example of a module of the embodiment.

3 is a block diagram showing a configuration of a NAND controller.

4 is a block diagram showing a configuration of a nonvolatile memory.

5 is a block diagram showing the configuration of a sense amplifier circuit.

Fig. 6 is a diagram showing a setting example of a status register.

7 is a diagram illustrating a configuration of a page.

8 is a diagram illustrating a configuration of a page.

9 is a diagram showing a command function to be given to a nonvolatile memory.

10 is a flowchart showing a refresh process determination process.

11 is a flowchart showing a refresh process.

12 is a flowchart showing a refresh process.

Fig. 13 shows the effect of the refresh processing.

Fig. 14 is a flowchart showing processing when displaying on the display that a refresh processing is currently being executed;

Fig. 15 is a flowchart showing processing when displaying on the display a screen prompting exchange of nonvolatile memory.

Fig. 16 is a block diagram showing the structure of the sense amplifier circuit of the second embodiment.

Fig. 17 is a block diagram showing a nonvolatile memory of the third embodiment.

Fig. 18 shows the command function of the nonvolatile memory of the third embodiment.

19 is a flowchart showing a refresh process of a third embodiment;

20 is a flowchart showing a rewrite process;

Fig. 21 is a block diagram showing a nonvolatile memory of the fourth embodiment.

Fig. 22 is a diagram showing a command function of the nonvolatile memory of the fourth embodiment.

Fig. 23 is a flowchart showing the rewrite process of the fourth embodiment.

24 is a flowchart showing an update process of a mapping table.

25 is a block diagram showing a configuration of a NAND controller according to a fifth embodiment.

Fig. 26 is a diagram illustrating a setting example of access count information.

Fig. 27 is a flowchart showing a refresh process need determination process according to the fifth embodiment;

28 is a flowchart showing a refresh interval changing process.

29 is a diagram showing the effect of a refresh interval changing process;

30 is a block diagram showing a configuration of a NAND controller according to a seventh embodiment.

Fig. 31 is a diagram explaining setting of current date and time information of a nonvolatile memory.

32 is a flowchart showing a refresh process need determination process in the seventh embodiment;

33 is a circuit diagram showing a basic cell structure of a NAND type nonvolatile memory.

34 is a diagram showing an aspect of data writing and erasing of a nonvolatile memory.

35 is a diagram illustrating deterioration of a gate oxide film due to the FN tunnel phenomenon.

36 is a graph showing a relationship between an elapsed time and a voltage change of a floating gate.

Fig. 37 is a graph showing the relationship between the number of rewrites and the data holding time;

<Description of the code>

1: non-volatile memory 2: memory cell array

3: first sense amplifier 4: second sense amplifier

5: register 10: module

11: CPU 12: chipset

12a: North Bridge 12b: South Bridge

13: memory 15: display

20: nonvolatile module 21, 21a, 21b: NAND controller

22: NAND type nonvolatile memory (nonvolatile memory)

30: Status register 40, 40a, 40b: command function table

211: host interface unit 212: control register

213: power control unit 214: buffer

215: ECC processing unit 216: NAND interface unit

217: refresh interval register 218: I2C interface unit

221: I / O buffer circuit 222: command register

223: control unit 223a: high voltage generation circuit

223b: rewrite circuit 224: address register

225: NAND Flash Array 226: X Decoder

227: Y decoder 228, 228a: sense amplifier circuit

229: substitution register 2281: main reference cell

2282: sub reference cell 2283: main sense amplifier

2284, 2286: subsense amplifier 2285: logic circuit

Claims (10)

A memory cell array having a plurality of memory cells having a floating gate; A first sense amplifier configured to determine a magnitude of a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell and output a signal indicating whether the memory cell is in a write state or an erase state; The magnitude of the voltage value of the floating gate and the second threshold value larger than the first threshold value and identifying the voltage margin of the floating gate of the memory cell are determined to indicate whether the voltage margin of the floating gate of the memory cell is secured. A second sense amplifier for outputting a signal, A recording unit for rewriting the data of the memory cell including the floating gate, wherein the second sense amplifier has determined that the second threshold value is greater than the voltage value of the floating gate; A data reading unit which reads data of a block of a specified address of the memory cell array; Temporary storage for temporarily storing the read data Including, The data reading unit reads the data, which is determined to be greater than the voltage value of the floating gate, in units of blocks, and stores the data in the temporary storage unit. The recording unit erases the data of the block of the address, and then writes the data stored in the temporary storage unit again to a block of an address different from that of the block of the address, The number of times of recording by the recording unit is stored again, and when the number exceeds a predetermined number of times, an interval of time from the time of performing the previous determination processing of the second sense amplifier to the time of performing this determination processing A nonvolatile memory, characterized in that the interval between the time of performing the next determination processing from the time of performing this determination processing becomes shorter. The nonvolatile memory according to claim 1, wherein the determination of the second sense amplifier is performed after the first sense amplifier determines that the first threshold value is greater than the voltage value of the floating gate. delete The memory cell of claim 1, wherein when data is written to a block of addresses of the memory cell array, the predetermined memory cell of the block is set to a write position to always write data, And the second sense amplifier determines the magnitude of the voltage value of the floating gate of the memory cell at the write position and the second threshold value. A memory cell array having a plurality of memory cells having a floating gate, and a magnitude of a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell are determined so that the memory cell is in a write state. Determine a magnitude of a first sense amplifier for outputting a signal indicating whether the signal is in an erase state or a second threshold value for identifying a voltage margin of the floating gate of the memory cell greater than the voltage value of the floating gate and the first threshold value; A second sense amplifier for outputting a signal indicating whether a voltage margin of the floating gate of the memory cell is secured, a recording unit for writing the indicated data to the memory cell, and data of a block at a specified address of the memory cell array. A data reading section for reading the data, and a temporary storage section for temporarily storing the read data. For the nonvolatile memory, a write instruction unit for instructing, in the second sense amplifier, writing of data of the memory cell including the floating gate, the second threshold being greater than the voltage value of the floating gate, to the recording unit. Including, The write instructing unit instructs the data reading unit to read, in units of blocks, data determined that the second threshold value is greater than the voltage value of the floating gate, and to store in the temporary storage unit, The write instructing unit instructs the recording unit to write data stored in the temporary storage unit into a block having an address different from that of the address block after erasing data of the block of the address; The nonvolatile memory stores a number of times that the recording instruction unit instructs recording in the recording unit, When the number of times exceeds a predetermined number of times, the time after the next time from the time of performing this determination processing, rather than the time interval from the time of performing the previous determination processing of the second sense amplifier to the time of performing this determination processing, The memory control apparatus characterized by shortening the interval of time for performing the determination process. The memory device of claim 5, wherein the nonvolatile memory further includes a register in which a temporary elapsed time threshold for determining whether a predetermined date and time has elapsed is set. The recording instruction unit instructs the recording unit to record the date and time when the determination process is performed at a predetermined position of the nonvolatile memory each time the second sense amplifier performs the determination process, And the determination process of the second sense amplifier is performed when a difference between a current date and time and a date and time recorded at the predetermined position exceeds the temporary elapsed time determination threshold value. The method of claim 5, And a register in which an access count determination threshold for determining the number of accesses of the memory cell is set. The recording instruction unit instructs the recording unit to record the number of times of access to the nonvolatile memory at a predetermined position of the nonvolatile memory, And the determination process of the second sense amplifier is performed when the number of accesses exceeds the access number determination threshold. A memory cell array having a plurality of memory cells having a floating gate, and a magnitude of a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell are determined so that the memory cell is in a write state. Determine a magnitude of a first sense amplifier for outputting a signal indicating whether the signal is in an erase state or a second threshold value for identifying a voltage margin of the floating gate of the memory cell greater than the voltage value of the floating gate and the first threshold value; A second sense amplifier for outputting a signal indicating whether a voltage margin of the floating gate of the memory cell is secured, a recording unit for writing the indicated data to the memory cell, and data of a block at a specified address of the memory cell array. A data reading section for reading the data, and a temporary storage section for temporarily storing the read data. And non-volatile memory, Writing to the recording unit instructing, in the second sense amplifier, writing of data of the memory cell including the floating gate that is determined that the second threshold is greater than the voltage value of the floating gate, with respect to the nonvolatile memory. A memory control device having an indicator, A display control unit which displays an operation state of the memory control device on a display device Including, The write instructing unit instructs the data reading unit to read, in units of blocks, data determined that the second threshold value is greater than the voltage value of the floating gate, and to store in the temporary storage unit, The recording instruction unit instructs the recording unit to write the data stored in the temporary storage unit into a block of an address different from that of the block of the address after erasing data of the block of the address; The nonvolatile memory includes a portion for storing the number of times that the recording instruction instructs the recording in the recording unit, When the number of times exceeds a predetermined number of times, the time after the next time from the time of performing this determination processing, rather than the time interval from the time of performing the previous determination processing of the second sense amplifier to the time of performing this determination processing, A memory control system characterized by shortening the interval of time for performing the determination process. delete A control method of a nonvolatile memory including a memory cell array having a plurality of memory cells having a floating gate, a first sense amplifier, a second sense amplifier, a recording unit, a data reading unit, and a temporary storage unit. The first sense amplifier determines a magnitude of a voltage value of the floating gate and a first threshold value for identifying a write state and an erase state of the memory cell, and outputs a signal indicating whether the memory cell is in a write state or an erase state. Steps, The second sense amplifier determines a magnitude of a voltage value of the floating gate and a second threshold that is greater than the first threshold and identifies a voltage margin of the floating gate of the memory cell, thereby determining a voltage margin of the floating gate of the memory cell. Outputting a signal indicating whether this is secured, Rewriting, by the writing unit, data of the memory cell including the floating gate in which the second sense amplifier determines that the second threshold value is greater than the voltage value of the floating gate; The data reading unit reading data of a block at a designated address of the memory cell array; Temporarily storing the read data of the temporary storage unit Including, The data reading unit reads the data, which is determined to be greater than the voltage value of the floating gate, in units of blocks, and stores the data in the temporary storage unit. The recording unit erases the data of the block of the address, and then again records the data stored in the temporary storage unit in a block of an address different from that of the block of the address, The number of times of recording by the recording unit is stored again, and when the number exceeds a predetermined number of times, an interval of time from the time of performing the previous determination processing of the second sense amplifier to the time of performing this determination processing A control method of a nonvolatile memory, characterized by shortening the interval between the time of performing the next judgment process and the time of performing the next judgment process.

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