JPH07220486A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To prolong the service life of a memory by making a switch to a redundancy word line upon detection that the accumulated number of cycle has reached a limit. CONSTITUTION:An accumulated number of cycle is read out from an auxiliary memory section 13 and delivered to a control section (not shown) in order to decide whether an expected limit has been reached. If the answer is NO, a writing circuit 2 writes a row address into a spare row decoder 5. Consequently, the output of a register in the decoder 5 goes High. Signals are then fed to the other inputs of AND circuits AND1-4 which are inactivated. As a result, word lines W1-Wn are disconnected and a switching is made to a redundant word line connected with a register into which the row address is written. Subsequently, erasure of word line sector, data rewriting, data reading and writing of accumulated number of cycle are effected for the switched redundant word line in place of the word line where the accumulated number of cycle has reached a limit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile memory, for example, a semiconductor nonvolatile memory device such as a flash EEPROM.

[0002]

2. Description of the Related Art Conventionally, for example, by injecting electrons into a floating gate, data "1" /
The flash EEPROM that judges "0" is a normal N
OR type, DINOR (DIvided bit line NOR) type, NAN
Classified as D type. And these NOR type, DIN
In OR type and NAND type flash EEPROMs, a method has been proposed in which sector erase is performed for each word line as a unit of an erase block.

FIG. 4 shows a NOR type flash EEPROM.
FIG. 6 is a circuit diagram showing bias conditions when erasing the word line sector. In FIG. 4, WL _{1 to} WL ₃ are word lines and BL
S _{1 to} BLS ₃ and BLD _{1 to} BLD ₃ are bit lines, MT
_{11 to} MT ₃₃ are memory cell transistors, respectively.

In the NOR type flash EEPROM, when word line sector erase is performed, as shown in FIG. 4, the selected word line WL ₂ is -10 V, the unselected word lines WL ₁ and WL ₃ are 0 V, and the common source line is used. Bit lines BLS _{1 to} BLS ₃ as 6 V, and bit lines BLD ₁ to
BLD ₃ is set to floating state,
The electrons in the floating gate are extracted.

FIG. 5 shows a DINOR type flash EEPR.
It is a circuit diagram showing a bias condition at the time of erasing the word line sector of the OM. In FIG. 5, SL ₁₁ and SL ₂₁ are select gate lines, WL _{11 to} WL ₁₈ and WL _{21 to} WL ₂₈ are word lines, and MB.
L ₁₁ , MBL ₁₂ are main bit lines, SBL ₁₁ , SBL ₁₂ , S
BL ₂₁ , SBL ₂₂ are sub-bit lines, SRL ₁₁ , SRL ₁₂ ,
SRL ₂₁ , SRL ₂₂ are common source lines, ST ₁₁ , ST ₁₂ ,
ST ₂₁ and ST ₂₂ are select gate transistors, MT _{11 1} to
MT ₁₁₈ , MT _{121 to} MT ₁₂₈ , MT _{211 to} MT ₂₁₈ ,
MT _{221 to} MT ₂₂₈ respectively indicate memory cell transistors.

In the DINOR type flash EEPROM, when the word line sector is erased, as shown in FIG. 5, the select gate lines SL ₁₁ and SL ₂₁ are 0V, the select word lines WL _{11 to} WL ₁₈ are 15V, and are not selected. Word line WL ₂₁ ~
WL ₂₈ is 0 V, bit lines MBL ₁₁ , MBL ₁₂ are in a floating state, and common source lines SRL ₁₁ , SRL ₁₂ , SR
L ₂₁ and SRL ₂₂ are set to minus 6V,
Electrons are injected into the floating gate.

FIG. 6 shows a NAND flash EEPRO.
Circuit diagram showing bias conditions when erasing M word line sectors
Is. In FIG. 6, SL₁₁, SL₁₂, SL_{twenty one}, SL
_{twenty two}Is the select gate line, WL₁₁~ WL₁₈, WL_{twenty one}~ WL₂₈Is
Word line, BL₁₁, BL₁₂Is a bit line, ST₁₁₁, ST
₁₁₂, ST₁₂₁, ST₁₂₂, ST₂₁₁, ST₂₁₂, ST
₂₂₁, ST₂₂₂Is a select gate transistor, MT₁₁₁~
MT₁₁₈, MT₁₂₁~ MT₁₂₈, MT₂₁₁~ MT ₂₁₈，
MT₂₂₁~ MT₂₂₈Are memory cell transistors
Is showing.

In the NAND flash EEPROM, when the word line sector is erased, the select gate lines SL _11, SL ₁₂ , SL ₂₁ , SL ₂₂ are set to 0 as shown in FIG.
V, the selected word line WL ₁₁ to WL ₁₈ minus 15V, the unselected word lines WL ₂₁ to WL ₂₈ are 0V, the bit lines BL _11,
BL ₁₂ is set to a floating state and the substrate is set to 6 V, so that electrons in the floating gate are extracted.

A flash EEPROM capable of erasing these word line sectors is extremely advantageous because it can be rewritten and erased in a so-called page mode.

[0010]

However, the flash E which can perform the above-mentioned word line sector erasing.
The EPROM has the following problems. In other words, if a particular word line is intensively rewritten / erased in the entire memory, if the cumulative number of cycles of that word line reaches a certain guaranteed value, other large Even if there is a margin in the cumulative number of cycles of the partial word line sector, the life of the entire memory is determined by the specific word line sector used intensively.

The present invention has been made in view of the above circumstances, and an object thereof is to know that the cumulative number of cycles of a particular word line has reached a limit value, and
It is an object of the present invention to provide a semiconductor nonvolatile memory device capable of extending the life of a memory even when the cumulative number of cycles reaches a limit value.

[0012]

In order to achieve the above object, a semiconductor nonvolatile memory device for word line sector erasing according to the present invention is provided with a recording section for recording the number of rewriting / erasing cycles for each word line. , The cumulative number of cycles of each word line is recorded for each rewriting / erasing cycle.

Further, in the semiconductor nonvolatile memory device of the present invention, the recording section comprises an auxiliary bit line provided for each word line and a nonvolatile memory connected to the auxiliary bit line.

In the semiconductor nonvolatile memory device of the present invention, the cumulative number of cycles of at least one redundant word line in which memory cells are connected in parallel and each word line recorded in the recording section are set in advance. And a circuit for disconnecting the word line and switching to the redundant word line when the value reaches the specified value.

[0015]

According to the present invention, rewriting / rewriting is performed for each word line.
The number of erase cycles is recorded, for example, in the nonvolatile memory connected to the auxiliary bit line of the recording unit for each rewrite / erase cycle. Then, the cumulative number of cycles recorded in this recording unit is read out, and it is determined whether or not the limit number of cycles has been reached for each sector.

Further, according to the present invention, when the cumulative cycle number of each word line recorded in the recording section reaches a preset value, the word line is disconnected and switched to the redundant word line. .

[0017]

Embodiment 1 FIG. 1 is a block diagram showing an embodiment of a semiconductor nonvolatile memory device according to the present invention. In this example, channel hot electron writing / FN (Fowler-Nord)
heim) A NOR type flash EEPROM for erasing by tunneling will be described as an example. In FIG. 1, 1 is a memory array section, 2 is a read / write circuit, 3 is a write circuit, 4 is a normal row decoder, 5 is a spare row decoder, 6 is a column decoder, NOR ₁ is a NOR circuit, and AN.
D _{1 to} AND _N indicate AND circuits, respectively.

The memory array unit 1 includes a normal memory unit 11 in which normal data is written and read, a redundant memory unit 12 for replacing defective memory cells in word line units, and a cumulative number of cycles corresponding to each word line. Of the auxiliary bit memory unit 13 for storing

FIG. 2 is a diagram showing a concrete configuration example of the memory array section. As shown in FIG. 2, the memory array unit 1 is a normal memory array as a normal memory unit 11 composed of M bit lines and N word lines.
It is configured by adding m auxiliary bit lines and n redundant word lines. In FIG. 2, a single circle indicates a memory cell in a normal word line, a double circle indicates an auxiliary bit memory for storing the cumulative number of cycles, a single triangle indicates a memory cell in a redundant word line, and a double triangle. Symbols respectively indicate auxiliary bit memories for storing the cumulative cycle number.

In the example of FIG. 2, since m auxiliary bit lines are provided, it is possible to store the cumulative number of cycles up to (2 ^m -1) times. Therefore, if it is necessary to store the accumulated number of cycles up to 10,000, for example, m = 14 auxiliary bit lines are added.
Also, DINOR type and NAND type flash EEPROM
In M, for example, in the case of using 8 word lines per sector as a unit, the number of auxiliary bit lines is 1/8. Therefore, when storing the cumulative number of cycles up to 10000 times, Two auxiliary bit lines may be provided.

The number of redundant word lines is n in the example of FIG. 2, and it is desirable to optimize this number in consideration of the effect of extending the memory life by replacement and the memory area. Then, in the case of the DINOR type and the MAND type, for example, when the unit is 8 word lines per sector, the redundant word lines are similarly configured in units of 8.

The read / write circuit 2 performs a normal data read operation and a write operation for the memory array section 1 and also makes a unit of each word line sector recorded in the auxiliary bit memory section 13 of the memory array section 1. Write and read the cumulative number of cycles.
This cumulative read cycle number is sent to, for example, a control system (not shown) to determine whether or not a preset limit value has been reached.

The write circuit 3 receives the row address,
When there is a word line sector in which the number of accumulated cycles reaches the limit value, its row address is set to the spare row decoder 5
Write to a predetermined area of.

The normal row decoder 4 receives the row address and outputs it to one input of each AND circuit AND _{1 to} AND _{N in} order to send a signal according to the operation mode to the word line according to the address. AND circuit AND _{1 to} AND
_{The N} outputs are connected to the word lines W _{1 to} W _N of the normal memory section 11 of the memory array section 1, respectively. Also,
The other inputs of the AND circuits AND _{1 to} AND _N are all
It is connected to the output of the NOR circuit NOR ₁ .

The spare row decoder 5 has n registers RG _{1 to} RGn corresponding to the number of redundant word lines of the redundant memory section 12 of the memory array section 1, and each of the registers RG ₁ to RG ₁ to RGn.
The write circuit 3 writes the row address of the word line sector whose cumulative cycle number has reached the limit value to RGn. The outputs of the register registers RG _{1 to} RGn are respectively connected in parallel to the inputs of the NOR circuit NOR ₁ and also to the redundant word lines RW _{1 to} RWn. The output level of each of the register registers RG _{1 to} RGn is normally low (“0”) level, and is high (“1”) level when the row address of the word line sector whose cumulative cycle number has reached the limit value is written. Switch to.

Next, the operation of the above configuration will be described with reference to the flowchart of FIG. First, the cumulative number of cycles is read from the auxiliary bit memory unit 13 of the memory array unit 1 and sent to, for example, a control system (not shown) (S1). In the control system, it is determined whether or not the read cumulative number of cycles is within a preset limit value (S2).

If a positive determination result is obtained in step S2, the write circuit 2 does not perform the write operation on the row address for the spare row decoder 5, so that the registers RG ₁ to RG ₁ to
The outputs of RGn are all at low level. Thus, the output of the NOR circuit NOR ₁ goes high, the input to the other input of the AND circuits AND ₁ ~AND _N, the AND circuits AND ₁ ~AND _N is activated. Therefore, in this case, the predetermined word lines W _{1 to} Wn of the normal memory section 11 of the memory array section 1 are passed through the normal row decoder 4.
Is accessed, and word line sector erase is first performed (S
3) Then, the data in the word line sector is rewritten (S4). Then, after the data in the word line sector is rewritten, writing is performed in the nonvolatile memory connected to the predetermined auxiliary bit line CB of the auxiliary bit memory unit 13 of the memory array unit 1. That is, the cumulative cycle number of the sector is incremented by "+1" (S
5).

On the other hand, when a negative determination result is obtained in step S2, the write circuit 2 writes the row address to a predetermined register of the spare row decoder 5. As a result, the register output in which the row address of the spare row decoder 5 is written becomes high level. As a result, the output of the NOR circuit NOR ₁ switches from the high level to the low level, and each AND circuit A 1
It is input to the other input of ND _{1 to} AND _N. Therefore, the AND circuits AND _{1 to} AND _N are inactivated, and the predetermined word lines W _{1 to} Wn of the normal memory section 11 of the memory array section 1 via the normal row decoder 4 are not accessed. That is, the word line is separated and switched to the redundant word line connected to the register in which the row address is written (S6). After that, instead of the word line for which the cumulative cycle number has reached the limit value, for the redundant word line that has been switched, word line sector erase,
Data rewriting, reading, and writing and reading of the cumulative number of cycles are performed.

As described above, according to this embodiment,
In a flash EEPROM that erases word line sectors, an auxiliary bit line connected to a non-volatile memory is provided in parallel with the bit line of the normal memory section 11 of the memory array section 1, and the non-volatile memory is cumulatively rewritten for each word line.・ Record the number of erase cycles, and determine from the recorded cumulative number of cycles whether or not the cycle number of the sector has reached the limit value, and if so, switch the word line to the redundant word line. By doing so, it is possible to know that the certain cumulative number of cycles has reached the limit value, and thus it is possible to grasp the usage status of the memory array and the like, and it becomes possible to perform the access on average. .
Further, since the redundant portion is provided, the life of the memory can be extended even if the specific cumulative number of cycles reaches the limit value. As a result, there is an advantage that the reliability of the entire memory can be significantly improved.

[0030]

As described above, according to the present invention,
It is possible to know that a certain cumulative number of cycles has reached the limit value. As a result, the usage status of the memory array and the like can be grasped, and a mode in which the access is performed on an average basis becomes possible. Further, since the redundant portion is provided, the life of the memory can be extended even if the specific cumulative number of cycles reaches the limit value. As a result, there is an advantage that the reliability of the entire memory can be significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a nonvolatile memory device according to the present invention.

FIG. 2 is a diagram showing a configuration example of a memory array section of FIG.

3 is a flow chart for explaining the operation of the apparatus of FIG.

FIG. 4 is a circuit diagram showing a bias condition when erasing a word line sector in a NOR flash EEPROM.

FIG. 5 is a circuit diagram showing a bias condition when erasing a word line sector in a DINOR type flash EEPROM.

FIG. 6 is a circuit diagram showing a bias condition when erasing a word line sector in a NAND flash EEPROM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory array part 11 ... Normal memory part 12 ... Redundant memory part 13 ... Auxiliary bit memory part 2 ... Read / write circuit 3 ... Write circuit 4 ... Normal row decoder 5 ... Spare row decoder 6 ... Column decoder NOR ₁ ... NOR circuit AND _1- AND _N ... AND circuit

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[Procedure amendment]

[Submission date] March 25, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

The number of redundant word lines is n in the example of FIG. 2, and it is desirable to optimize this number in consideration of the effect of extending the memory life by replacement and the memory area. Contact name, DINOR type, in the case of N the AND-type, for example in the case of the eight word lines per sector units are similarly constructed to eight units redundant word line.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

Claims (3)

[Claims] 1. A semiconductor non-volatile memory device for erasing word line sectors, comprising a recording section for recording the number of rewrite / erase cycles for each word line, and accumulating each word line for each rewrite / erase cycle. A semiconductor nonvolatile memory device that records the number of cycles. 2. The semiconductor nonvolatile memory device according to claim 1, wherein the recording section includes an auxiliary bit line provided for each word line and a nonvolatile memory connected to the auxiliary bit line. 3. When at least one redundant word line in which memory cells are connected in parallel and the cumulative number of cycles of each word line recorded in the recording section have reached a preset value, that word 3. The semiconductor non-volatile memory device according to claim 1, further comprising a circuit for disconnecting the line and switching to the redundant word line.