CN216647862U

CN216647862U - Solid state disk flash memory array erasing current detection circuit comprising main control chip

Info

Publication number: CN216647862U
Application number: CN202220634951.4U
Authority: CN
Inventors: 谢元禄; 张君宇; 呼红阳; 刘璟; 霍长兴; 张坤; 季兰龙; 习凯
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2022-03-23
Filing date: 2022-03-23
Publication date: 2022-05-31
Anticipated expiration: 2032-03-23

Abstract

The utility model discloses a solid state disk flash memory array erasing current detection circuit comprising a main control chip, and relates to the technical field of solid state disks. The erase current of the Block in the flash memory array is the supply current provided by the SSD power supply module, and after the current detection circuit is connected into the power supply link of the flash memory array, the current detection circuit can detect the supply current of the flash memory array, namely the erase current of the flash memory array, and sends the detected erase current to the main control chip, so that the detection of the erase current of the flash memory array of the solid state disk is realized.

Description

Solid state disk flash memory array erasing current detection circuit comprising main control chip

Technical Field

The utility model relates to the technical field of solid state disks, in particular to a solid state disk flash memory array erasing current detection circuit comprising a main control chip.

Background

An SSD (solid state disk) is composed of a main control chip and a Flash memory medium, and generally employs NAND Flash (NAND Flash memory chip) as a main Flash memory medium. The basic operations of NAND Flash include Read, Program, Erase, where Read and Program are each in units of pages, and Erase is in units of blocks, where a Block generally contains multiple pages. When data in the NAND Flash is updated and rewritten, new data cannot be directly programmed into a Block address space where old data is located, the new data can only be written into other free Block address spaces first, then Erase operation is performed on the Block address space where the old data is located, and the Block can be used for subsequent data programming and writing after Erase is performed on the Block.

When Block is erased, the erasing current needs to be monitored in real time so as to monitor the state of the solid state disk flash memory array.

Disclosure of Invention

The utility model solves the technical problem of how to detect the erasing current of the solid state disk flash memory array by providing the solid state disk flash memory array erasing current detection circuit comprising the main control chip.

The embodiment of the utility model provides the following technical scheme:

a solid state disk flash memory array erasing current detection circuit comprising a main control chip comprises a main control chip and a current detection circuit;

the main control chip is in communication connection with the flash memory array;

the current detection circuit is connected into a power supply link of the flash memory array and is in communication connection with the main control chip.

Preferably, the current detection circuit comprises a sampling resistor and an analog-to-digital converter;

the sampling resistor is connected into a power supply link of the flash memory array in series, the analog-to-digital converter is connected with two ends of the sampling resistor and is in communication connection with the main control chip, and the analog-to-digital converter is used for detecting voltages at two ends of the sampling resistor and converting analog voltage signals into digital signals.

Preferably, the flash memory array is used for storing an erase current of the flash memory array.

Preferably, the solid state disk flash memory array erasing current detection circuit comprising the main control chip further comprises an embedded nonvolatile memory, and the embedded nonvolatile memory is embedded in the main control chip.

Preferably, the embedded nonvolatile memory is an eFlash, a ROM, an OTP or an EEPROM.

Preferably, the solid state disk flash memory array erasing current detection circuit comprising the main control chip further comprises an independent nonvolatile memory, and the independent nonvolatile memory is in communication connection with the main control chip.

Preferably, the independent nonvolatile memory is SPI Flash, parallel port NOR Flash, EEPROM or IIC-based memory.

Preferably, the main control chip is a controller of the solid state disk.

The technical scheme provided by the utility model at least has the following technical effects or advantages:

the erase current of the Block in the flash memory array is the supply current provided by the SSD power supply module, and after the current detection circuit is connected into the power supply link of the flash memory array, the current detection circuit can detect the supply current of the flash memory array, namely the erase current of the flash memory array, and sends the detected erase current to the main control chip, so that the detection of the erase current of the flash memory array of the solid state disk is realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a main control chip, a flash memory array and a current detection circuit according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a main control chip, a flash memory array, a sampling resistor and an analog-to-digital converter according to an embodiment of the present invention;

FIG. 3 is a block diagram of an exemplary solid state drive;

FIG. 4 is a schematic structural diagram of a main control chip and a flash memory array according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a main control chip, a flash memory array and an embedded non-volatile memory according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a main control chip, a flash memory array and a stand-alone non-volatile memory according to an embodiment of the present invention.

Detailed Description

The embodiment of the utility model solves the technical problem of how to detect the erasing current of the solid state disk flash memory array by providing the solid state disk flash memory array erasing current detection circuit comprising the main control chip.

In order to better understand the technical scheme of the utility model, the technical scheme of the utility model is explained in detail in the following with the accompanying drawings and the specific embodiments.

First, it is stated that the term "and/or" appearing herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

As shown in fig. 1, the solid state disk flash memory array erase current detection circuit including a main control chip of the present embodiment includes a main control chip and a current detection circuit; the main control chip is in communication connection with the flash memory array; the current detection circuit is connected to a power supply link of the flash memory array and is in communication connection with the main control chip. Power for the flash array is provided by the SSD power supply module in fig. 1.

In this embodiment, the erase current of the Block in the flash memory array is the supply current provided by the SSD power supply module, and after the current detection circuit is connected to the power supply link of the flash memory array, the current detection circuit can detect the supply current of the flash memory array, that is, the erase current of the flash memory array, and send the detected erase current to the main control chip, so that the erase current of the flash memory array of the solid state disk can be detected, and the state of the flash memory array can be monitored according to the erase current.

Specifically, as shown in fig. 2, the current detection circuit of the present embodiment includes a sampling resistor and an analog-to-digital converter; the sampling resistor is connected in series into a power supply link of the flash memory array, the analog-to-digital converter is connected with two ends of the sampling resistor and is also in communication connection with the main control chip, and the analog-to-digital converter is used for detecting voltages at two ends of the sampling resistor and converting analog voltage signals into digital signals. Each flash memory of the flash memory array may be provided with a sampling resistor and an analog-to-digital converter. The sampling resistor can be a single resistor, or a plurality of resistors can be connected in series or in parallel, the sampling resistor is used for converting the erasing current into voltage, and the analog-to-digital converter detects the voltage at two ends of the sampling resistor, converts an analog voltage signal into a digital signal and sends the digital signal to the main control chip. And the main control chip calculates the erasing current according to the voltages at the two ends of the sampling resistor and the resistance value of the sampling resistor. The calculation process of obtaining the current by dividing the voltage at the two ends of the sampling resistor by the resistance value of the sampling resistor is well known in the art.

The organization structure of a typical SSD is shown in fig. 3, and considering that the SSD itself includes an SSD controller, the main control chip of this embodiment may be an SSD controller of the solid state disk, and no additional main control chip is needed, which can save cost.

The present embodiment provides a variety of storage modes in view of the need to store the erase current.

In the first storage mode, the flash memory array of the solid state disk is used for storing the erasing current of the flash memory array. This way is equivalent to a special memory space is opened in the NAND Flash memory array to store the erase current, and a special erase current control logic is set in the main control chip to perform access control on the erase current storage area, as shown in fig. 4. This storage method is equivalent to incorporating an erase current into the NAND main memory array, which saves hardware overhead, but the NAND main memory array itself has an endrace problem and a bad block problem, which have poor reliability, affect the capacity of the main memory array, and further affect the effect of operations such as garpage Collection.

In a second storage manner, as shown in fig. 5, the erase current detection circuit of the flash memory array of the solid state disk further includes an embedded nonvolatile memory, the embedded nonvolatile memory is embedded in the main control chip, and the embedded nonvolatile memory is used for storing the erase current. The embedded non-volatile memory may be an eFlash, ROM, OTP or EEPROM. This approach does not account for NAND main memory arrays nor require additional memory chips.

In a third storage mode, as shown in fig. 6, the solid state disk flash memory array erase current detection circuit further includes an independent nonvolatile memory, the independent nonvolatile memory is in communication connection with the main control chip, and the independent nonvolatile memory is used for storing erase current. The independent nonvolatile memory can be SPI Flash, parallel port NOR Flash, EEPROM or IIC-based memory. This approach is equivalent to adding an additional memory chip, which increases cost but provides better reliability. An SPI Flash memory is generally arranged in the current SSD product and is used for storing the firmware information of a host CPU, so that the erasing current and the firmware information can be stored in the same SPI Flash by means of the SPI Flash, and the cost can be reduced.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the utility model.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the utility model. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A solid state disk flash memory array erasing current detection circuit comprising a main control chip is characterized by comprising the main control chip and a current detection circuit;

2. The solid state disk flash memory array erase current detection circuit including a master control chip of claim 1, wherein the current detection circuit includes a sampling resistor and an analog to digital converter;

3. The solid state disk flash memory array erase current detection circuit comprising a master control chip of claim 1, wherein the flash memory array is to store an erase current of the flash memory array.

4. The solid state disk flash array erase current detection circuit comprising a master control chip of claim 1, further comprising an embedded non-volatile memory embedded in the master control chip.

5. The solid state disk flash array erase current detection circuit including a master control chip of claim 4, wherein the embedded non-volatile memory is eFlash, ROM, OTP or EEPROM.

6. The solid state disk flash array erase current detection circuit including a master control chip of claim 1, further comprising a stand-alone non-volatile memory communicatively coupled to the master control chip.

7. The solid state disk Flash array erase current detection circuit including a master control chip of claim 6, wherein the stand alone non-volatile memory is SPI Flash, parallel NOR Flash, EEPROM, or IIC based memory.

8. The solid state disk flash array erase current detection circuit comprising a master control chip of claim 1, wherein the master control chip is a controller of the solid state disk.