CN111009274A - Flash memory storage device and operation method thereof - Google Patents
Flash memory storage device and operation method thereof Download PDFInfo
- Publication number
- CN111009274A CN111009274A CN201811169428.3A CN201811169428A CN111009274A CN 111009274 A CN111009274 A CN 111009274A CN 201811169428 A CN201811169428 A CN 201811169428A CN 111009274 A CN111009274 A CN 111009274A
- Authority
- CN
- China
- Prior art keywords
- recording
- record
- row
- erase
- record row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Landscapes
- Read Only Memory (AREA)
Abstract
The invention provides a flash memory storage device, which comprises a memory cell array and a memory control circuit. The memory cell array includes a plurality of well regions. Each well region comprises a plurality of memory blocks and recording blocks. The memory control circuit is coupled to the memory cell array. The memory control circuit is used for erasing the memory blocks of each well area and recording the erasing times of each well area in the respective recording block. In addition, an operation method of the flash memory storage device is also provided.
Description
Technical Field
The present invention relates to a memory storage device and an operating method thereof, and more particularly, to a flash memory storage device and an operating method thereof.
Background
For flash memory storage devices, cycling tends to create interface states at their drain junctions and oxide traps at their tunnel oxide layers. Generally, the loop operation includes an erase operation and a program operation. Flash memory cells are often susceptible to degradation over multiple cycles, such as reduced reliability of the memory blocks, or increased erase and program times, i.e., slower operating speeds. In addition, after many cycles, some bits in the cell may be out of specification due to premature wear. These worn bits are difficult to cull out during the test phase. Therefore, it would be beneficial to obtain erase counts for each well region of a memory cell array including a plurality of memory blocks to evaluate the performance of a flash memory storage device during subsequent applications or manufacturing processes.
Disclosure of Invention
The invention provides a flash memory storage device and an operation method thereof, which can record the erasing times of a well region.
The flash memory storage device comprises a memory cell array and a memory control circuit. The memory cell array includes a plurality of well regions. Each well region comprises a plurality of memory blocks and recording blocks. The memory control circuit is coupled to the memory cell array. The memory control circuit is used for erasing the memory blocks of each well area and recording the erasing times of each well area in the respective recording block.
The operation method of the flash memory storage device comprises the following steps: performing an erase operation on a plurality of memory blocks in the memory cell array; judging whether the erasing times recorded by at least one recording row reaches an upper limit value; if the erasing times recorded by at least one recording row reaches the upper limit value, erasing operation is carried out on at least one recording row while erasing operation is carried out on the memory block in the memory cell array; and recording the data of the erasing times in at least one recording row if the erasing times recorded in at least one recording row does not reach the upper limit value. The memory block and the recording block are located in the same well region.
Based on the above, in the exemplary embodiment of the invention, the flash memory storage device can automatically record the number of times each well region is erased. The recorded data can be used for subsequent evaluation of the performance of the flash memory storage device.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a flash memory storage device according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a well region in the memory cell array of the embodiment of fig. 1.
Fig. 3 is a schematic diagram of a recording block in the embodiment of fig. 1.
FIG. 4 is a flowchart illustrating a method of operating a flash memory storage device according to an embodiment of the invention.
FIG. 5 is a flowchart illustrating a method of operating a flash memory storage device according to another embodiment of the present invention.
Fig. 6 illustrates a detailed flowchart of step S200 of fig. 5.
[ notation ] to show
100: flash memory storage device
110: memory cell array
111_1, 111_2, 111_3, 111_ (N-1), 111_ N: memory block
112: well area
113: recording block
120: memory control circuit
310_1, 310_2, 310_3, 310_ M: record column
312. 312_1, 312_2, 312_3, 312_4, 312_ 5: byte(s)
LSB: least significant bit
MSB: most significant bit
S100, S110, S120, S130, S200, S210, S220, S230, S240, S250, S300, S310, S320, S330, S340, S350, S360: step (ii) of
Detailed Description
Fig. 1 is a schematic diagram of a flash memory storage device according to an embodiment of the invention. Fig. 2 is a schematic diagram of a well region in the memory cell array of the embodiment of fig. 1. Referring to fig. 1 and 2, a flash memory storage device 100 of the present embodiment includes a memory cell array 110 and a memory control circuit 120. The memory control circuit 120 is coupled to the memory cell array 110. In the present embodiment, the Flash memory storage device 100 is, for example, a coded Flash memory (NOR Flash).
In the present embodiment, the memory cell array 110 includes a plurality of well regions 112 as shown in FIG. 2. Fig. 2 shows only one well region 112 in the memory cell array 110, but the number is not intended to limit the present invention. Well region 112 is, for example, a P-well (P well). The well region 112 includes a plurality of memory blocks 111_1 to 111_ N and a recording block 113, where N is a positive integer greater than 0. The memory blocks 111_1 to 111_ N are used for storing data. The recording block 113 is used to store the erase count of the well region 112.
In the present embodiment, the memory control circuit 120 is used for performing an erase operation on the memory blocks 111_1 to 111_ N of the well region 112, and recording the number of times of erasing the well region 112 in the recording block 113. For example, the memory control circuit 120 performs an erase operation on the target memory block 111_2 during an erase period. At this time, a positive high voltage (positive high voltage) is applied to the well region 112, a negative high voltage (negative high voltage) is applied to the memory cell array gate in the target memory block 111_2, and a positive voltage (positive voltage) is applied to the memory cell array gates in the remaining memory blocks 111_1, 111_3, 111_ (N-1), 111_ N. In the present embodiment, the memory block 111_2 is erased, and the number of times of erasing the well region 112 is increased once. Then, the memory control circuit 120 records the erase count in the recording block 113. When any one of the memory blocks 111_1 to 111_ N is erased, the number of times of erasing the well region 112 is increased once.
In the embodiment of multiple well regions, the memory control circuit 120 performs an erase operation on the memory blocks of each well region respectively, and records the erase times of each well region in the respective recording blocks.
In the present embodiment, the memory control circuit 120 can be implemented by any suitable circuit structure in the technical field, and the present invention is not limited thereto, and the circuit structure and the operation method thereof can be adequately suggested, suggested and described by the common general knowledge in the technical field.
Fig. 3 is a schematic diagram of a recording block in the embodiment of fig. 1. Referring to fig. 3, the recording block 113 of the present embodiment includes a plurality of recording rows 310_1 to 310_ M, where M is a positive integer greater than 0. The record columns 310_1 to 310_ M include a plurality of bytes 312. The number of bytes per recording column may be the same or different. The record rows 310_1 to 310_ M are used for storing the data of the erase times. For example, each recording row is, for example, a word line, which is coupled to a plurality of memory cells (not shown), wherein a portion of the memory cells are used for storing erase data. For example, in one embodiment, a plurality of memory cells corresponding to two bytes of data stored in each record row are used to store the erase count data. In one embodiment, a plurality of memory cells corresponding to four bytes of data stored in each record row are used for storing the erase count data.
In the present embodiment, the memory control circuit 120 records the data of the erase count to the last record row 310_ M in sequence from the first record row 310_ 1. Taking the first recording row 310_1 comprising two bytes as an example, the memory control circuit 120 records the data of the erasure number to the most significant bit MSB sequentially from the least significant bit LSB of the byte 312_ 1. For example, after the memory control circuit 120 performs an erase operation on any one of the memory blocks 111_1 to 111_ N of the well region 112, the least significant bit LSB of the byte 312_1 is programmed from the state "1" to the state "0" to indicate that the number of times of erasing of the well region 112 is increased once and recorded in the byte 312_ 1. In this manner, the memory control circuit 120 sequentially records the data of the erase times to the most significant bit MSB of the byte 312_ 1.
Then, the memory control circuit 120 sequentially records the data of the erase times to the most significant bit MSB of the byte 312_2 from the least significant bit LSB of the byte 312_ 2. Therefore, when all bits of the two bytes 312_1 and 312_2 in the record row 310_1 are programmed from the state "1" to the state "0", it represents that the erase count of the well region 112 is 16 times. The 16 times is the upper limit of the erase count recorded in the recording row 310_ 1. When the erase count recorded in the record row 310_1 (the first record row) has reached the upper limit of the record row 310_1, the memory control circuit 120 records the erase count recorded in the record row 310_1 by using the next record row 310_2 (the second record row).
For example, when the erase count recorded in the record row 310_1 has reached the upper limit value of 16 times, the memory control circuit 120 performs an erase operation on the record row 310_1 at the same time as performing an erase operation on any memory block during the erase period, so as to erase all bits of the two bytes 312_1 and 312_2 from the state "0" to the state "1" for recording the erase count again. At this time, when the record row 310_1 is erased once, the memory control circuit 120 programs the least significant bit LSB of the byte 312_3 of the record row 310_2 from the state "1" to the state "0" to indicate that the erase count of the record row 310_1 is 1, and also to indicate that the erase count of the well region 112 has been accumulated 17 times, and is recorded in the byte 312_ 3. In this manner, the memory control circuit 120 sequentially records the data of the erase times to the most significant bit MSB of the byte 312_ 3.
In the embodiment, after the erase operation is performed on the record row 310_1, the memory control circuit 120 records the data of the erase count in the bytes 312_1 and 312_2 of the record row 310_1 again, and the upper limit of the record count of the record block 113 is increased by reusing the record bytes of the record row 310_ 1.
Then, the memory control circuit 120 sequentially records the data of the erase times to the most significant bit MSB of the byte 312_4, starting from the least significant bit LSB of the byte 312_ 4. Therefore, when all bits of the two bytes 312_3 and 312_4 in the record row 310_2 are programmed from the state "1" to the state "0", the erase count of the well region 112 is 256. The 256 times is the upper limit of the erase count recorded in the recording row 310_ 2. If the erase counts recorded in the record row 310_1 and the record row 310_2 have reached the upper limit, the memory control circuit 120 performs an erase operation on the record row 310_1 and the record row 310_2 simultaneously to re-record the erase counts. At this time, when the record row 310_1 and the record row 310_2 are erased, the memory control circuit 120 programs the least significant bit LSB of the byte 312_5 of the record row 310_3 from the state "1" to the state "0" to indicate that the erase count of the well area 112 has been accumulated 257 times and is recorded in the byte 312_ 5. In this manner, the memory control circuit 120 sequentially records the data of the erase times to the most significant bit MSB of the byte 312_ 5.
In the embodiment, after the erasure operation is performed on the record row 310_1 and the record row 310_2, the memory control circuit 120 records the data of the erasure number in the bytes 312_1 and 312_2 of the record row 310_1 and the bytes 312_3 and 312_4 of the record row 310_2 again, and increases the upper limit of the recording number of the recording block 113 by reusing the recording bytes of the record row 310_1 and the record row 310_ 2.
Similarly, if 100-thousand erase counts (100k) are recorded as the target, the recording block 113 includes 4 recording rows, the first to third recording rows store the erase count data with a plurality of memory cells corresponding to two bytes of data, and the fourth recording row stores the erase count data with a plurality of memory cells corresponding to three bytes of data. When the erase counts recorded in the last record row (e.g. 310_ M) all reach the upper limit of the record row, which is the upper limit of the erase counts recorded in the record block, the memory control circuit 120 does not erase the last record row any more.
In another embodiment, the recording block 113 includes 4 recording rows, for example, the first to third recording rows store erase data with a plurality of memory cells corresponding to a data amount of four bytes, and the fourth recording row stores erase data with a plurality of memory cells corresponding to a data amount of one byte. Therefore, in this example, the recording block 113 can record about 256 thousand erase times (256 k).
In the present embodiment, each recording row is, for example, a word line, which is coupled to a plurality of memory cells (not shown), wherein a portion of the memory cells are used for storing data of erase times. The word lines (i.e., the recording rows) coupled to the recording block 113 are word lines additionally disposed in the well region 112 for recording erase counts, compared to the word lines coupled to the memory blocks 111_1 to 111_ N. When the memory control circuit 120 programs a valid bit in the byte of the record row 310_1(LSB record row) from the state "1" to the state "0", the erase count of the recording area 112 is increased once. When the erase count recorded in the record row 310_1 reaches the upper limit value and is erased once, the memory control circuit 120 programs a valid bit in the byte of the next record row 310_2 from "1" to "0" to indicate that the erase count of the record row 310_1 is increased by 1 time. When the erase counts recorded in the bytes of the record rows 310_1 to 310_2 all reach the upper limit value and are erased simultaneously, the memory control circuit 120 programs a valid bit in the byte of the next record row 310_3 from the state "1" to the state "0" to indicate that the erase count of the record row 310_2 is increased by 1 time. The erase count of the well region 112 can be obtained by counting the data of the inequality values in the bytes of each record row.
FIG. 4 is a flowchart illustrating a method of operating a flash memory storage device according to an embodiment of the invention. The operation method of the present embodiment is applicable to a coded Flash memory (NOR Flash) storage device, for example. Referring to fig. 1 to 4, in step S100, the memory control circuit 120 performs an erase operation on the memory blocks 111_1 to 111_ N located in the same well region 112 in the memory cell array 110. In step S110, the memory control circuit 120 determines whether the erase count recorded in the recording row 310_1 in the recording block 113 reaches an upper limit. If so, the memory control circuit 120 executes step S120 to erase the recording row 310_1 while erasing the memory blocks 111_1 to 111_ N, and record the data of the number of times of erasing in the recording row 310_ 2. If not, the memory control circuit 120 executes step S130 to record the data of the erase count in the record row 310_ 1.
In addition, the operation method of the flash memory storage device according to the embodiment of the invention can be adequately taught, suggested and implemented in the descriptions of the embodiments of fig. 1 to 3.
FIG. 5 is a flowchart illustrating a method of operating a flash memory storage device according to another embodiment of the present invention. The operation method of the present embodiment is applicable to a coded Flash memory (NOR Flash) storage device, for example. Referring to fig. 5, in the present embodiment, the memory control circuit 120 performs an erase operation on the memory blocks 111_1 to 111_ N located in the same well region 112 in the memory cell array 110. The erase operation includes performing a pre-program (pre-program) operation (step S210), an erase operation (step S220), and a post-program (post-program) operation (step S230) on the target memory block 111_2 to perform a soft-program (soft-program) operation on over-erased memory cells in the target memory block and a refresh (refresh) operation (step S240) on the memory blocks 111_1 and 111_3 to 111_ N outside the target memory block to perform programming on programmed memory cells in the non-target memory blocks. In the present embodiment, performing the pre-program operation, the erase operation, the post-program operation on the target memory block 111_2 and performing the refresh operation on the memory blocks 111_1 and 111_3 to 111_ N other than the target memory block are well suggested, suggested and described in the prior art.
In this embodiment, before step S210 is executed, in step S200, the memory control circuit 120 scans the bytes 312_1 and 312_2 in the record column 310_1 to determine which bits are "1". If at least one bit in the bytes 312_1 and 312_2 is in the state of "1", the memory control circuit 120 records the data of the erase count in the bit in the state of "1" in step S250. If the states of all bits in the bytes 312_1 and 312_2 are "0", the memory control circuit 120 records the data of the erase count in the record row 310_2, i.e. the programmed record row 310_2, in step S250. In step S220, the memory control circuit 120 performs an erase operation on the target memory block 111_2 and the recording row 310_1 at the same time.
In step S200, after scanning, if the memory control circuit 120 determines that the status of all bits of the bytes in the record rows 310_1 and 320_2 is "0", the memory control circuit 120 can record the data of the erase count in the next record row of the record row 310_2 in step S250. In step S220, the memory control circuit 120 performs an erase operation on the target memory block 111_2 and the record rows 310_1 and 310_2 at the same time. The erase operation of the memory control circuit 120 for the remaining recording rows can be repeated.
In the present embodiment, the memory control circuit 120 performs the post-programming operation and the refresh operation on the recording block 113 at the same time as performing the post-programming operation and the refresh operation on the memory blocks 111_1 to 111_ N in steps S230 and S240. In addition, the operation method of the flash memory storage device according to the embodiment of the invention can be adequately taught, suggested and implemented in the descriptions of the embodiments of fig. 1 to 4.
Fig. 6 illustrates a detailed flowchart of step S200 of fig. 5. Referring to fig. 3 and 6, in step S300, the memory control circuit 120 sets the read mode in the recording block 113 and sets the read from the recording row 310_ 1. In step S310, the memory control circuit 120 reads the data of the byte 312_1 starting from the least significant bit LSB of the byte 312_ 1. In step S320, the memory control circuit 120 determines whether the states of the read data are all "0".
If the data states are not all "0", for example, at least one data state is "1", the memory control circuit 120 executes step S330, loads the address of the byte 312_1 and the data thereof into the register and programs the register in step S250, for example, performs one-bit programming (one-bit program) on the bit of the byte 312_1 whose data state is not "0" to record the erase count. After step S330, the memory control circuit 120 returns to the flow of fig. 5 to execute step S210.
If the data states are all "0", the memory control circuit 120 executes step S340 to determine whether the read byte is the last byte in the record column 310_ 1. If the read byte is not the last byte in the record column 310_1, the memory control circuit 120 returns to step S310 to read the next byte, i.e., byte 312_ 2. If the read byte is the last byte in the record row 310_1, the memory control circuit 120 executes step S350 to determine whether the read record row is the last record row 310_ M in the record block 113.
If the read record row is not the last record row 310_ M in the record block 113, the memory control circuit 120 returns to step S310 to read the first byte of the next record row, for example, the byte 312_3 of the record row 310_ 2. If the data states are not all "0", the memory control circuit 120 executes step S330 to load the address of the byte 312_3, the data thereof and the address of the recording row reaching the recording upper limit value into the register, erase the recording row 310_1 while performing the erase operation on the target memory block in steps S210 to S240, and perform the one-bit programming on the bit of the byte 312_3 whose data state is not "0" in step S250 to record the erase count. If the read record row is the last record row 310_ M in the record block 113, the memory control circuit 120 executes step S360 to end the setting of the read byte data. After step S360, the memory control circuit 120 returns to the flow of fig. 5 to execute step S210.
In summary, in the exemplary embodiments of the invention, the flash memory storage device can automatically record the number of times each well region is erased in each recording block. The recording rows in the recording block are additionally provided with word lines in the well region for recording the erase times, and the coupled partial or all memory cells can be used for storing the data of the erase times. The recorded data can be used for subsequent evaluation of the performance of the flash memory storage device.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (15)
1. A flash memory storage device, comprising:
a memory cell array including a plurality of well regions, each of the well regions including a plurality of memory blocks and a recording block; and
the memory control circuit is coupled to the memory cell array and used for carrying out erasing operation on the plurality of memory blocks of each well region and recording the erasing times of each well region in the respective recording blocks.
2. The flash memory storage device of claim 1, wherein the recording block comprises a plurality of recording rows for storing the erase count data, and each of the recording rows comprises a plurality of bytes.
3. The flash memory storage device of claim 2, wherein the memory control circuit sequentially records the erase count data to a last recording row of the recording blocks starting from a first recording row of the recording blocks.
4. The flash memory storage device of claim 3, wherein the memory control circuit sequentially records the erase count data to the most significant bit of each of the bytes, starting from the least significant bit of each of the bytes.
5. The flash memory storage device of claim 2, wherein the erase count recorded by each record row has an upper limit, the plurality of record rows includes a first record row and a second record row, and when the erase count recorded by the first record row has reached the upper limit of the first record row, the memory control circuit records the erase count recorded by the first record row by using the second record row until the erase count recorded by the second record row reaches the upper limit of the second record row.
6. The flash memory storage device of claim 5, wherein the memory control circuit performs the erase operation on the first record row during an erase when the erase count recorded by the first record row has reached an upper limit value of the first record row.
7. The flash memory storage device of claim 6, wherein the memory control circuitry performs the erase operation on the first record column together during the erase while performing the erase operation on the plurality of memory blocks.
8. The flash memory storage device of claim 5, wherein the second record row is a next record row of the first record row in the record block.
9. The flash memory storage device of claim 6, wherein the memory control circuit stores the erased data in the erased first record row again after the first record row is subjected to the erase operation.
10. An operation method of a flash memory storage device, wherein the flash memory storage device includes a memory cell array including a recording block including at least one recording row, the operation method comprising:
performing an erase operation on a plurality of memory blocks in the memory cell array, wherein the plurality of memory blocks and the recording block are located in a same well region;
judging whether the erasing times recorded by the at least one recording row reaches an upper limit value or not;
if the erase count recorded by the at least one record row has reached the upper limit, performing the erase operation on the at least one record row while performing the erase operation on the plurality of memory blocks in the memory cell array; and
if the erasing times recorded in the at least one recording row do not reach the upper limit value, recording the data of the erasing times in the at least one recording row.
11. The operating method according to claim 10, wherein the at least one record column includes a plurality of record columns, and the step of recording the erasure count data in the at least one record column includes:
and sequentially recording the data of the erasing times to the last recording row of the recording block from the first recording row of the recording block.
12. The method of claim 11, wherein each of the record rows includes a plurality of bytes for storing the erasure data, and the step of recording the erasure data in the at least one record row further comprises:
and sequentially recording the data of the erasure times to the most significant bit in each byte from the least significant bit in each byte.
13. The operating method according to claim 10, wherein the at least one record row includes a first record row and a second record row, and in the step of performing the erase operation on the at least one record row in which the erase count has reached the upper limit value, when the erase count recorded in the first record row has reached the upper limit value of the first record row, the erase operation is performed on the first record row while performing the erase operation on the plurality of memory blocks in the memory cell array.
14. The operating method according to claim 13, wherein the second recording column is a next recording column of the first recording column in the recording block.
15. The operating method according to claim 13, wherein in the step of recording the erase count data in the at least one record row, the erase count data is stored again in the erased first record row after the erase operation is performed on the first record row.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811169428.3A CN111009274B (en) | 2018-10-08 | 2018-10-08 | Flash memory storage device and operation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811169428.3A CN111009274B (en) | 2018-10-08 | 2018-10-08 | Flash memory storage device and operation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111009274A true CN111009274A (en) | 2020-04-14 |
| CN111009274B CN111009274B (en) | 2022-11-08 |
Family
ID=70110657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811169428.3A Active CN111009274B (en) | 2018-10-08 | 2018-10-08 | Flash memory storage device and operation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111009274B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113488098A (en) * | 2021-07-20 | 2021-10-08 | 南京冷火电子科技有限公司 | Counting algorithm based on FALSH memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120170365A1 (en) * | 2011-01-04 | 2012-07-05 | Samsung Electronics Co., Ltd. | Non-volatile memory devices and systems including the same, and methods of programming non-volatile memory devices |
| US20140269069A1 (en) * | 2013-03-13 | 2014-09-18 | Sandisk Technologies Inc. | Tracking cell erase counts of non-volatile memory |
| CN106844583A (en) * | 2017-01-10 | 2017-06-13 | 厦门雅迅网络股份有限公司 | A kind of optimization method that FAT file system is set up on NOR Flash |
| CN107193493A (en) * | 2017-05-19 | 2017-09-22 | 惠州佰维存储科技有限公司 | The management method and its system of Nand flash blocks |
| CN107293324A (en) * | 2016-04-13 | 2017-10-24 | 华邦电子股份有限公司 | Storage arrangement and memory block application method |
-
2018
- 2018-10-08 CN CN201811169428.3A patent/CN111009274B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120170365A1 (en) * | 2011-01-04 | 2012-07-05 | Samsung Electronics Co., Ltd. | Non-volatile memory devices and systems including the same, and methods of programming non-volatile memory devices |
| US20140269069A1 (en) * | 2013-03-13 | 2014-09-18 | Sandisk Technologies Inc. | Tracking cell erase counts of non-volatile memory |
| CN107293324A (en) * | 2016-04-13 | 2017-10-24 | 华邦电子股份有限公司 | Storage arrangement and memory block application method |
| CN106844583A (en) * | 2017-01-10 | 2017-06-13 | 厦门雅迅网络股份有限公司 | A kind of optimization method that FAT file system is set up on NOR Flash |
| CN107193493A (en) * | 2017-05-19 | 2017-09-22 | 惠州佰维存储科技有限公司 | The management method and its system of Nand flash blocks |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113488098A (en) * | 2021-07-20 | 2021-10-08 | 南京冷火电子科技有限公司 | Counting algorithm based on FALSH memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111009274B (en) | 2022-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101463967B1 (en) | Non-volatile semiconductor memory, erasing method and programming method | |
| US8830752B2 (en) | Dynamically configurable MLC state assignment | |
| US6353553B1 (en) | Nonvolatile semiconductor memory device having structure storing multivalued data and data storage system comprising the nonvolatile semiconductor memory device | |
| KR100926195B1 (en) | Non-volatile semiconductor memory device | |
| US6965526B2 (en) | Sectored flash memory comprising means for controlling and for refreshing memory cells | |
| US7599236B2 (en) | In-circuit Vt distribution bit counter for non-volatile memory devices | |
| JP4280739B2 (en) | How to access memory | |
| US20190221268A1 (en) | Semiconductor memory device for improving high temperature data retention | |
| US6778443B2 (en) | Non-volatile semiconductor memory device having memory blocks pre-programmed before erased | |
| KR20070024707A (en) | Erase algorithm for multi-level bit flash memory | |
| US7236405B2 (en) | Method for setting erasing pulses and screening erasing defects of nonvolatile memory | |
| US20100034021A1 (en) | Method of controlling operation of flash memory device | |
| US9818476B1 (en) | Reprogram without erase using capacity in multi-level NAND cells | |
| US7181566B2 (en) | Scratch control memory array in a flash memory device | |
| KR100282679B1 (en) | Semiconductor Memory and Information Storage Device | |
| US20030072204A1 (en) | Semiconductor device | |
| CN111009274B (en) | Flash memory storage device and operation method thereof | |
| US6515905B2 (en) | Nonvolatile semiconductor memory device having testing capabilities | |
| JP4658812B2 (en) | Nonvolatile semiconductor memory device and writing method thereof | |
| US10908824B2 (en) | Flash memory storage device and method thereof | |
| CN115470052A (en) | Bad block detection method and device for memory chip and storage medium | |
| KR101227368B1 (en) | Method for data programming of a NAND flash memory device and method for data reading of the same | |
| TWI678699B (en) | Flash memory storage device and method thereof | |
| JP2008293616A (en) | Erasing method for nonvolatile semiconductor memory | |
| JPH07122088A (en) | Nonvolatile semiconductor memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |