CN115470052A - Bad block detection method and device for memory chip and storage medium - Google Patents
Bad block detection method and device for memory chip and storage medium Download PDFInfo
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Abstract
The application discloses a bad block detection method, a detection device and a storage medium of a storage chip, wherein the bad block detection method comprises the following steps: performing erasing operation, writing operation and reading operation on at least one storage block of a storage chip, and determining whether any storage block in the at least one storage block is a bad block, wherein the number of the storage blocks in the at least one storage block is less than the total number of the storage blocks in the storage chip; in response to a memory block being a bad block, the bad block is marked. Through the mode, the bad blocks in the memory chip can be detected in a read-while-write mode, and the error number can be rapidly stabilized through the read-while-write mode, so that the detection time is shortened.
Description
Technical Field
The present invention relates to the field of bad block detection technologies, and in particular, to a bad block detection method, a bad block detection apparatus, and a storage medium for a memory chip.
Background
Due to the limitation of the manufacturing process, a memory chip may have a bad block when it leaves the factory, and the damage of the data block may cause data loss and abnormal suspension when accessing data, which may adversely affect the system. At this time, it is necessary to detect a bad block of the memory chip and mark the detected bad block. However, the bad block detection technology on the market needs to perform the erasing/writing/reading operation of the whole disk for a long time.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a bad block detection method, a detection device and a storage medium of a storage chip, which can detect bad blocks in the storage chip in a writing and reading mode and save detection time.
In order to solve the technical problem, the present application adopts a technical solution that: a bad block detection method of a memory chip is provided, which comprises the following steps: the method comprises the steps of performing erasing operation, writing operation and reading operation on at least one storage block of a storage chip, determining whether any storage block in the at least one storage block is a bad block, and responding to the condition that one storage block is the bad block, and marking the bad block.
The number of the storage blocks in the at least one storage block is smaller than the total number of the storage blocks in the storage chip.
Wherein, to at least one memory block execution erasing operation, write operation and read operation of memory chip, include: selecting at least part of memory blocks from memory blocks which are not subjected to erasing operation in the memory chip to execute erasing operation each time; and selecting at least part of the memory blocks from the memory blocks which are subjected to the erasing operation each time to perform writing operation, and selecting at least part of the memory blocks from the memory blocks which are subjected to the writing operation to perform reading operation until all the memory blocks in the memory chip are subjected to the erasing operation, the writing operation and the reading operation.
Wherein, the number of the memory blocks for executing the erasing operation at different times is the same or different.
Wherein, at least part of the memory blocks are selected from the memory blocks which have performed the erasing operation each time to perform the writing operation, and at least part of the memory blocks are selected from the memory blocks which have performed the writing operation to perform the reading operation, comprising: and all the storage blocks which have executed the erasing operation each time execute the writing operation, and all the storage blocks which have executed the writing operation execute the reading operation.
And a preset time is separated between the execution of the write operation and the execution of the read operation on the same storage block.
Wherein, the erasing operation, the writing operation and the reading operation are executed to at least one memory block of the memory chip, and the erasing operation, the writing operation and the reading operation comprise: selecting at least part of memory blocks from memory blocks which do not execute the erasing operation in the memory chip to execute the erasing operation each time, and selecting at least part of memory blocks from memory blocks which execute the erasing operation each time to execute the writing operation; and selecting a storage block in which at least part of the write operation is finished from the partial storage blocks in which the erase operation is finished at least twice to execute the read operation until all the storage blocks in the storage chip execute the erase operation, the write operation and the read operation.
Wherein, the erasing operation, the writing operation and the reading operation are executed to at least one memory block of the memory chip, and the erasing operation, the writing operation and the reading operation comprise: performing erasing operation on all storage blocks in the storage chip; and selecting at least part of the storage blocks from which the erasing operation is executed to perform writing operation each time, and selecting at least part of the storage blocks from which the writing operation is executed to perform reading operation until all the storage blocks in the storage chip perform the erasing operation, the writing operation and the reading operation.
The number of the memory blocks for performing the write operation or the read operation at different times is the same or different.
Wherein determining whether any of the at least one memory block is a bad block comprises: determining the number of the storage units with errors in the storage block based on the write data and the read data of the storage units in any storage block: and determining the storage block as the bad block in response to the number of the storage units with errors in the storage block being larger than the error number threshold.
The memory blocks in the memory chip are programmed in a TCL, QLC, SLC or MLC mode to perform erasing operation, writing operation and reading operation.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided a detection apparatus comprising a memory storing program data and a processor for executing the program data to implement the bad block detection method of the memory chip as described above.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided a computer-readable storage medium storing program data for implementing the bad block detection method of a memory chip as described above when the program data is executed by a processor.
The beneficial effect of this application is: different from the prior art, the method and the device have the advantages that the erasing operation, the writing operation and the reading operation are performed on at least one storage block of the storage chip, whether any storage block in the at least one storage block is a bad block is determined, the bad block is marked in response to the fact that one storage block is the bad block, and due to the fact that the number of the storage blocks in the at least one storage block which are erased and written is smaller than the total number of the storage blocks in the storage chip, the storage chip can be detected by the operation of reading and writing while reading, the reading and the writing are not performed after all erasing and writing are completed, the error number can be rapidly stabilized by the reading and the writing while reading, the detection time can be shortened, and the detection efficiency is improved.
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In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of a memory chip provided in the present application;
FIG. 2 is a flowchart illustrating a bad block detection method according to a first embodiment of the present disclosure;
FIG. 3 is a flowchart illustrating a bad block detection method according to a second embodiment of the present application;
FIG. 4 is a flowchart illustrating a bad block detection method according to a third embodiment of the present application;
FIG. 5 is a flowchart illustrating a fourth embodiment of a bad block detection method provided in the present application;
FIG. 6 is a flowchart illustrating a fifth embodiment of a bad block detection method according to the present application;
FIG. 7 is a schematic structural diagram of an embodiment of a detection apparatus provided in the present application;
FIG. 8 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory chip provided in the present application, where the memory chip 10 includes a memory block 101, a memory block 102 … and a memory block 10M, where M represents the total number of memory blocks into which the memory chip 10 is divided, and each memory block is in communication connection with another memory block.
A plurality of wafers are stacked and packaged in a chip, each wafer is called a Logical Unit (LUN), the plurality of Logical units share a set of input and output interfaces, but each Logical Unit can independently perform erasing, writing and reading operations.
The erase operation refers to erasing data of a specified length in the memory cell.
The write operation means that data is firstly written into a data buffer area in a message processing unit by a GTX bus, after a certain data volume is reached, an MC (main controller) sends a write command to an NAC (Flash memory control unit) of a specified logic channel, the data is then transmitted to a page buffer area in the NAC by a DMA (data Interface), finally, the NAC processor controls a memory Interface unit to write the data into the buffer area in a memory chip from the page buffer area through an ONFI (Open NAND Flash Interface generating Group) bus, and the chip executes programming operation to write the data into each memory unit.
The read operation means that after a logic unit of the chip receives a read command, internal reading is performed first, data is read from an internal storage unit to a cache buffer, then the data is transmitted from the inside of the chip to a page buffer of an NFI (NAND Flash Interface Working Group) through an ONFI bus, and finally the data is sent to a memory of the expansion board through a GTX bus by a DMA engine.
Referring to fig. 2, fig. 2 is a schematic flowchart of a bad block detection method according to a first embodiment of the present application, and the bad block detection method includes the following specific steps:
step 21: the method comprises the steps of performing erasing operation, writing operation and reading operation on at least one storage block of a storage chip, and determining whether any storage block in the at least one storage block is a bad block, wherein the number of the storage blocks in the at least one storage block is smaller than the total number of the storage blocks in the storage chip.
In the embodiments of the present application, the memory Block is also called Block.
Specifically, a certain memory chip includes a plurality of blocks, and erase operation, write operation, and read operation are implemented for each Block, and the specific implementation of erase/read/write operation includes three ways, one is to complete erase operation all the way, and then to perform write operation and read operation on the Block cycle of which erase operation has been completed, namely, in the form of "erase operation all → write operation → read operation → write operation → read operation … …", and the write operation and the read operation are performed in sequence, in other words, in a way of writing while reading; the second is a form in which an erase operation, a write operation, and a read operation are performed alternately, that is, "erase operation → write operation → read operation → write operation → read operation … …", that is, a manner of writing while erasing and reading while reading; <xnotran> , " → → → → → → → 5363 zxft 5363" " → → → → → → → → 3242 zxft 3242" , , , . </xnotran>
It is noted that, regardless of the mode one/mode two/mode three, the number of blocks performing erase/write/read operations at different times may not be uniform.
In addition, whether a certain Block is a bad Block is detected, whether the data of the write operation and the read operation are consistent or not is judged, the inconsistency indicates that the Block has an error, and whether the error Count (FBC) of the Block exceeds a preset value (error Count threshold) or not is judged at this time, and if the error Count (FBC) exceeds the preset value, the storage Block is a bad Block.
The memory chip is erased in blocks (corresponding memory blocks) as a unit, and the larger the Block Size is, the longer the erase time is.
Specifically, the Block executes an erase operation, a write operation and a read operation in a TLC (Triple-Level Cell), a QLC (Quad-Level Cell), an SLC (Single-Level Cell) or an MLC (Multi-Level Cell) programming manner.
When only one bit of information is stored in each memory cell, this approach is called single level memory cell (SLC); when two bits of information are stored, they are called multi-level cells (MLC), when three bits of information are stored, they are called three-level cells (TLC) or 3-bit MLC, and when four bits of information are stored, they are called four-level cells (QLC). With the increase of bits represented on a memory cell, the information stored under the same wafer area and process technology increases, but the erasing life of the memory cell is reduced, and the time consumption of erasing operation and writing operation is increased, i.e. the overall performance and reliability of the whole chip are reduced.
Step 22: in response to a memory block being a bad block, the bad block is marked.
Specifically, in response to a memory Block being a bad Block, the memory Block is marked as bad Block or weak Block, and no more data is stored in the memory Block.
Different from the prior art, the bad Block detection of the storage type chip provided by the application can perform erasing operation, writing operation and reading operation on the bad Block, and does not perform full erasing/writing/reading operation, because the FBC (error count) for performing full erasing/writing and reading Block is higher, the storage chip is detected in a mode of writing and reading while, the FBC can be in a stable state, and the effect of reducing the detection time is further achieved.
Referring to fig. 3, fig. 3 is a schematic flowchart of a bad block detection method according to a second embodiment of the present application, and the bad block detection method includes the following specific steps:
step 31: at least a part of memory blocks in the memory chip, which are not subjected to the erase operation, are selected to perform the erase operation each time.
Firstly, determining a Block which does not execute an erasing operation from any memory chip; secondly, determining the number of blocks needing to be subjected to erasing operation, wherein the number is less than or equal to the total number of the blocks not subjected to erasing operation; finally, an erase operation is performed on a selected number of blocks.
Step 32: and selecting at least part of the memory blocks from the memory blocks which are subjected to the erasing operation each time to perform writing operation, and selecting at least part of the memory blocks from the memory blocks which are subjected to the writing operation to perform reading operation until all the memory blocks in the memory chip are subjected to the erasing operation, the writing operation and the reading operation.
In an embodiment, all the memory blocks which have performed the erasing operation each time perform the writing operation, and all the memory blocks which have performed the writing operation perform the reading operation, i.e. the mode of "erase N → write N → read N → erase M → write M → read M → erase L → write L → read L …", wherein the values of N, M and L may be the same or different.
It should be noted that, a preset time is provided between the write operation and the read operation performed on the same memory block, and the preset time is variable, that is, after the write operation is completed, the read operation may be performed after a period of time has elapsed, or the read operation may be performed immediately after the write operation is completed, which is not limited herein.
Step 33: and determining the number of the memory cells with errors in the memory block based on the write data and the read data of the memory cells in any memory block.
Specifically, whether a certain Block is a bad Block is judged, and the number of the memory cells with errors is determined by judging whether the write data of all the memory cells in the Block is consistent with the corresponding read data.
Step 34: and judging whether the number of the storage units with errors in the storage block is larger than an error number threshold value or not.
When the number of errors of a certain Block memory unit exceeds the error number threshold value, the Block is a bad Block. Where the error threshold is related to the number of memory cells, the error threshold may be a certain percentage of the number of memory cells, such as 85%, 90%, etc.
If so, go to step 35.
Step 35: and determining the storage block as the bad block, and marking the bad block.
When a Block is identified as bad, it is marked as bad Block or weak Block and is no longer used to store data, etc.
For example, a certain memory chip includes 256 blocks which do not perform erase operation, 16 memory blocks are selected from the 256 memory blocks for the first erase operation, then 12 memory blocks are selected from the 16 memory blocks which have completed erase operation for the write operation, and then 10 memory blocks are selected for the read operation; selecting 16 storage blocks for erasing operation for the second time, wherein 20 storage blocks which are subjected to erasing operation can be selected for executing writing operation; and continuing the operation until the blocks which do not execute the erasing operation all complete the erasing operation, the writing operation and the reading operation. That is, the pattern is "erase N → write M → read L"
For example, a certain memory chip contains 256 blocks which do not perform erase operation, 16 memory blocks are selected from the 256 memory blocks for the first time to perform erase operation, then 16 memory blocks are selected from the 16 memory blocks to perform write operation, and then 12 memory blocks are selected from the 16 memory blocks to perform read operation; selecting 16 storage blocks for erasing operation for the second time, wherein 16 storage blocks can be selected for executing write operation, and if 16 write operations are selected for executing write operation for the second time, 20 storage blocks can be used for executing read operation; and continuing the operation until the Block which does not execute the erasing operation completely executes the erasing operation, the writing operation and the reading operation. That is, the pattern is "erase N → write N → read M".
In other embodiments, the manner in which the erase, write, and read operations are performed may also be "erase N → write M → read M", "erase N → write N → read N". And the number of blocks performing the erase/write/read operations at different times may be different, such as "erase N → write M → read M → erase L → write H → read H", "erase N → write N → read N → erase M → write M → read M", etc.
Different from the prior art, the bad Block detection method provided by the application detects bad blocks in a mode that erasing operation, writing operation and reading operation are carried out circularly, can stabilize the error number of the Block to be stable, and further reduces the detection time.
Referring to fig. 4, fig. 4 is a schematic flowchart of a bad block detection method according to a third embodiment of the present application, where the bad block detection method includes the following specific steps:
step 41: at least a part of the memory blocks in the memory chip which are not erased are selected to be erased at a time.
It will be appreciated that the number of at least some of the memory blocks ranges between 1 and the total number of memory blocks for which no erase operation is performed.
Step 42: and all the storage blocks which have executed the erasing operation each time execute the writing operation, and all the storage blocks which have executed the writing operation execute the reading operation.
For example, a certain memory chip includes 256 blocks which do not perform an erasing operation, 16 blocks are selected from the 256 blocks for the first time to perform an erasing operation, then a writing operation is performed on the 16 blocks which have completed the erasing operation, and a reading operation is performed on the 16 blocks which have completed the writing operation; selecting 16 memory blocks from 240 blocks for erasing operation for the second time, and then performing writing operation and reading operation on the 16 memory blocks; and continuing to perform the operation so as to realize that all the blocks which do not execute the erasing operation, the writing operation and the reading operation. That is, the pattern is "erase N → write N → read N → erase N → write N → read N".
For example, a certain memory chip includes 256 blocks which do not perform an erasing operation, 16 blocks are selected from the 256 blocks for the first time to perform the erasing operation, then a writing operation is performed on the 16 blocks, and a reading operation is performed on the 16 blocks which complete the writing operation; selecting 18 blocks for the second time to perform erasing operation, and then performing writing operation and reading operation on the 18 blocks which have completed the erasing operation; the above operations are continued until all blocks which do not execute the erasing operation complete the erasing operation, the writing operation and the reading operation. That is, the pattern is "erase N → write N → read N → erase M → write M → read M".
That is, the number of blocks performing the erasing operation at different times may be the same or different.
Step 43: and determining the number of the memory cells with errors in the memory block based on the write data and the read data of the memory cells in any memory block.
Specifically, whether a certain Block is a bad Block is judged, whether the write data and the read data of the memory cell in the Block are consistent or not is judged, and if the write data and the read data are inconsistent, the memory cell is indicated to have an error.
Step 44: and judging whether the number of the storage units with errors in the storage block is larger than an error number threshold value or not.
If so, go to step 45.
Step 45: and determining the storage block as the bad block, and marking the bad block.
Different from the prior art, the bad block detection method provided by the application sets the number of the storage blocks which execute the erasing operation, the writing operation and the reading operation to be consistent each time, so that the reading and the writing are realized while the error number is in a stable state, and the detection time can be further reduced.
Referring to fig. 5, fig. 5 is a schematic flowchart of a fifth embodiment of the bad block detection method provided in the present application, and the bad block detection method specifically includes the following steps:
step 51: at least part of the memory blocks in the memory chip which are not subjected to the erasing operation are selected to perform the erasing operation each time, and at least part of the memory blocks in the memory chip which are subjected to the erasing operation each time are selected to perform the writing operation.
The number of memory blocks each time the erase operation is performed is a natural number, and is a natural number equal to or greater than 1, which is smaller than the total number of memory blocks on which the erase operation is not performed. Similarly, the number of memory blocks in which a write operation is performed at a time is also a natural number, and is greater than or equal to 1 and less than the total number of memory blocks in which no write operation is performed.
For example, the number of blocks which do not execute the erasing operation in a certain memory chip is M, N blocks are selected from the M blocks to execute the erasing operation, and then N or L (1 ≦ L < N) blocks are selected from the N blocks which finish the erasing operation to perform the writing operation.
Step 52: and selecting a storage block in which at least part of the write operation is finished from the partial storage blocks in which the erase operation is finished at least twice to execute the read operation until all the storage blocks in the storage chip execute the erase operation, the write operation and the read operation.
It is to be noted that the read operation is performed on a memory block on which the write operation has been completed on the premise that there is a memory block on which the erase operation or the write operation is not performed.
For example, the number of blocks in a certain memory chip which do not execute the erasing operation is M, N (N < M) blocks are selected from M blocks to execute the erasing operation, then N or L (1 ≦ L < N) blocks are selected from N blocks to execute the writing operation, then N (M > 2*N) or T (T ≠ N, and T ≦ M-N) blocks are selected from M-N blocks which do not execute the erasing operation to execute the erasing operation,
in some embodiments, N blocks are selected to perform a write operation, when performing the second erase operation, N or H (1 ≦ H < N) blocks are selected from the N blocks to perform an erase operation, and then N/P blocks are selected from the N blocks to perform a write operation, or H/Q blocks are selected from the H blocks to perform a write operation, that is, "erase N → write N → erase N → write N" or "erase N → write N → erase N → write P" or "erase N → write N → erase H → write H" or "erase N → write H → erase H → write Q", and then a third erase cycle or a read operation is performed, and if an erase cycle is performed, a condition that there is a Block that is not performing an erase operation or a write operation when performing a read operation is satisfied, so as to achieve an effect of reading while writing.
In some embodiments, if L blocks are selected to perform a write operation, L or K (1 ≦ K < L) blocks are selected to perform an erase operation from the L blocks when a second erase operation is performed, and then L/D blocks are selected to perform a write operation from the L blocks, or K/Z blocks are selected to perform a write operation from the K blocks, i.e., "erase N → write L → erase L → write L" or "erase N → write L → erase L → write D" or "erase N → write L → erase K → write K" or "erase N → write L → erase K → write Z", and then a third erase operation loop or a read operation is performed, it is also necessary to satisfy the condition that there is a Block that is not performing an erase/write operation when a read operation is performed. Step 53: and determining the number of the memory cells with errors in the memory block based on the write data and the read data of the memory cells in any memory block.
The specific way of determining the number of faulty memory cells in the memory block is the same as the method described above, and is not described herein again.
Step 54: and judging whether the number of the storage units with errors in the storage block is larger than an error number threshold value or not.
The specific method for determining whether the storage block is a bad block is the same as the method described above, and is not described herein again.
Step 55: and determining the storage block as the bad block, and marking the bad block.
Different from the prior art, the bad block detection method provided by the application is performed by at least two times of circulation of erasing operation and writing operation, then the reading operation is performed, and the storage block which does not finish the erasing/writing operation exists during the reading operation, so that the reading and the writing can be realized while the error number of the storage unit in the storage block is in a stable state, and the detection time can be further reduced.
Referring to fig. 6, fig. 6 is a schematic flowchart of a bad block detection method according to a sixth embodiment of the present application, and the bad block detection method includes the following specific steps:
step 61: and performing erasing operation on all the memory blocks in the memory chip.
It can be understood that the erase operation is performed on all blocks in a certain memory chip, i.e., "erase all".
Step 62: and selecting at least part of the storage blocks from which the erasing operation is executed to perform writing operation each time, and selecting at least part of the storage blocks from which the writing operation is executed to perform reading operation until all the storage blocks in the storage chip perform the erasing operation, the writing operation and the reading operation.
For example, the number of blocks which do not execute the erasing operation in a certain memory chip is M, the erasing operation is executed on the M blocks, then M/N (1 ≦ N < M) blocks are selected from the M blocks which have completed the erasing operation to execute the writing operation, and then M/H (1 ≦ H < M) blocks are selected from the M blocks which have completed the writing operation to execute the reading operation, or N/L (1 ≦ N < L) blocks are selected from the N blocks which have completed the writing operation to execute the reading operation. Namely "erase M → write M → read M" or "erase M → write M → read H" or "erase M → write N → read N" or "erase M → write N → read L".
Next, the cycle of the second write operation and the read operation may continue as described above.
And step 63: and determining the number of the memory cells with errors in the memory block based on the write data and the read data of the memory cells in any memory block.
Specifically, an error number threshold is set, when the write operation and the read operation are inconsistent, the error number is one, and when the total error number of the storage units in the Block exceeds the error number threshold, the Block is represented as a bad Block.
Step 64: and judging whether the number of the storage units with errors in the storage block is larger than an error number threshold value or not.
For a specific method for determining a bad block, reference may be made to the foregoing method, which is not described herein again.
Step 65: and determining the storage block as the bad block, and marking the bad block.
Different from the prior art, the bad block detection method provided by the application completes the erasing operation through the whole disk, then realizes the cyclic operation of the writing operation and the reading operation, namely, the mode of writing while reading, and can reduce the time for detecting the bad block through the mode.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of the detection apparatus provided in the present application, where the detection apparatus 70 includes a memory 701 and a processor 702, the memory 701 stores program data, and the processor 702 is configured to execute the program data to implement a bad block detection method for a memory chip, which is as follows:
performing an erasing operation, a writing operation and a reading operation on at least one storage block of the storage chip, and determining whether any storage block in the at least one storage block is a bad block, wherein the number of the storage blocks in the at least one storage block is less than the total number of the storage blocks in the storage chip;
in response to a memory block being a bad block, the bad block is marked.
The processor 702 may also be referred to as a Central Processing Unit (CPU), and the processor 702 may be an integrated circuit chip having signal Processing capability, a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.
Referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of a computer-readable storage medium 80 provided in the present application, where the computer-readable storage medium 80 stores program data 801, and when the program data 801 is executed by a processor, the program data 801 is used to implement the bad block detection method described above, and details are not repeated here.
The computer-readable storage medium 70 may specifically be a medium that can store program instructions, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, or may also be a server that stores the program instructions, and the server may send the stored program instructions to another device for operation, or may self-operate the stored program instructions.
The above description is only an embodiment of the present application, and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes performed by the present application and the contents of the attached drawings, which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (12)
1. A bad block detection method of a memory chip, the method comprising:
performing an erasing operation, a writing operation and a reading operation on at least one storage block of the storage chip, and determining whether any storage block in the at least one storage block is a bad block, wherein the number of the storage blocks in the at least one storage block is less than the total number of the storage blocks in the storage chip;
in response to a memory block being a bad block, the bad block is marked.
2. The method of claim 1,
the executing erasing operation, writing operation and reading operation on at least one memory block of the memory chip comprises:
selecting at least part of memory blocks from memory blocks which are not subjected to erasing operation in the memory chip to execute erasing operation each time;
and selecting at least part of the memory blocks from the memory blocks which are subjected to the erasing operation each time to perform writing operation, and selecting at least part of the memory blocks from the memory blocks which are subjected to the writing operation to perform reading operation until all the memory blocks in the memory chip are subjected to the erasing operation, the writing operation and the reading operation.
3. The method of claim 2, wherein the number of memory blocks performing the erase operation at different times is the same or different.
4. The method of claim 2,
the selecting at least part of the memory blocks from which the erasing operation is performed each time to perform the writing operation and selecting at least part of the memory blocks from which the writing operation is performed to perform the reading operation includes:
and all the storage blocks which have executed the erasing operation each time execute the writing operation, and all the storage blocks which have executed the writing operation execute the reading operation.
5. The method of claim 2,
and a preset time is separated between the execution of the write operation and the execution of the read operation on the same storage block.
6. The method of claim 1,
the performing an erase operation, a write operation, and a read operation on at least one memory block of the memory chip includes:
selecting at least part of memory blocks from memory blocks which do not execute the erasing operation in the memory chip to execute the erasing operation each time, and selecting at least part of memory blocks from memory blocks which execute the erasing operation each time to execute the writing operation;
and selecting a storage block in which at least part of the write operation is finished from the partial storage blocks in which the erase operation is finished at least twice to execute the read operation until all the storage blocks in the storage chip execute the erase operation, the write operation and the read operation.
7. The method of claim 1,
the executing erasing operation, writing operation and reading operation on at least one memory block of the memory chip comprises:
performing erasing operation on all storage blocks in the storage chip;
and selecting at least part of the memory blocks from the memory blocks which have executed the erasing operation to perform writing operation each time, and selecting at least part of the memory blocks from the memory blocks which have executed the writing operation to perform reading operation until all the memory blocks in the memory chip have executed the erasing operation, the writing operation and the reading operation.
8. Method according to any of claims 6-7, characterized in that the number of memory blocks performing a write operation or a read operation at different times is the same or different.
9. The method of claim 1,
the determining whether any of the at least one memory block is a bad block includes:
determining the number of storage units with errors in the storage blocks based on the write data and the read data of the storage units in any storage block;
and determining the storage block as the bad block in response to the number of the storage units with errors in the storage block being larger than an error number threshold.
10. The method of claim 1, wherein the memory blocks in the memory chip perform erase, write and read operations using TCL, QLC, SLC or MLC programming.
11. A detection apparatus comprising a memory storing program data and a processor for executing the program data to implement the bad block detection method of any one of claims 1-10.
12. A computer-readable storage medium, characterized in that the computer-readable storage medium stores program data for executing the bad block detection method according to any one of claims 1 to 10 when the program data is executed by a processor.
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