JP2001013932A - Matrix type display device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain excellent contrast in a method for driving a quick response STN liquid crystal. SOLUTION: This drive method is constituted of a memory means storing plural rows of the display data, a function generation means 22 generating a drive function of a row electrode, an operation means operating the outputs of these means, a column electrode drive means 18 driving a column electrode according to the output of the operation means and a row electrode drive means 24 driving a row electrode according to the row electrode drive function. Since operation object are several rows part, the circuit scale of the memory means, the operation means, etc. is reduced. Further, a voltage applied to a matrix becomes average in a period when the row electrode drive function has values of 1, -1, and the drive suitable for quick response is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving method and a display device thereof, and more particularly to a high-speed response STN (Super T).
The present invention relates to a driving method for displaying high contrast liquid crystal (wisted nematic) liquid crystal and a display device thereof.

[0002]

2. Description of the Related Art Conventionally, as a method of driving a liquid crystal display device having a matrix structure, an Itriple-E Transactions on Electron Device (IEEE) has been proposed.
Transactions on Electron
devices Vol. ED-26, no. 5, M
ay1979 (PP795-) UltimateLi
mits for Matrix Addressin
go of RMS-Responding Liqui
d-Crystal Display and SID92 '
Digest Active Addressing
Methodfor High-Contrast V
As described in “ideo-Rate STN Display”, a voltage according to a function having orthogonality is applied to a row electrode, and a function of the sum of products of all display information of the column and a function on a scanning side is applied to a column electrode. A display method has been proposed.
Hereinafter, the driving method will be described in detail with reference to FIGS.

FIG. 2 is a diagram showing the structure of a liquid crystal display unit having a matrix structure of N rows and M columns, where the intersections of row electrodes and column electrodes form display dots. Voltages represented by functions of f (1) to f (N) are applied to the N row electrodes, and voltages represented by functions of g (1) to g (M) are applied to the M column electrodes. Applied. U (i, j) indicates the voltage applied to the dot at the intersection of row i and column j, which is f (i)
And g (j). FIG. 3 is a diagram showing an example of an orthogonal function applied to a row electrode generally used as a drive waveform of an STN liquid crystal at present. A driving method generally used as a driving method of the STN liquid crystal at present will be described with reference to FIGS. Assuming that f (i) is represented by the function in FIG. 3, f (i) and g (j) can be expressed by equations (1) and (2), respectively.

[0004]

(Equation 8)

Here, δ (i, t) is 1 at i = t, i ≠
j is 0, and FP is a constant given by equation (3).

[0006]

(Equation 9)

P (i, j) indicates the display information of the dot at the intersection of the i-th row and j-th column, and becomes -1 when the display is on and 1 when the display is off. At this time, the effective value Urms (i, j) of the voltage applied to the dot U (i, j) is given by the following equations (1), (2), and (3).
Can be calculated as follows.

[0008]

(Equation 10)

Here, the deformation is performed with T = N.

[0010]

[Equation 11]

[0011]

(Equation 12)

From the above, Urms (i, j) is given by equation (4)
Becomes At this time, if P (i, j) turns on the display,
(I, j) = − 1, and equation (4) becomes equation (5). When the display is turned off, P (i, j) = 1 and equation (6) is obtained.

[0013]

(Equation 13)

As described above, the effective value of the voltage applied to the dot U (i, j) is the information P (i,
j) yields equations (5) and (6). The voltage waveform applied to U (i, j) is (f (i) -g (j)), which is the waveform shown in FIG. 4 from equations (1) and (2). In FIG. 4, S1, S2, and S3 are represented by the following equations.

[0015]

[Equation 14]

If N = 240, S1 = 12.1
(U (i, j) = display ON), 10.6 (U (i, j)
= Display off) S2 = 0.73, S3 = -0.73, and a large (i = t) voltage is applied once per frame (period of t = 1 to N), and a low voltage is applied to the rest. . Therefore, it is conceivable that the display luminance of the STN liquid crystal having a high response speed is reduced during the period in which the low voltage is applied. Therefore, the following method has been proposed as a driving method for solving this. This driving method will be described. FIG. 5 shows an example of an orthogonal function called a Walsh function with division = 8. Now, a dot U () obtained when a Walsh function of division = T is used as a function of a row electrode of the liquid crystal display unit in FIG. 2 and N Walsh functions are selected and applied (T ≧ N) to T (f) for f (i). The effective voltage value Urms (i, j) of (i, j) is as follows.

[0017]

(Equation 15)

[0018]

(Equation 16)

Here, f (i) and G (j) are expressed by the following equation (7).
Let it be given by equation (8).

[0020]

[Equation 17]

Here, W (i, t) is a Walsh function and takes a value of 1 or -1, and FP is a constant represented by equation (9).

[0022]

(Equation 18)

From the above, the effective voltage value of the dot U (i, j) is given by the following equation.

[0024]

[Equation 19]

The value is the same as the expression (4). When the display is on, the value is the expression (5), and when the display is off, the value is the expression (6). That is, even if the function of the voltage applied to the row electrode is the Walsh function shown in FIG. 5, the effective value of the voltage applied to the dot U (i, j) is determined by the display ON and OFF of the dot according to Expression (5).
It will be shown by equation (6).

In this case, if g (j) in equation (8) is transformed into the following equation,

[0027]

(Equation 20)

Here, D is P (i,
j) and the number of matches between w (i, j) values (P (i, j) are ±
1, W (i, j) takes a value of ± 1). At this time D
Is represented by a normal distribution represented by the following equation.

[0029]

(Equation 21)

From equation (11), since D follows a normal distribution centered on N / 2, the value of equation (10) also follows a normal distribution. Accordingly, the voltage waveform (f (i) -g (j)) applied to U (i, j) is different from FIG.
During this period, the averaged voltage is applied.

[0031]

According to the above conventional driving method, when a voltage function applied to a row electrode is a Walsh function,
From the equations (7) and (8), the voltage function g that can be applied to the column electrode
(J) becomes equation (12). To determine the applied voltage for one dot at a certain time t, the product of the display information P (i, j) for i = 1 to N and the Walsh function W (i, t) It is necessary to calculate the sum, which is difficult to realize, and a specific driving circuit is not specified. On the other hand, assuming that the voltage function given to the row electrode is the function shown in FIG. 3, the voltage function g (j) applied to the column electrode is expressed by the following equation (13).

[0032]

(Equation 22)

No product sum is required and the circuit configuration is simplified. However, in this case, as shown in FIG. 4, the dot U (i, j)
Is a high voltage only once every N times, and a low voltage during the remaining N-1 times.
When displaying a TN liquid crystal, it is conceivable to lower the contrast.

An object of the present invention is to show a voltage function to be applied to a new row electrode which has a simple circuit structure and does not lower contrast even for a high-speed response STN liquid crystal, and to show a feasible circuit structure. It is.

[0035]

In order to achieve the above object, a line function generating means, a function generating means, a line memory means for storing display data of X rows, an operation for calculating outputs of the line memory means and the function generating means are provided. Means and a voltage generating means for converting the output of the calculating means into a voltage are provided.

The row function generating means generates a function such that only the X row is a Walsh function at a certain time t among the N rows, and the remaining rows become 0, and gives the function to the row electrode driving means of the liquid crystal. The function generating means generates the same value as the Walsh function of the X-th row, and its output is calculated with the output of the line memory means, and the calculation result is converted into a voltage and provided to the column electrode driving means.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device according to one embodiment of the present invention. Before describing the operation of the liquid crystal display of FIG. 1, a voltage waveform applied to the liquid crystal will be described. FIG. 6 shows a case in which the voltage function applied to the N row electrodes is a Walsh function for only eight rows, one frame period T is 2N (N is the number of display rows), and the Walsh function for the eight rows is driven by division = 16. It is a figure showing the voltage function of a row electrode. The liquid crystal display section has N rows and M columns as in the conventional example. In this case, the voltage function applied to the row electrode and the voltage function applied to the column electrode are expressed by equations (20) and (21), respectively.

[0038]

(Equation 23)

Here, FP is a constant represented by the equation (22), and B (i, t) is a function shown in FIG.

[0040]

(Equation 24)

Further, P (i, j) is equal to i
-1 when dot on row, j column is display on, 1 when display is off
Becomes Using the equations (20) to (22), the dot U (i,
Calculation of the voltage effective value Urms (i, j) of j) is as follows.

[0042]

(Equation 25)

[0043]

(Equation 26)

[0044]

[Equation 27]

[0045]

[Equation 28]

From this, the effective voltage value of U (i, j) is given by equation (23).
Since (i, j) is −1, its effective voltage value is given by equation (2)
4), and when the display is off, P (i, j) is 1, so that equation (25) is obtained.

[0047]

(Equation 29)

FIG. 1 shows the voltage function applied to the row electrodes.
By comparing the expressions (24) and (25) with the expressions (5) and (6), it can be seen that the effective voltages of the display ON and OFF are the same as those in the conventional example.

As described above, eight of the N rows are assumed to be Walsh functions, and the Walsh functions of the eight rows are driven by 16 divisions. However, the present invention is not limited to this. It is also possible to use a Walsh function and drive this Walsh function by K division. This time R
It is assumed that the relationship of <N, K ≧ R holds.

Hereinafter, f (i) and g in the generalized case
(J) is shown in equations (26) and (27), and the constant F in this case is
P is shown in equation (28). At this time, a voltage effective value Urms (i, j) of U (i, j) is calculated.

[0051]

[Equation 30]

[0052]

(Equation 31)

[0053]

(Equation 32)

This is consistent with equation (23). As described above, even if the equation (29) is satisfied even if the dot is placed as described above, the effective voltage value Urms (i, j) of the dot U (i, j) is obtained.
Becomes the same as the conventional example. In the present embodiment, the description has been made using the Walsh function. However, the present invention is not limited to this. Any orthogonal function having values of 1 and −1 from the progress of the calculation of the effective value may be used. Hereinafter, this driving method is referred to as a partial orthogonal function driving method and will be described.

[0055]

[Equation 33]

Next, one embodiment of the liquid crystal drive circuit described above will be described with reference to FIGS. 1 and 7 to 14. FIG. 7 is a block diagram of one embodiment of the column signal generating means for realizing the partial orthogonal function driving method.
"1" and display off are represented by "0."
Is A data, 4 is B data, 5 is a line memory A for storing X rows of data, 6 is a line memory B for storing X rows of data, and the writing means 2 is through A data 3 and B data 4. Then, the display data 1 is written to the line memories A5 and B6. At this time, the writing means 2 alternately writes data to the line memories A5 and B6 every X rows. 7 is read data A, 8 is read data B, 9
Is reading means, and reading means 9 is a line memory A
5. Read out the stored data via the readout data A7 and the readout data B8 from the line memory B6 which has not been written. Note that this reading operation is to simultaneously read data for X rows. Reference numeral 10 denotes display information read from the line memory by the reading means 9 and is X-line display data. 11 is an operation means, 13 is a function generation means, 13 is X-line function data,
Performs a product-sum operation of X-row display data 10 and X-row function data 13 which are display information. Numeral 14 denotes operation data, 15 denotes voltage conversion means, and 16 denotes analog display data. The operation data 14, which is the operation result of the operation means 11, is converted into a voltage by the voltage conversion means to be analog display data.

FIG. 1 is a block diagram of one embodiment of a liquid crystal display device using the column signal generating means of FIG. 7, wherein 17 is the column signal generating means described in FIG. 6, and 18 is the column electrode driving means. To fetch one line of analog display data, and then simultaneously output one line of data. Note that the data acquisition for one row is performed in one division period. Reference numerals 19 to 21 denote column electrode signals, which are a one-column electrode signal, a two-column electrode signal, and an M-column electrode signal, respectively. Reference numeral 22 denotes a row function generating means for generating the row function shown in FIG. 23 is a row function data; 24 is a row electrode driving means; and a row function generating means 22 is a function for a row of one division time.
And the row electrode driving means 24 outputs a voltage according to the value to the row electrode after the writing is completed. The writing of the row function data 23 is also performed in one division period, and is synchronized with the cycle of the one division period of writing the analog display data 16 of the column electrode driving unit 18. Reference numerals 25 to 27 denote row electrode signals, which are a one-row electrode signal, a two-row electrode signal, and an N-row electrode signal, respectively. Reference numeral 28 denotes a liquid crystal panel for displaying N rows and M columns. FIG. 8 shows that the liquid crystal panel 28 has four rows and four rows in this embodiment.
FIG. 9 is a diagram showing dot information of the liquid crystal panel when columns are set, FIG. 9 is a diagram showing values at each t of the X row function data 13 of the function generating means 12, and FIG. 10 is X row read data 10 and X row function data. FIG. 11 is a block diagram of an embodiment of the arithmetic means 11, in which 29 and 30 are inversion circuits for performing logical inversion, 31 and 32 are EXOR circuits which take exclusive OR, and 33 is Decoding means. FIG.
FIG. 3 is a diagram for explaining the operation of the decoding means 33.
3 is a diagram showing the value of each t in the function data 23 output from the row function generating means 12, and FIG. 14 is a timing chart for explaining the operation of the column electrode driving means 18 and the row driving means 24.

In this embodiment, for convenience of explanation, the liquid crystal panel 28 is described as having four rows and four columns, X = 2, and these two rows are driven in quadrants. That is, one frame is driven by eight divisions (see equation (29)). First, the operation of FIG. 7 will be described.

The display data 1 corresponds to the liquid crystal panel 28 shown in FIG.
U (1,1), U (1,2)... For each dot
U (2,1), U (2,2) ... U (4,1), U
(4, 2) ... U (4, 4) is sent serially. The display data 1 is alternately written into the line memories A5 and B6 by the writing means 2 every two rows. That is, the data in the first and second rows is stored in the line memory A
In 5, the data in the third and fourth rows are written to the line memory B6. Now, assuming that the writing of the data of the first and second rows to the line memory A5 has been completed and the data of the third row has been written to the line memory B6, the reading means 9 reads the data written from the line memory A5. From the line memory A5. At this time, read data A
7 simultaneously converts U (1,1) and U (2,1) into U (1,1).
2) and U (2,2) are read at the same time and data in the row direction are read at the same time and output as X-row read data 10. According to each time t (t = 1 to 4 are repeated because two rows are driven in four divisions), the function generating means h shown in FIG.
X-line function data of (1) and h (2) is generated. Here, the function data h (1) and h (2) are 1 bit and −1
Are indicated by "0" and +1 by "1". Here, the timing of the operation of the function generating means 12 and the timing of the operation of the reading means 9 will be described with reference to FIG. X row function data 13 is h for t = 1
When the values are (1) and h (2), as shown in FIG. 10, the reading means 9 sequentially reads two rows of data from the first column to the fourth column. This is repeated until t = 4, and after completion, the function generating means generates X-row function data 13 again from t = 1.
On the other hand, the reading means 9 reads data from the line memory B6 by the same operation as reading from the line memory A5. Next, the operation of the calculating means 11 will be described with reference to FIGS.
This will be described with reference to FIG. Now, the X-line read data is U (1,
1), U (2, 1), and the X row function data is h (1), h
Assuming that (2), the display data indicates “1” for display-on and “0” for display-off. Therefore, P (i,
In order to match the expression of j), U
(1,1) and U (2,1) are inverted. The inverted data are taken as exclusive-OR circuits by h (1) and h (2) by EXORs 31 and 32, respectively, and the output is decoded by data decoding means 33 in accordance with FIG. This means that the following equation is calculated, and the product sum of equation (21) is calculated.

[0060]

(Equation 34)

Accordingly, the operation data 14 takes one of the values shown in FIG.
(27) From (28), the voltage is converted so as to have the following voltage value, and is output as the analog display data 16.

[0062]

(Equation 35)

In this embodiment, N = 4 and R = 2. Voff is a coefficient for converting the display off voltage to "1" as shown by the equation (25), so that it is converted to an actual drive voltage. As described above, the column signal generating means in FIG. 7 realizes the partial orthogonal function drive described in equations (20) to (29). Next, an embodiment of a liquid crystal display device using the column signal generating means shown in FIG. 7 will be described with reference to FIG.

The display data 1 is converted by the column signal generating means 17 into a signal according to the equation (27), and is converted into a voltage according to the equation (30). The analog display data 16 is sequentially taken into the column electrode driving means 18, and this data is simultaneously output as a column electrode signal at the end of taking in one row. The row function generating means 22 is a function shown in FIG.
3 are sequentially output as f (1), f (2), f (3), f (4). The row electrode driving means 24 receives this row function data 23, and after receiving all the data for one column, outputs it as a row electrode signal. As described above, the column electrode means 18 and the row electrode means 2
The operation timing of No. 4 is shown in FIG.

According to the method of driving the STN liquid crystal described above, the operation of the column signal represented by the equation (27) is N in the prior art.
R rows (R <N) are sufficient for the row division, and the circuit is easy to realize. Here, one operation time (ta in FIG. 10) for 240 rows and 640 columns is obtained. Here, the frame frequency is 60 Hz, R = 8, and K = 16.

[0066]

[Equation 36]

That is, eight rows (R =
8) It is sufficient to read the data for the minute and perform the calculation. this is,
As shown in the embodiment, it is easy to simultaneously read out eight rows of data and perform calculations. On the other hand, in the conventional driving method, ta is as follows.

[0068]

(37)

The ta itself becomes longer as compared with the partial orthogonal function drive. However, it is difficult for a logic circuit to read out and calculate 240 rows of data in about 100 ns. That is, the processing speed for one row of data is 0.4 n.
s, and even if the speed is reduced to a speed feasible on a logic circuit by performing the parallel drive, the number of parallels increases, resulting in a large logic scale. In comparison, in the partial orthogonal function driving, the number of rows of the operation is small, and it can be realized with a small logical scale.

Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 15 is a block diagram of the liquid crystal display device of the present embodiment. Before describing the operation of the liquid crystal display of FIG. 15, a voltage waveform applied to the liquid crystal will be described. FIG. 16 shows N
The voltage function applied to the row electrodes is a Walsh function for only eight rows, one frame period T is 2N (N is the number of display rows), and the Walsh function of the eight rows is divided by = 16 and the row electrodes are driven. It is a figure showing a voltage function. Further, the liquid crystal display section has N rows and M columns as in the conventional example. In general, when a voltage function applied to N row electrodes is a Walsh function only for m rows, a period of one frame is T, and a division number of the Walsh function for the m rows is s, the voltage function is applied to each row electrode. The voltage function Fh, the voltage function Gj applied to each column electrode, and the effective value Ur of the voltage applied to the pixel on the ith row and the jth column
ms is as follows.

[0071]

(38)

[0072]

[Equation 39]

[0073]

(Equation 40)

[0074]

[Equation 41]

From the above, the effective value Urms of the voltage applied to the pixel on the i-th row and the j-th column is expressed by the following equation (36). When the display is on, Iij is −1, and when the display is off, Iij is +1. Therefore, the respective voltage execution values are expressed by Expressions (37) and (3).
8).

[0076]

(Equation 42)

Here, when the operation margin R is defined, the following equation (39) is obtained.

[0078]

[Equation 43]

In Expression (39), c that maximizes the operation margin R is obtained as Expression (40).

[0080]

[Equation 44]

By substituting equation (40) into equations (37) and (38), Urms (on) and Urms (off) become equations (41) and (42).

[0082]

[Equation 45]

When the equation (40) is substituted into the equation (39), the operation margin R becomes the equation (43).

[0084]

[Equation 46]

Here, if Urms (off) is set to 1, F is converted to Eq. (44) from Eq. (42).

[0086]

[Equation 47]

By substituting equation (44) into equation (41) and equation (42), Urms (on) and Urms (off) become equations (45) and (46).

[0088]

[Equation 48]

As described above, when the voltage function applied to the row electrode is as shown in FIG. 16, the display ON / OFF voltage execution value is the same as that of the conventional example when N is nN. (45) It can be found by comparing equation (46) with equations (6) and (6). In the present embodiment, the description has been made using the Walsh function. However, the present invention is not limited to this. Any orthogonal function having values of 1 and −1 from the progress of the calculation of the effective value may be used. Hereinafter, this driving method is referred to as a partial orthogonal function driving method as in the first embodiment.

Next, a second embodiment of the liquid crystal drive circuit described above will be described with reference to FIGS. 15, 16 and FIGS. FIG. 7 is a block diagram of a column signal generating means for realizing the partial orthogonal function driving method, which has the same configuration as that of the first embodiment, and a description of each part will be omitted.

Since FIGS. 8 to 14 have the same configuration as the first embodiment, the description of each part is omitted. FIG.
5 is a block diagram of a second embodiment of the liquid crystal display device using the column signal generator of FIG. 7, and 17 is a column signal generator.
Numeral 18 denotes column electrode driving means for fetching analog display data for one row, and thereafter outputting data for one row all at once. Note that the data acquisition for one row is performed in one division period. Reference numerals 19 to 21 denote column electrode signals, which are a one-column electrode signal, a two-column electrode signal, and an M-column electrode signal, respectively. Numeral 34 denotes a row function generating means for generating the row function shown in FIG.

Reference numeral 23 denotes row function data, reference numeral 24 denotes row electrode driving means, and row function generating means 34 writes functions for one row of the divided time into the row electrode driving means 24 via the row function data 23. 24 outputs a voltage according to the value to the row electrode after the writing is completed. Note that this row function data 2
3 is also performed in one division period, and the column electrode driving means 1
8 is synchronized with the cycle of one division period for writing the analog display data 16. Reference numerals 25 to 27 denote row electrode signals, which are a one-row electrode signal, a two-row electrode signal, and an N-row electrode signal, respectively.
Reference numeral 28 denotes a liquid crystal panel for displaying N rows and M columns. still,
In the present embodiment, for convenience of explanation, the liquid crystal panel 28 is described as having four rows and four columns, X = 2, and driving these two rows by four. That is, one frame is driven by eight divisions (see equation (29)).

First, the operation of FIG. 7 will be described.

The display data 1 corresponds to the liquid crystal panel 28 shown in FIG.
U (1,1), U (1,2)... For each dot
U (2,1), U (2,2) ... U (4,1), U
(4, 2) ... U (4, 4) is sent serially. The display data 1 is alternately written into the line memories A5 and B6 by the writing means 2 every two rows. That is, the data in the first and second rows is stored in the line memory A
In 5, the data in the third and fourth rows are written to the line memory B6. Now, assuming that the writing of the data of the first and second rows to the line memory A5 has been completed and the data of the third row has been written to the line memory B6, the reading means 9 reads the data written from the line memory A5. From the line memory A5. At this time, read data A
U (1,1) and U (2,1) simultaneously, U (1,2)
And U (2,2) at the same time and data in the row direction are read at the same time and output as X-row read data 10. The function generating means operates at each time t (t 2
= 1 to 4), h (1), h shown in FIG.
The X-line function data of (2) is generated. Here, the function data h (1) and h (2) are 1 bit, and -1 is "0", +
1 is indicated by "1". Here, the timing of the operation of the function generating means 12 and the timing of the operation of the reading means 9 will be described with reference to FIG. X row function data 13 is h (1), h for t = 1
When the state is (2), the reading means 9 sequentially reads the data of two rows from the first column to the fourth column as shown in FIG. This is repeated until t = 4, and after completion, the function generating means generates X-row function data 13 again from t = 1. On the other hand, the reading means 9 reads data from the line memory B6 by the same operation as reading from the line memory A5. Next, the operation of the calculating means 11 will be described with reference to FIGS. Now, the X line read data is U (1, 1), U
In (2, 1), if the X-line function data is h (1), h (2), the display data is “1” for display on and “1” for display off.
0 ", the inverting circuits 29 and 30 use U (1,1), U (1,1) to match the expression of P (i, j) in the equation (21).
Invert U (2,1). The inverted data are EXORed with h (1), h (2) and the exclusive OR circuit, respectively.
At 31 and 32, the output is decoded by the decoding means 33 in accordance with FIG. This means that the product-sum operation of Expression (34) is performed. Accordingly, the operation data 14 takes one of the values shown in FIG. 12 and is converted by the voltage conversion means into the voltage values shown in the equations (31), (32), (34), (40), and (44). It is output as display data 16. In this embodiment, N = 4 and R = 2. Voff is a coefficient for converting the display off voltage to an actual driving voltage because the display off voltage is "1". As described above, the column signal generating means of FIG.
The partial orthogonal function drive described in 6) is realized.

Next, an embodiment of a liquid crystal display device using the column signal generating means shown in FIG. 7 will be described with reference to FIG. The display data 1 is converted by the column signal generating means 17 into a signal according to equation (34). This analog display data 16
Are sequentially taken into the column electrode driving means 18, and this data is simultaneously output as a column electrode signal at the end of taking in one row. The row function generator 22 converts the row function data 23 into f (1), f (2), f (3), f (4) using the function shown in FIG.
Are sequentially output. The row electrode driving means 24 receives the row function data 23, and after receiving all the data for one column, outputs it as a row electrode signal. As described above, the column electrode unit 1
8. The operation timing of the row electrode means 24 is shown in FIG.

According to the driving method of the STN liquid crystal described above, the operation of the column signal represented by the equation (34) is performed for m rows (m <m).
N), and the circuit is easy to realize. here,
One operation time (ta in FIG. 10) for 240 rows and 640 columns is obtained. Here, the frame frequency is 60 Hz, m = 8, s
Assuming that = 16, eight rows (m = 8) of data may be read and operated in about 54 ns as in the first embodiment. This is because it is easy to simultaneously read eight rows of data and calculate as shown in the embodiment. On the other hand, in the conventional driving method, ta is also about 100 ns as in the first embodiment. However, during this approximately 100 ns, 2
It is difficult for a logic circuit to read and calculate data for 40 rows. In other words, the processing speed for one row of data is 0.4 ns, and even if the speed is reduced to a speed achievable on a logic circuit by performing parallel driving, the number of parallels increases and the logic scale becomes large. In comparison, in the partial orthogonal function driving, the number of rows of the operation is small, and it can be realized with a small logical scale.

In the embodiment described above, when the display device of N rows is driven in units of R rows by using the orthogonal function of K division as a voltage function, the K division is continuously performed as shown in FIGS. I was doing. Further, the first and second embodiments can also be realized by using the orthogonal function shown in FIG.
The orthogonal function in FIG. 17 gives 0 in the first embodiment, and alternately combines 0 and W0 in the period of W0 in the second embodiment. Although a detailed description of the embodiment in this case will not be given, it is obvious from the description of the first embodiment and the second embodiment that the present invention can be similarly realized. Further, in FIG. 17, 0 and W0 are alternately arranged. However, the present invention is not limited to this.

Next, a third embodiment of the present invention will be described. In the third embodiment, for example, when a display device having N rows is driven by 8 rows of 8 rows by 16 divisions, the 16 divisions are divided into four divisions of W1 to W4 (k of 16 divisions indicated by k1 to k16).
1 to k4 is W1, k5 to k8 is W2, and k9 is k1.
2 is W3 and k13 to k16 are W4).
In this case, only the 16 divisions are dispersed, and at the time when the division is performed, the operation of the eight rows is performed and the applied voltage to the column electrode is calculated. It is obvious that it can be driven with the off voltage.
It should be noted that a known example close to this concept is Japan D.
50 from page 503 of display '92 digest
Although described on page 5, its operation and specific circuit are not described. Hereinafter, the details of the third embodiment will be described with reference to the drawings. FIG. 18 is a block diagram of the liquid crystal display device according to the third embodiment. Reference numeral 35 denotes display data; 36, an H signal as a horizontal synchronization signal; 37, a V signal as a vertical synchronization signal; Synchronized DCLK, 3
Reference numeral 9 denotes a display signal indicating "high" data to be displayed on the display device among the display data 35. The display data 35 includes 640 dots for one line and V in one horizontal time of one cycle of the H signal 36. It is assumed that data for 240 lines is transmitted in one frame time of one cycle of the signal 37. 4
0 is a frame memory control means, 41 is frame write data, 42 is a frame memory control bus for controlling writing and reading of data inputted to the frame memory, 43 is a data signal control bus, and 43 is a frame memory control means. Converts the display data 35 from serial to parallel to generate 4-dot parallel data frame memory write data 41, and further outputs an H signal 36, a V signal 37,
A frame control signal bus 42 and a data signal control bus 43 are generated from the DCLK 38 and the display signal 39. Details of these generated signals will be described later. 44 is a frame memory means, and 45 is frame memory read data. 46
Numeral denotes a column signal generating means, which performs an operation on eight lines of the frame read data 45 to generate liquid crystal data 47 as in the first embodiment. 48 is a column signal control bus, 49
Are function signal buses generated by the column signal generating means 46, respectively. 50 is a row function generating means, 51 is row data,
Reference numeral 52 denotes a row signal bus, and the row function generating means 50 uses the function signal bus 49 to generate row data 51 and a row data control signal bus 52. 53 is a column electrode driving means;
Reference numeral 6 denotes column electrode signals of the first, second, and 640th columns. The liquid crystal data 47 is written to the column electrode driving means 53 by the column signal control bus 48, and the column electrode driving means 53
According to the information of 7, one of the nine voltages is selected and output as a corresponding column electrode signal.

In FIG. 18, nine types of voltages are not shown, but as an example, they can be realized externally by generating a voltage dividing circuit using resistance means and inputting them to the column electrode driving means. . 57 is a row electrode driving means, 58 to 60 are row electrode signals of the first row, the second row, and the 240th row, respectively.
7, the row electrode driving means 57 selects one voltage from three types of voltages in accordance with the written information of the row data 51 and outputs the selected voltage to a corresponding row electrode signal. In FIG. 18, 3
Although the types of voltages are not shown, they are generated externally by a voltage dividing circuit using a resistor as in the case of the column electrode driver 53,
There is an embodiment in which an input is made to the row electrode driving means 57. The operation of the column electrode driving means 53 and the row electrode driving means 57 is the same as that of the TFT liquid crystal driver “HD
It is self-evident that the operation is the same as that of 66310 ″, and that it is easy to realize. Display ON and display OFF are indicated by the voltage effective value of the potential difference at the intersection, Fig. 19 is a timing chart of display data 35 input to the present liquid crystal display device, Fig. 2
0 is a timing chart showing the timing of the frame memory read data 45 read from the frame memory means 44 and the timing of the data control bus 43. In FIG.
The read V signal 81, the read H signal 82, and the read display data 45 are signals of the data control bus 43. FIG. 21 is a block diagram of one embodiment of the frame memory means 44.
62 is a frame memory means A for storing display information of 640 dots × 240 lines for one frame, 63 is a frame memory means B for similarly storing display information for one frame, and 64 is a frame memory means A62. AW reset for instructing an address reset, 65 is an AW clock for performing a write operation on the frame memory means A62, 66 is an AR reset for instructing the frame memory means A62 to read and reset an address, and 67 is an AW reset for instructing a reset of the address. AR clock for performing an operation, 68 is a BW reset for instructing the frame memory means B63 to reset a write address, 69 is a BW clock for performing a write operation to the frame memory means B63, 70 is a read address of the read address to the frame memory means B63. Instruct reset BR reset that, 71 is a BR clock performing reading operation in the frame memory unit B63. Reference numeral 72 denotes a frame memory R / W signal which indicates "high" for writing to the frame memory means A62 and reading from the frame memory means B63, and "low" for reading from the frame memory means A62 and frame memory means B63. Indicates writing to. 73 is a selection means A,
74 is a selection means B, each of which has a frame memory R /
The selection operation is performed according to the W signal 72. 75 is a memory A reset, 76 is a memory A clock, 77 is a memory AR / W
Signal, 78 is a memory B reset, 79 is a memory B clock, 80 is a memory BR / W signal, and the memory A means 62,
The memory B means 63 performs read and write operations in accordance with the respective R / W signals 77 and 80 (a write operation when the R / W signal is "high" and a read operation when the R / W signal is "low"). The read and write addresses of the memory A means 62 and the memory B means 63 are reset to "0" by the reset signals 75 and 78, and thereafter, the clocks 76 and 79 are reset.
It is incremented after the write and read operations of.

FIG. 22 is a timing chart for explaining the operation of the frame memory means 44, and FIG. 23 is a block diagram of one embodiment of the column signal generating means 46 of FIG. In FIG. 23, 85 is a writing means, 86 is A data, 87 is an A control bus, 88 is a line address, 89 is a B control bus, 9
0 is B data, 91 is an AW signal, 92 is a line memory A, and 93 is a line memory B. The writing means 85 outputs the 4-bit parallel frame memory read data 45 as A data 86 and B data 90, and transmits the A control bus 87, line address 88, B control bus 89, and AW signal 91 by the data control signal bus 43. Generate. The write operation is performed on the frame memory read data 4
Line memory A92, line memory B every eight lines of 5
93 alternately, and this is set to “high” by the AW signal 91.
At this time, writing to the line memory A92 is indicated, and when "low", writing to the line memory B93 is indicated. 9
5 is an A read control bus, 96 is a B read control bus, 94
Is reading means, 97 is A read data, 98 is B read data, and reading means 94 is data control bus 4
3, the A read control bus 95 and the B read control bus 9
6 and A read data 97 and B read data 98
The read operation is performed from the line memories A92 and B93. This reading operation is performed by the AW signal 9.
1 to perform reading from a line memory in which a writing operation is not performed. 99 is 8-line data which is read data, and 100 is a read count, which is generated by the reading means 94, respectively. 101
Is a function generating means, and 102 is orthogonal function data. The function generating means 101 generates eight orthogonal functions of division 16 by the read count 100 and the data control bus 43, and outputs them as orthogonal function data 102. Numeral 103 denotes arithmetic means, which calculates the 8-line data 99 and the orthogonal function data 102 and outputs the liquid crystal data 47. The specific calculation method and means will be described later. FIG. 24 is a block diagram of one embodiment focusing on the write operation of the line memory A92 of FIG. 23. Reference numeral 104 denotes an AW reset, and 105 denotes an AW clock, which are signals of the A control bus 87. 106 to 10
Reference numeral 8 denotes a line memory for storing display information for one line, which is a line 1 memory, a line 2 memory, and a line 8 memory, respectively. It should be noted that the memory for lines 3 to 7 is omitted in the figure. Reference numeral 109 denotes a write address decoding means for decoding the line address 88 and instructing which line memory the data is to be written. 110 is a line memory 1 write signal, 111 is a line memory 2 write signal, 1
Reference numeral 12 performs a write operation on the memories which are "high" with the line memory 8 write signal. The write address of each line memory is set to “0” by the AW reset 104, and then the write operation and the address increment are sequentially performed by the AW clock 105.
FIGS. 25 and 26 are diagrams for explaining the write operation to the line memory A92, and FIG. 27 is a block diagram of one embodiment focusing on reading from the line memory A92. This is a signal of the bus 95. Reference numerals 113 to 115 denote line 1 memory 106, line 2 memory 107, and line 8 memory 1, respectively.
08 read data are line memory A1 data, line memory A2 data, and line memory A8 data. In the read operation, the read address is set to “0” by the AR reset 116, and thereafter, by the AR clock 117, 640 dots are read from the line 1 memory 106 to the line 8 memory 108, one by one, simultaneously from the eight lines of memory. FIG. 28 is a timing chart for explaining the reading operation from the line memory A92, and FIG. 29 is a block diagram of one embodiment of the calculating means 103 in FIG. 119 is EX
This is OR, and the exclusive OR of each data of 8-line data 99 of 1-bit data information of 8 lines and orthogonal function data 102 as eight orthogonal functions is calculated. 12
Numeral 0 denotes operation data output from the EXOR 119, reference numeral 121 denotes decoding means for decoding the number of “high” in the operation data 120, and the decoding result is output as liquid crystal data 47.
FIG. 30 is a block diagram of an embodiment of the function generating means 101. Reference numeral 122 denotes an orthogonal function storing means for storing eight kinds of orthogonal function data for 16 divisions. The orthogonal function data 102 as a value is output. Reference numeral 123 denotes a line block counter, and reference numeral 124 denotes a line block signal. The line block case 123 performs a count operation in units of 8 lines with a read H signal 82 based on the read V signal 81, and outputs the count value to the line block signal. Output as 124. FIG. 31 is a diagram for explaining the operation of the function value storage means 122, and FIG.
FIG. 33 is a timing chart for explaining the operation of the column electrode driving means 53. FIG. FIG.
Is a block diagram of one embodiment of the row function generating means 50.
5 is a horizontal clock, 126 is a liquid crystal clock, 128 is a partial count value, and 129 partial clocks, each of which is generated by the column signal generating means 46. Reference numeral 127 denotes a partial counter, which is reset by the horizontal clock 125 and repeats eight counts by the liquid crystal clock 126. The counter 127 outputs the count value as a partial count value 128 and generates a partial clock 129 synchronized with eight counts. 13
0 is a block counter, 131 is a block value, reset by the horizontal clock 125, counted by the partial clock 129, and outputs the count value as the block value 131. 132 is a comparing means, 133 is a comparison output. The line block output 124 is compared with the block value 131, and when they match, the comparison output 133 is set to "high". Reference numeral 134 denotes P → S means for outputting the orthogonal function data 102 of the eight kinds of orthogonal functions, which are inputs, according to the partial cant value 128 one by one. Reference numeral 135 denotes serial orthogonal data output from the P → S unit 134. Reference numeral 136 denotes a selection unit that outputs serial orthogonal data when the comparison output 133 is “high”, and outputs “0” otherwise.

First, the schematic operation of the third embodiment will be described with reference to FIG. 18, and thereafter, with reference to FIG. 19 to FIG.
The detailed operation of each block in the block diagram of the liquid crystal display device will be described.

As input display data 35, data for one screen to be displayed in one frame period is serially transmitted. The frame memory control means 40 converts the display data 35 into 4-bit parallel data and sequentially writes the converted data into the frame memory means 44.

The frame memory control means 40 performs an operation of reading the information of the 4-bit parallel display data 35 stored one frame before from the frame memory means 44 four times in a cycle of 1/4 of the input frame cycle. . The frame memory control means 40 receives the input H signal 36, V signal 37, DCLK 38, display signal 39 from the input signal H, the read V signal 81, the read H signal 82, the read display signal 83, the field signal 84, and the DCLK in accordance with the read timing. The data control bus 43
Is output to the column generating means 46. Field signal 84
Indicates the number of readings four times, from "1" to "4".
Where the first to fourth fields
Called a field. The column signal generating means 46 generates liquid crystal data 47 and a column signal control bus 48 to be output from the data signal control bus 43 and the frame memory read data 45 to the column electrode driving means 53. The column signal generating means 46 fetches the frame read data 45 for eight lines, reads out the fetched eight lines of data one dot at a time, and performs an operation on the read eight lines of data and the orthogonal function data. The liquid crystal data 47 is generated. In this calculation, FIG.
As shown in FIG. 7, the first field is calculated by the orthogonal function of W1, the second field is W2, the third field is W3,
The operation with the orthogonal function of W4 is performed in the fourth field. The row function generating means 50 controls the row electrode driving means 57 so that the orthogonal function of FIG. 17 and the drive voltage of “0” are applied to each row electrode signal. The row function generator 50 generates the row data 51 using the function signal bus 49 in order to synchronize with the orthogonal function of the operation in the column signal generator 46.

Hereinafter, the operation of each block will be described in detail.

FIG. 19 shows the timing of the display data 35 input to FIG. The display data 35 has 240 vertical lines, and data of 240 lines is sent in one frame period (16 ms in this case) of one cycle of the V signal 37.
One line is represented by one cycle of the H signal 36, and during this period, data of 640 dots is sequentially transmitted in a valid period indicated by “high” of the display signal 39. Therefore,
This display data 35 is composed of 640 dots horizontally and 24 pixels vertically.
It is composed of 0 lines. The display data is converted into 4-bit parallel data, written into the frame memory means 44, and read out at a period of 1/4 as shown in FIG. Next, reading of the frame memory means 44,
The write operation will be described. Frame memory means 4
21 can be realized by the configuration shown in FIG. 21. When the frame R / W signal 72 is "high", the selecting means A causes the AW reset 64 to perform writing to the memory means A79 as shown in FIG. , AW clock 65, and outputs them as a memory A reset 75 and a memory A clock 76, and makes the memory AR / W signal "high". As a result, the memory unit A resets the address by the AW reset 64 at the same timing as the V signal 37, and then writes the frame write data 41 during the “high” period of the display signal 39 by the AW clock 65. Here, the AW clock 63 is a clock signal synchronized with the frame write data 41, that is, a clock having a cycle four times as long as the DCLK 38, and a clock output only for data in a period when the display signal 39 is "high". When performing this write operation, the selecting means B 74
A BR reset 70 and a BR clock 71 are selected as the reset 78 and the memory B clock 79, and the memory BR / W
Since the signal is "low", the memory B means 80 performs the reading operation in synchronization with the read V signal having a frequency four times the frequency of the V signal 37, as shown in FIG.
Note that the BR clock 71 is a clock having a cycle of 1/4 of the write clock, that is, a clock having the same cycle as the DCLK 38, since reading is performed at four times the speed of writing. Also, the frame R / W signal 72 is "low".
In this case, the selecting means A73 and the selecting means B74 select the AR reset 66, the AR clock 67, the BW reset 68, and the BW clock 69, respectively, and
The W signal 77 is set to "low", the memory BR / W signal 80 is set to "high", and a read operation is performed for the memory A means 62.
The writing operation is performed on the memory B means 63.

As described above, the operation of the frame memory control means 40 and the frame memory means 44 causes the operation of FIG.
The display data 35 shown in FIG.
, And the data is read out four times with a period of 1/4 as shown in FIG. 20 with a delay of one frame period.
Although not shown in FIG. 20, the frame read data 45 is synchronized with a read clock having the same cycle as the input DCLK 38, and this read clock is included in the data control signal bus 43.

Next, the operation of column signal 46 will be described in detail.

The frame read data 45 is 4-bit parallel data, and is written into the line memory A 92 or the line memory B 93 by the writing means 85.
As shown in FIG. 24, the writing means 85 is counted by the read H signal 82 based on the read V signal 81,
A line address 88 that repeats the values of 1 to 8 is generated, and the AW signal 91 is repeatedly changed to “high” and “low” every eight lines. The AW signal 91 is the frame read data 4
5 is a signal for instructing the line memory for writing 5, and when "high", it instructs writing to the line memory A92, and when "low", it instructs writing to the line memory B.

Now, the AW signal 91 is set to "high" and the write operation to the line memory A92 will be described with reference to FIGS. In FIG. 25, when the AW signal 91 is "high", the write address decoding means 109 uses the value of the write address 88 shown in FIG.
The write operation is sequentially enabled for eight line memories from line 06 to line 8 memory 109. That is, for each line memory, as shown in FIG. 26, the write address is reset by the same AW reset 113 as the read H signal 82, and the clock synchronized with the data during the period when the read display signal 83 is "high" With the AW clock 114, the A data 86 is sequentially written to the line memory line by line. Line memory B93 is also shown in FIG.
It can be realized with the same configuration as described above. However, the line memory B93
When the AW signal 91 is "low", the write address decode means enables each write signal in accordance with the write address 88. Line memory A92 has AW signal 9
When 1 is "low" (when writing to the line memory B93), the reading means 94 performs a reading operation. Hereinafter, this read operation will be described with reference to FIGS. From the line 1 memory 106 to the line 8 memory 108, the read address is reset by the AR reset 116, and then the 1
The dots are read out dot by dot. At this time, the reading means 94 sets the AR reset 116 to the AW signal 9 as shown in FIG.
1 is low four times, that is, the read H signal 82
Are generated every two periods, and the read count 118
Is counted up from 1 to 4. AR reset 116
In one cycle, data of 640 dots is sequentially read out by the AR clock 117 and can be output as A-read data 97 of eight lines of data. This operation is the same for the frame memory B. When the AW signal is “high”, B
The reading means 94 outputs the R clock and the BR reset as a B read control bus, and performs reading. As can be seen from FIG. 26, AW reset 113, AW clock 114
Is output only when the line memory A92 performs a write operation. Similarly, the BW reset and the BW clock are output only when the line memory B93 is writing.

The same applies to the reset and clock for reading. The 8-line data 99 of the read data is input to the arithmetic means 103, and EXOR as shown in FIG.
In step 119, the operation is performed on the orthogonal function data 102, the number of “1” in the output result is decoded, and the result is output as liquid crystal data 47. At this time, the orthogonal function data 102 to be calculated
Is generated by the function generating means 101 shown in FIG. 30, the function storage unit 122 generates the orthogonal function data 102 according to the relationship shown in FIG. 31 according to the field signal 84 and the read count 100. That is, when the field signal 84 is "1", the orthogonal function data of the division times K1 to K4 corresponding to W1 in FIG. 17 is used, and when the field signal 84 is "2", the orthogonal function data of the division times K5 to K8 corresponding to W2 is used. , "3", the division times K9 to K1 corresponding to W3
The orthogonal function data of 2 is generated, and when it is "4", the orthogonal function data of K16 to K16 is generated which corresponds to W4.

As shown in FIG. 32, the line block counter 123 reads the frame read data 45 once by writing it to the line memory and then reading it out.
Delay by line. Therefore, for the read V signal 81, 8
At a timing delayed by the line, 1 to 30 (240 lines are divided into 30 by 8 lines) is counted. That is, the line block signal 124 output from the line block counter 123 indicates a block of lines currently being read from the line memory and calculated by the calculating unit 103 (blocks of 1 to 30 every 8 lines). Will be.

The column signal control bus 48 is connected to the horizontal clock 12
5, a liquid crystal clock 126, each signal is generated by the reading means 94, and the horizontal clock 12
5 is a read H signal 8 having the same cycle as the AR reset 116.
2, the liquid crystal clock 126 has the same period as the read clock, and the OR operation of the AR reset 116 and the BR reset, and the AR clock 11
7 and a BR clock OR operation.

The column signal driving means 53 is connected to the liquid crystal clock 12
6, the liquid crystal data 47 is sequentially latched, and one of nine voltages is selected and output as the column electrode signal based on the information of the liquid crystal data 47 of each dot by the horizontal clock 125 after data latching for 640 dots. . That is, as shown in FIG. 33, the liquid crystal data 47 is converted into a voltage with one cycle delay of the horizontal clock 125, and
Given to one. In the drawing, 1-k1, 1-k2... Are the calculation results of the division times k1, k2,... Of the orthogonal function with respect to the display data of the first block (the first to eighth rows). It is shown that.

Next, the operation of the row function generator 50 will be described. The row function generating means 50 is means for controlling the row electrode driving means 57 so as to output an orthogonal function to the line on which the operation is performed by the column signal generating means 46, and can be realized by the configuration shown in FIG. As shown in FIG. 35, the partial counter 127 is reset by the horizontal clock 125, repeatedly outputs the count operation from 1 to 8 as the partial count value 128 by the liquid crystal clock 126, and outputs the partial count value 128 by the liquid crystal clock 129 having the eight count period. The block counter 130 is counted up. That is, since the row data control bus, which is the control signal of the row electrode driving means 57, is the horizontal clock 135 and the liquid crystal clock 126, the row data 51 other than the same block value 131 as the line block signal 124 is set to "0". Therefore, the comparing means 132 and the selecting means 136 operate, and the line block signal 124
If the block value 131 matches the P → S means 174
, The orthogonal function data 102 used for the operation of the column signal generating means 46 is output as row data 51 bit by bit. As a result, it becomes possible to provide the orthogonal function data only to the row of the calculated block and set the other rows to “0”.

By the operation described above, the calculation for the column electrodes and the application of the voltage to the row electrodes can be controlled, and the liquid crystal can be driven in a manner that the division time is dispersed. In this embodiment, the frame memory is read four times in the writing cycle. However, the present invention is not limited to this, and it is also possible to read x times.

Further, although the number of lines in one block is also eight, it is also possible to use y lines as in the first embodiment.

In the circuit configuration of the third embodiment, a line memory is used for the column signal generating means 46 as shown in FIG. However, the present invention is not limited to this, and can be realized even in a configuration not using a line memory.

This embodiment will be described as a fourth embodiment with reference to FIGS. 35 to 38.

FIG. 35 is a block diagram of a liquid crystal display device according to the fourth embodiment.
Reference numeral 138 denotes frame read data, which controls writing of display data and reading of frame read data 138 with respect to the frame memory means. 139 is a column signal generating means. Other blocks performing the same operations as in the third embodiment are denoted by the same reference numerals as in FIG. FIG. 36 is a timing chart for explaining the read operation from the frame memory means 44, and FIG. 37 is a block diagram of one embodiment of the column signal generating means. In FIG. 37, reference numeral 140 denotes data conversion means for rearranging the data of the frame read data 138. The other blocks are the same as those of the third embodiment shown in FIG. 23 showing the configuration of the column signal generating means 46, and the blocks performing the same operations are denoted by the same reference numerals. FIG.
5 is a timing chart for explaining the operation of the data conversion means 140. FIG.

The operation of the fourth embodiment will be described below with reference to the drawings.

In FIG. 35, input display data 3
5 and the input timing signal are input at the timings shown in FIG. 19 as in the third embodiment. The input display data 35 is written into the frame memory means 44 by the frame memory control means 137. The frame memory control unit 137 outputs an H signal 36, which is an input timing signal,
A signal of the frame memory control bus 42 is created by using the V signal 37, the DCLK 38, and the display signal 39. These operations are the same as in the third embodiment. The display data 35 written in the frame memory means 44 is similarly read out by the frame memory control means 137 and given to the column signal generation means 139 as frame read data 138. The frame memory control unit 137 adjusts the read V signal 81, the read H82, the read display signal 83, the field signal 84,
A reference clock having the same cycle as CLK 38 is generated as data control bus 43. Hereinafter, this read operation will be described. As in the third embodiment, reading is performed from the memory unit A62 or the memory unit B63 in which writing is not performed in the frame memory unit shown in FIG. 21 as shown in FIG. The read operation is performed four times in the cycle of the signal 37. Therefore, the read V signal 8
1 is four periods in one input frame period, and forms the first field to the fourth field indicated by the field signal 84. The read H signal 82 has 30 cycles in one field period, and display data for 8 lines is read from the frame memory means in one cycle. Therefore, the read H signal 8
In the first cycle of the frame read data 138, the data of the first to eighth lines are read in the horizontal direction by 4 bits in the order shown in FIG.
8 is assumed. In the figure, L1, L2,..., L8 indicate data of the first line, the second line,.

As described above, in the fourth embodiment,
Compared with the third embodiment, the operation is the same as that of the third embodiment except that the reading order of the frame read data 138 is changed and the period of the read H signal 82 is accordingly different.

The frame read data 138 is supplied to the column signal generator 139 together with the data signal control bus 43. The column signal generating means 139 can be realized by the configuration shown in FIG.
As shown in FIG. 38, 8 is converted from 8-bit data of 4 bits in the horizontal direction to 8-line data 99 of 8-bit data of 1 bit and 8 lines in the horizontal direction. As shown in FIG. 37, the eight line data 99 is given to the arithmetic means 103 and converted into the liquid crystal data 47. The operation of the calculating means 103 is the same as in the third embodiment.

As described above, the same operation as in the third embodiment can be realized without using a line memory.

In the embodiment described above, the liquid crystal display device is a system which is a display control circuit of an information processing device such as a personal computer, a workstation, a word processor or the like, which generates display data, like a liquid crystal display device 143 shown in FIG. It is often used by being connected to the device display control means 141 by an interface signal 142. FIG. 40 shows the interface signal 142 at this time. This is the input signal used in the first to fourth embodiments, and the V signal 37,
H signal 36, display data 35, display signal 39, DCLK
38. The V signal 37 is a signal indicating a period for transmitting display data of one screen to the liquid crystal display device 143, and one cycle is referred to as one frame. The H signal 36 indicates a period for transmitting one line of display data, and one cycle is referred to as one horizontal period. In the display data 35, the data of one screen is serially displayed one bit at a time according to the above timing.
Send to The DCLK 38 is a clock (not shown) synchronized with the display data. The display signal 39 is the display data 3
5 is a signal indicating data to be displayed on the liquid crystal display device. In FIG. 40, the data which is not displayed, which is called the retrace data, is only horizontal (the display data 35 in FIG. 40).
The data before and after the entry of "1" and the data after the entry of 640 are not limited to this, and there may be cases where there are several lines of retrace data.

However, the interface of the information processing apparatus that realizes the first to fourth embodiments is not limited to this. For example, the frame memory control means, the frame memory Means, column signal generating means, row function generating means, etc.
1, the signal of the interface 142 of the liquid crystal display device 143 can be as shown in FIGS.

FIG. 41 shows the frame memory control means of the third embodiment, and the interface signal 142 when the frame memory means is provided in the system device display control means 141.
FIG. 6 is a timing chart showing an example of the above. This corresponds to the frame read data 45 and the data signal control bus 4 shown in FIG.
3 is a signal. Although not shown, a clock synchronized with the frame read data 45 is required. Further, in FIG. 41, the frame read data 45 is 4-bit parallel, but is not limited to this. The number of parallels can be any serial number from 1 bit to any number of bits. Also, in the case of sending in parallel, in order to simplify the timing design of the processing circuit on the liquid crystal display device side,
It is also conceivable to add a clock having a data period of one dot as an interface signal.

FIG. 42 shows a frame memory control means of the fourth embodiment, and an interface signal 142 when the frame memory means is provided in the system device display control means 141.
FIG. 6 is a timing chart showing an example of the above. This is the signal of the frame read data 138 and the data signal control bus 43 shown in FIG. Although not shown, a clock synchronized with the frame read data 45 is required. Also,
In FIG. 41, the frame read data 45 is in the horizontal direction 4
The bit number is parallel, but is not limited to this. The number of parallel bits can be changed from 1 bit serial to arbitrary plural bits. Also, for reading in the line direction, for example, after transmitting data of the first line by 8 bits,
It is also possible to send 8-bit data in the order of the second and third lines. That is, the feature here is that data of a plurality of lines is alternately transmitted instead of sequentially transmitting one horizontal data. When sending in parallel,
For the purpose of simplifying the timing design of the processing circuit on the liquid crystal display device side, it is conceivable to add a clock having a data period of one dot as an interface signal.

A feature of the interface signals of the above two embodiments is that data of the same screen is transmitted a plurality of times.
The number of times of the field is not limited to four times and other timings.

Further, there is no field signal as compared with the data signal control bus 43 of the third and fourth embodiments, but this can be easily generated from the V signal and the read V signal.

Next, an example of the interface signal 142 when the system device display control means 141 is provided with a column signal generating means and a row function generating means will be described. The interface signals 142 in this case are liquid crystal data 47, column signal control bus 48, row data 51, and row signal bus 52 in FIG. The feature at this time is that the liquid crystal data is the result of the calculation of the display data of a plurality of lines and the orthogonal function applied to the plurality of lines, and that the row electrode driving means not only operates the timing signal but also controls its operation. The line data 51 to be controlled is used as an interface. Further, a configuration in which only the row function generating means is provided in the liquid crystal display device 143 can be considered. At this time, the function signal bus 49 is added to the interface signal 142 instead of the row data 51 and the row signal bus 52. The function signal bus includes, for example, orthogonal function data 102 indicating display data of a plurality of lines and orthogonal function data on which an operation is performed, as described in the third embodiment.
And a line block signal 124 indicating a timing signal, a horizontal clock 125, and a liquid crystal clock 126.
The feature in this case is that the orthogonal function data 10 used in the calculation of the liquid crystal data 47 is used as the interface signal 142.
There are two. Also, the above timing signal is
The present invention is not limited to this. The orthogonal function data 102 can be converted into row data 51 for driving the row electrode driving means 57,
Any timing signal that can generate the row signal bus 52 may be used.

Next, an embodiment in which the functions described in the first to fourth embodiments are provided in the system device display control means 141 will be described with reference to the drawings. FIG. 43 is a block diagram of an example of a conventional system device display control means 141. 144 is a central processing unit CPU, 145 is an address bus, 146 is a data bus, 147 is a display controller, 148 is a display memory bus, 149 is a display memory for storing information to be displayed, 150 is display pallet data, and 151 is display A timing signal bus, 152 is pallet means, and 153 is display data. At this time, the interface signal 142 has the timing shown in FIG. 19 (DCLK is not shown). The CPU 144 instructs a write / read position of the display memory 149 on the address bus via the display controller 147, and writes and reads data via the data bus.
As a result, the CPU 144 can write the screen to be displayed on the display memory or read the screen from the display memory 149. The display controller 147 is a CP
U144 arbitrates the writing and reading operations to and from the display memory 149 and reads from the display memory 149 to send data to be displayed to the display device. Also,
The display controller 147 generates a display timing control signal bus 151. The data read from the display memory 149 of the display controller 147 is
0, and the display data 15
It becomes 3. Normally, the pallet unit 152 converts the pallet data 150 into color information. Here, since the pallet data 150 is a monochrome display, the pallet data 150 is used as the display data 153 as it is.

FIG. 44 shows an embodiment of the system device display control means in the case where the interface signal shown in FIG. 41 is used. The functions of the frame memory control means and the frame memory means described above are used as they are. It has a feature that the capacity of the memory means for storing display information can be reduced to 2/3 as compared with the case where it is provided in the system device.
This will be described with reference to FIGS. 44 to 46.

FIG. 41 shows one of the system device display control means.
FIG. 13 is a block diagram of the embodiment, in which the way of reading the display memory 149 of the display controller 147 is changed from the conventional configuration, and further, a memory means for storing the read data is provided. Reference numeral 154 denotes a buffer unit serving as the storage unit. The previously described frame memory means is shown in FIG.
As shown in FIG. 1, two memory means for storing data for one screen are used, but the buffer means 154 stores data for one screen. 155 is buffer data. FIG. 45 is a block diagram of an embodiment of the buffer means 154. Reference numeral 156 denotes a selection means for switching between the pallet data 150 or stored data. 157 is a buffer memory read / write means, 158 is a data switching signal, 159 is a memory control signal bus, 16
0 is memory data and 161 is memory read data. A memory unit 162 stores display data for one screen. Buffer memory read / write means 157
Generates a memory address and a memory control signal bus 159 which is a signal for writing and reading memory, in order to control writing and reading to the memory means 162 using the display timing control signal bus 151. . FIG. 46 is a timing chart for explaining the pallet data 150.

In FIG. 44, the display controller 147
As shown in FIG. 46, the data of one screen is read from the display memory 149 in the first cycle (first field) of the read V signal having a cycle (one field cycle) of 1/4 of the conventional one frame period. Read it out, make it pallet data 150,
Reading is not performed in the subsequent second to fourth fields. . The read H signal is 26 in one field cycle.
0 period, and the pallet data 150 is stored in the 24th period from the first line to the 249th period of the read H signal.
The data is up to the 0th line. This is shown in FIG.
L1 to L240 are shown. The read display signal is a signal that becomes “high” when the pallet data 150 is the data to be displayed. Further, the pallet data 150 is changed from “1” to “6” in one cycle of the read H signal.
The data of 640 dots indicated by "40" is serial data. Such pallet data 150 is converted into the buffer data 155 in the first field by the selection means 156 shown in FIG. In the field, the data is written to the memory means 162 by the buffer memory read / write means 157. In the second and subsequent fields, the written data is one in one field.
The data for the screen is read from the buffer unit 162 at the same timing as the palette data 150 from the memory unit 162.
The memory read data 1 read by the write means 157
The memory read data 161 becomes the buffer data 155 in the second to fourth fields. Therefore, buffer data 1
55 is the display data 153 via the pallet means 152.
And becomes the same as the frame read data shown in FIG. The buffer memory read / write means 157 uses the display timing control signal bus 151 to generate various control signals, which will not be described in detail here.
It is obvious that it can be easily generated from the timing signal No. 6 and the dot clock serving as the reference signal of the pallet data.

In this embodiment, the display controller 147
Is divided into a plurality of field periods in which one frame of data is conventionally read out, and display data is read out from the display memory 149 in one of the field periods, and this is used as the display data 153 as it is. At the same time, the data is stored in the memory means 162, and in the remaining fields, the data stored in the memory means 162 is read for one screen for one screen, and is used as display data 153. This allows
Compared with the embodiment described above, the capacity of the memory means 162 can be set to one screen. FIG. 48 shows an example using this embodiment.
In order to explain reading from the display memory 149 of the display controller 147 when the interface signal shown in FIG. 42 is used, the timing of the pallet data 150 is shown. The display controller 147 operates as shown in FIG.
As shown in (1), data for one screen is read out in the first field, and becomes pallet data 150. Pallet data 150 is data of one screen in 30 cycles of read H signal,
Eight lines are read out in one cycle. Therefore, LL1 in FIG.
Then, the first through eighth lines, the LL2 through the ninth through sixteenth lines, and the LL30 with the second through 233th lines
The data for eight lines in the fortieth line is read out. In FIG. 47, eight lines are read out one dot at a time in one cycle of the read H signal, and this is repeated (L1, L in the figure).
.., L8 indicate the first line, the second line,..., The eighth line, and “1” to “640” indicate the first dot to the 640th dot).

[0137]

According to the method of driving the STN liquid crystal described above, the calculation of the column signal shown in the equation (27) is performed for N rows in the conventional example, but is performed for R rows (R <N). And it is easy to realize in terms of circuit. Where 240 lines, 640
One operation time (ta in FIG. 10) of the column is obtained. Here, the frame frequency is 60 Hz, R = 8, and K = 16.

[0138]

[Equation 36]

That is, eight rows (R =
8) It is sufficient to read the data for the minute and perform the calculation. this is,
As shown in the embodiment, it is easy to simultaneously read out eight rows of data and perform calculations. On the other hand, in the conventional driving method, ta is as follows.

[0140]

(37)

[0141] ta itself becomes longer as compared with the partial orthogonal function drive. However, it is difficult for a logic circuit to read out and calculate 240 rows of data in about 100 ns.

That is, the processing speed for one row of data is 0.4 ns. Even if the speed is reduced to a speed achievable on a logic circuit by performing parallel driving, the number of parallels increases and the logic scale becomes large. In comparison, in the partial orthogonal function driving, the number of rows of the operation is small, and it can be realized with a small logical scale.

Further, by dividing the division of the partial orthogonal driving in the time direction, the period of applying the voltage during the selection period (a period during which the voltage indicated by the orthogonal function for the partial orthogonal driving is applied to the row electrodes) is shortened. Thus, it is possible to prevent a decrease in display luminance during a non-selection period (a period during which the voltage indicated by the orthogonal function for partial orthogonal driving is not applied to the row electrodes).

Conventionally, the display control means of the system device is provided with a storage means for storing display data in addition to a display memory for storing data to be displayed, and an orthogonal function generating means, thereby simplifying the functions of the display device. can do.

Further, by reading the display data of the display controller of the display control means by reading one screen of data from the display memory in one field of each field divided into a plurality of fields, The storage capacity of the storage means can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a liquid crystal display device of the present invention;

FIG. 2 is a liquid crystal display section having a matrix structure of N columns and M rows;

FIG. 3 is a diagram showing an example of an orthogonal function applied to a row electrode generally used as a drive waveform of an STN liquid crystal at present;

FIG. 4 is a diagram showing a liquid crystal drive voltage waveform applied to a dot U (i, j).

FIG. 5 is a diagram showing an example of division = 8 in an orthogonal function called a Walsh function;

FIG. 6 shows a case in which a Walsh function is applied to only eight rows as voltage functions applied to N row electrodes, a frame period T is 2N (N is the number of display rows), and the Walsh functions of the eight rows are driven by division = 16. Diagram showing the voltage function of the row electrode of

FIG. 7 is a block diagram of one embodiment of a column signal generating means;

FIG. 8 is a diagram showing dot information of the liquid crystal panel when the liquid crystal panel 28 has four rows and four columns in the embodiment.

FIG. 9 shows each t of the X-row function data 13 of the function generator 12
FIG.

FIG. 10 shows X row read data 10 and X row function data 1
3 is a diagram for explaining the timing relationship of FIG.

FIG. 11 is a block diagram of an embodiment of a calculating means 11,

FIG. 12 illustrates an operation of the decoding circuit 33.

FIG. 13 shows function data 2 output by the row function generating means 12
3 is a diagram showing the value of each t of 3,

FIG. 14 is a timing chart for explaining the operation of the column electrode driving means 18 and the row driving means 24;

FIG. 15 is a block diagram of a second embodiment of the liquid crystal display device of the present invention;

FIG. 16 is a diagram showing a Walsh function for a voltage function applied to N row electrodes for only eight rows, a frame period T of 2N (N is the number of display rows) in the second embodiment, FIG. 7 is a diagram showing a voltage function of a row electrode in the case of driving by dividing = 16;

FIG. 17 is a diagram showing a voltage function of a row electrode with W0 being W0 and 0 for the second embodiment of FIG. 16;

FIG. 18 is a block diagram of a liquid crystal display device according to a third embodiment,

FIG. 19 is a timing chart of display data 35 input to the liquid crystal display device;

20 shows frame memory read data 45 and data control bus 43 read from frame memory means 44. FIG.
Diagram showing the timing of

FIG. 21 is a block diagram showing one embodiment of a frame memory means 44;

FIG. 22 is a timing chart for explaining the operation of the frame memory means 44;

FIG. 23 is a block diagram of a column signal generator 46;

24 is a view for explaining a write operation of the line memory A92 of FIG. 23;

FIG. 25 is a block diagram focusing on a write operation of the line memory A92 of FIG. 23;

FIG. 26 is a diagram illustrating a write operation of the line memory A92 of FIG. 23;

FIG. 27 is a block diagram focusing on a read operation of the line memory A92 of FIG. 23;

FIG. 28 is a view for explaining a read operation of the line memory A92 of FIG. 23;

FIG. 29 is a block diagram of a calculation means 103;

FIG. 30 is a block diagram of a function generator 101;

FIG. 31 is a view for explaining the operation of the function value storage means 122;

FIG. 32 is a timing chart for explaining the operation of the line block counter 123;

FIG. 33 is a timing chart for explaining the operation of the column electrode driving means 53;

FIG. 34 is a block diagram of a row function generator 50.

FIG. 35 is a block diagram of a liquid crystal display device according to a fourth embodiment;

FIG. 36 is a timing chart for explaining a read operation from the frame memory means 44;

FIG. 37 is a block diagram of one embodiment of a column signal generating means.

FIG. 38 is a timing chart for explaining the operation of the data conversion means 140;

39 is a block diagram illustrating an interface between the display control device 141 of the system device and the liquid crystal display device 143.

FIG. 40 is a diagram showing an example representing the timing of an interface signal 142;

FIG. 41 is a timing chart showing an example of an interface signal 142 when the frame memory control means of the third embodiment is provided in the system device display control means 141;

FIG. 42 is a timing chart showing an example of an interface signal 142 when the frame memory control means of the fourth embodiment is provided in the system device display control means 141;

FIG. 43 is a block diagram showing an example of a display control means 141 of a conventional system device.

FIG. 44 is a block diagram as one embodiment of a system device display control means 141 when the interface signal shown in FIG. 41 is used;

FIG. 45 is a block diagram of one embodiment of a buffer means 154;

FIG. 46 is a timing chart for explaining the pallet data 150 of FIG. 44;

FIG. 47 shows a display memory 149 of the display controller 147 when the interface signal shown in FIG. 42 is used.
Palette data 150 for explaining reading from
FIG.

[Explanation of symbols]

1 display data, 2 writing means, 3 A data, 4
... B data, 5 ... Line memory A, 6 ... Line memory B, 7 ... Read data A, 8 ... Read data B, 9
... Reading means, 10 ... X row display data, 11 ... Calculation means, 12 ... Function generation means, 13 ... X row function data, 14
... Calculation data, 15 ... Voltage conversion means, 16 ... Analog display data, 17 ... Column signal generation means, 18 ... Column electrode drive means, 19-21 ... One row electrode signal and two row electrode signals for column electrode signals, respectively. , M column electrode signals, 22... Row function generating means, 23... Row function data, 24.
25 to 27... Row electrode signals, one row electrode signal, two row electrode signal, N row electrode signal, 28... Liquid crystal panel for displaying N rows and M columns, 29, 30.
XOR circuit, 33 decoding circuit, 34 row function generating means 35 display data, 36 H signal, 37 V signal, 3
8 DCLK, 39 display signal, 40 frame memory control means, 41 frame write data, 42 frame memory control bus, 43 data signal control bus, 44
Frame memory means, 45 ... frame memory read data, 46 ... column signal generating means, 47 ... liquid crystal data, 48 ...
Column signal control bus, 49 function signal bus, 50 row function generating means, 51 row data, 52 row signal bus, 53 column electrode driving means, 54 first column electrode signal, 55 second column Column electrode signal, 56: 640th column electrode signal, 57: row electrode drive means, 58: first row electrode signal, 59: second row electrode signal, 60: 240 row electrode signal, 61: liquid crystal Display device, 62: Frame memory means A, 63: Frame memory means B, 64: AW reset, 65: AW clock, 66: AR reset, 67: AR clock, 68:
BW reset, 69 ... BW clock, 70 ... BR reset, 71 ... BR clock, 72 ... Frame memory R / W
Signal, 73 ... selecting means A, 74 ... selecting means B,
75: memory A reset, 76: memory A clock, 7
7: memory AR / W signal, 78: memory B reset, 7
9: memory B clock, 80: memory BR / W signal, 8
1 Lead V signal, 82 Lead H signal, 83 Lead display signal, 84 Field signal 85 Writing means,
86 A data, 87 A control bus, 88 line address, 89 B control bus, 90 B data, 91 AW
Signal, 92: line memory A, 93: line memory B,
94 ... Reading means, 95 ... A read control bus, 96 ...
B read control bus, 97 A read data, 98 B read data, 99 8 line data, 100 read count, 101 function generating means, 102 orthogonal function data, 103 arithmetic means, 104 AW reset, 105
... AW clock, 106 ... Line 1 memory, 107 ... Line 2 memory, 108 ... Line 8 memory, 109 ... Write address decoding means, 110 ... Line memory 1 write signal, 111 ... Line memory 2 write signal, 112 ...
Line memory 8 write signal, 113 ... line memory 1 read data, 114 ... line memory 2 read data, 1
15: line memory 8 read data, 116: AR reset, 117: AR clock, 118: read count, 119: EXOR, 120: operation data, 121 ...
Decoding means, 122 ... orthogonal function storage means, 123 ... line block counter, 124 ... line block signal,
125 horizontal clock, 126 liquid crystal clock, 127
... partial counter, 128 ... partial count value, 129 ... partial clock, 130 ... block counter, 131 ... block value, 132 ... comparing means, 133 ... comparison output, 134
... P → S means, 135… Serial orthogonal data, 136…
Selection means, 137 ... frame memory control means, 13
8: frame memory read data, 139: column signal generation means, 140: data conversion means, 141: system device display control means, 142: interface signal, 143
... Liquid crystal display device, 144 ... CPU, 145 ... Address bus, 146 ... Data bus, 147 ... Display controller,
148 display memory bus 149 display memory 150
... pallet data, 151 ... display timing signal bus,
152 ... pallet means, 153 ... display data, 154 ...
Buffer means, 155 buffer data, 156 selection means, 157 buffer memory read / write means, 1
58: data switching signal; 159: memory control signal bus; 160: memory data; 161: memory read data. 162: Memory means for storing display data for one screen.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeyuki Nishitani 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. 7-1-1, Hitachi Research Laboratory, Hitachi Research Laboratory

Claims (10)

[Claims] 1. A column electrode driving means for generating a voltage value according to display data, a row electrode driving means for generating a row electrode voltage, a voltage waveform output from the column electrode driving means, and an output from the row electrode driving means. In a matrix type display device in which display is turned on or off based on a voltage effective value of a voltage difference of a voltage waveform, display data given to a column electrode driving means is expressed by the following equation. Column signal generating means for converting display data so as to attain the voltage indicated by.
A voltage waveform according to an orthogonal function having a value of 1 or −1 is applied to each of the divided row electrodes only in a K period obtained by dividing one frame into T, and a voltage according to another function is applied during the remaining period. A matrix type display device comprising a row function generating means for instructing the row electrode driving means to be applied. 2. The matrix type display device according to claim 1, wherein said other function is a function F of a K period having a value of +1 or -1.
a, the matrix type display device being orthogonal to the orthogonal function. 3. The matrix type display device according to claim 1, wherein said other function is a function of a K period, and its value is "
A matrix-type display device, wherein the function is F0 of 0 ”. 4. The matrix-type display device according to claim 1, wherein said other function is an arbitrary combination of said Fa function and said F0 function. 5. The matrix type display device according to claim 1, wherein the column signal generating device comprises a memory means for storing display data for X rows, a writing means for writing the display data into the memory means, and a display means for displaying the data from the memory means. A reading means for reading data, an X-row function generating means for generating an orthogonal function having a value of 1 or -1 for the K period, an output of the X-row function generating means, and data read from the memory means. And a voltage conversion means for converting an output of the calculation means into a voltage. 6. The matrix type display device according to claim 5, wherein said calculating means is: And the voltage generating means: A matrix type display device, wherein the conversion is performed so as to obtain a voltage value. 7. The matrix type display device according to claim 1, further comprising: frame memory means for storing display data.
A method of driving a matrix-type display device, wherein display data is read from the frame memory means at a period S times as long as an input, and T-divided periods are given by dispersing S in one frame. 8. A display control means of a system device, a display device, and an information processing apparatus in which the display control means and the display device are connected by an interface signal group, the display data of the interface signal group is the same S times. An information processing apparatus characterized in that the information is data for one screen. 9. The information processing apparatus according to claim 8, wherein said display control means includes a display controller, a display memory for storing display data for one screen, and one display read from said display memory.
The display controller reads out one screen of memory data from the display memory and uses it as display data to be sent to the display device. The memory data is stored in the buffer memory. After the display controller has read the memory data for one screen, the data read for one screen from the buffer memory is used as display data S-1 times. Display control means of the device. 10. In an information processing apparatus in which a display control means and a display device of a system device and the display control means and the display device are connected by an interface signal group, display data of the interface signal group is equivalent to one screen. An information processing device, wherein after sending data to a display device, the data becomes invalid data that is not displayed S-1 times.