JP2001013922A - Addressing method of memory effect display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to eliminate electric charges as completely as possible while eliminating them, by applying a semi-selective signal to different electrodes at the same time during a part of a cycle period of a selective signal. SOLUTION: A sustained signal applied to a row YA contains waveforms having a low level voltage V1 of the duration T1 and a following high level voltage V2 of the duration T2. A semiconductive elimination signal contains a signal impressed for the duration of the high level voltage T2, namely, for the same cycle time as that for receiving a selective write signal. This semi- selective elimination signal has an ascending slope starting with a voltage V3 slightly higher than an intermediate voltage V and rising up to the high level voltage V2. For the time T2 corresponding to also a selective address time, a row driving device sends sleeted row pulses IS1, IS2, etc., as shown by VX. The signal obtained during an elimination period is a series of uneven short elimination pulses I'S1, I'S2, etc., having the amplitudes controlled by the slope r.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory effect type display panel, and more particularly, to an addressing method for an AC type plasma display panel.

[0002]

2. Description of the Related Art In the following description, a plasma display panel is referred to as P
Abbreviated DP, this panel is a flat panel display screen that uses the emission of radiation obtained from a discharge gas in the visible or ultraviolet spectrum. PDP is DC type P
They can be broadly classified into two types: DP and AC type PDPs.

[0003] AC PDPs, during their operation, benefit from an effect called the memory effect because of their specific structure, which makes AC PDPs for professional use and high definition color television. It is particularly suitable for forming large screens with a large number of basic cells for both commercial applications such as

The present invention relates to this type of PDP.

There are many types of AC type PDPs.
One of them is a so-called matrix-type PDP that has only two arrays of crossed electrodes that define cells and address and activate each cell. This PDP
Are especially disclosed in French Patent No. 2,417,848. Another type of AC-type PDP has an array of two so-called sustaining electrodes on a first tile and an array of electrodes on a second tile, the array of electrodes being associated with one sustaining electrode. This is a so-called coplanar PDP in which address electrodes are defined and cells are defined at intersections of two arrays. This type of PDP is particularly well known in European Patent Application 0,1.
No. 35,382.

The operation of an AC type or memory effect type PDP is as follows.
Generally, it has an addressing function and a persistence function for generating light energy. The sustain function applies a substantially square wave alternating sustain signal to the set of electrodes, typically all rows of the panel, for the purpose of maintaining the state of each cell previously specified by the address signal. This sustain signal generates a sustain discharge in the cell in the address state.

Addressing is typically performed by scanning the panel line by line. The cells in the selected row are
Driven simultaneously by a semi-selective operation, eg, an erase operation, followed by a selective operation during which cells in a row may be written. The semi-selective operation following the selective operation is realized by a time shift from one row to another. Further, as is known, the semi-selective operation may be a write operation and the selective operation may be an erase operation.

In an AC plasma display panel, the discharge current is limited by a capacitor connected in series with each cell so that the display panel is not destroyed when the source is not current limited. Capacitors are commonly created by covering an electrode array with a dielectric layer, eg, borosilicate glass.

[0009] Erasing a cell therefore removes the charge stored in the dielectric within the cell of the row of interest. To erase, a voltage is applied to the electrodes that form the row of interest, and the intensity of the discharge induced by this voltage is such that the charges stored at locations facing the electrodes combine to cancel each other out Is chosen as Erasing the cell creates a discharge current whose intensity is approximately equal to half the intensity of the sustained current, since about half of the normal sustained charge is transferred.

At the present time, selective erase operations are performed in various ways.

According to one embodiment, referred to as "shuffling", a matrix AC PDP receives an address signal of the type shown in dashed lines in FIG. 1, and the signal shown in solid lines represents the voltage of the gas discharge. In this case, all the row electrodes simultaneously receive the sustained signal indicated by the dashed line. This signal Vref has the upper limit level of the potential V2 and the potential V1.
, Which are on either side of the central potential V0 where a central level (not shown in this embodiment) may be formed in some cases. The threshold level is separated by a rising edge and a falling edge. The sustain signal Vref causes a sustained discharge in the cell in the write state. In the embodiment shown, the address signal superimposed on the persistence signal is applied to each electrode in turn for one electrode of the array. For example, an address signal can be applied to a row electrode. However, it is possible that the address signal is applied to a column.
The address signal is decomposed into a semi-selective signal and a selective signal. The semi-selective signal is, for example, an erase signal, and the selective signal is a write signal. However,
As is known to those skilled in the art, the semi-selective signal and the selective signal may be reversed.

As shown in FIG. 1, the selective write signal includes a pulse IE superimposed on the high level of the sustain signal. The semi-selective erase signal includes an erase pulse IR generated from a low level of the sustain signal. The erase pulse IR causes an erase discharge to occur in all cells in the selected row in the written state, replacing the pulse to be generated by the sustain signal. The erase pulse IR may last until the next rising edge of the sustain signal or may be shorter. In the case of a matrix type AC color PDP, it is common to apply several write pulses superimposed on the high level of the sustain signal.

[0013]

With this type of addressing, referred to as "multi-pulse" addressing, the high level duration must be long enough, i.e., low so that the address cycle time is not extended. It means shortening the duration of a level. This shortens the erasing time because the erasing pulse is generated from a low level at the present time. However, if the erasing time is too short, the charges accumulated in the terminals of the dielectric are not completely removed.

The present invention overcomes the above-mentioned drawbacks, thereby making it possible to remove charges as completely as possible during erasing for both matrix type and coplanar type AC plasma display panels. The purpose of the present invention is to provide an addressing method.

[0015]

The technical contents of the present invention are as follows.
"Write" defined at the intersection of the array of crossed electrodes
In a memory effect type display panel having a cell including two states, a state and an "erase" state, a sustaining signal for generating a sustained discharge in a cell in a writing state is applied to all cells over a given cycle time, and a half cycle is applied. An addressing method for sequentially applying a selective signal and an address signal having the selective signal to an array of electrodes, wherein the semi-selective signal is applied for at least a portion of a cycle time of the selective signal. It is characterized by being applied simultaneously to different electrodes.

According to one embodiment, which shows addressing while displaying, here the sustaining signal is a square wave signal having at least two limit levels on either side of the central potential, and the semi-selective signal is a selective signal. The signal is applied to at least a portion of the limit level of the applied sustained signal. The semi-selective signal is applied during a high or low level of a square wave sustain signal and includes a signal portion having a rising slope and a falling slope, wherein the signal portion is between a central potential and a potential at a critical level. Starting at an intermediate potential and ending at a critical level. In this case, since the pulses of the multi-pulse selective signal are superimposed on the semi-selective signal, for example, the slope of the erase signal, a continuous short erase pulse is obtained, and the amplitude is controlled based on this slope. You. As a result, the cell receives a continuous discharge including a gradually changing voltage. This feature, which is associated with a long discharge time, allows the cell to be almost completely erased, for example for any structural uniformity of the cell.

[0017] Preferably, the pulses associated with the selective signal are adjustable with respect to width, and these pulses are typically about 1.5 µs but from 0.5 µs to 10 µs
It has a fixed or variable width that varies between less than, and the spacing is also adjustable in the order of this magnitude.

According to another feature of the embodiment, the semi-selective signal is applied during the upper or lower level of the sustained signal. This signal has the waveform of a semi-selective address signal disclosed in French Patent Application No. 96/01060 filed by THOMSON-CSF, the content of which is incorporated herein by reference.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS Further features and advantages of the present invention are:
BRIEF DESCRIPTION OF THE DRAWINGS The invention will become apparent from reading the various embodiments described below with reference to the accompanying drawings.

A first embodiment of an image display device to which the method of the present invention is applied will be described with reference to FIG. This display device is a matrix type plasma display panel or PDP1.
And means for driving the panel.

Matrix type plasma display panel PDP1
Has a first array of row electrodes Y1 to Y4, which intersects a second array of column electrodes X1 to X5.
The plasma cells C correspond to the intersections of the respective electrodes, and these cells are arranged in a matrix. In a matrix type PDP, a sustain signal and an address signal are applied between a row electrode array and a column electrode array.

Accordingly, as shown in FIG. 2, each of the row electrodes Y1 to Y4 is connected to a row address circuit or a row driving device RD. For large panels, there are typically a plurality of row drivers, each supplying a sustain signal and an address signal to a group of rows. Similarly, each of the column electrodes X1 to X5 is connected to a column address circuit or a column driving device CD. The column drive is
Generate a pulse that masks the pulse generated by the semi-selective write address signal on the row selected in cell C, where the row selected in cell C
It may not be written as described below.

As shown in FIG. 2, the row driving device RD
Receives the persistent signal from the persistent signal generator SSG.
This duration signal has two threshold voltage levels V1 each having a low level duration T1 and a high level duration T2.
, And V2, the time T1 is shorter than the time T2 in this embodiment. The row driver RD receives the address signal superimposed on the sustain signal from the row address signal generator RASG.

In the embodiment shown in FIG. 2, the operation of the row driver RD is such that the switches I1, I2, I3 and I4 can be switched between a line RSS supplying the sustain signal and a line RAS supplying the address signal. Indicated by The state of the switch is controlled by a signal SC coming from a scan generator (not shown). In FIG. 2, the switches I1, I2 and I4 are switched to the position receiving the signal RSS, so that the rows Y1, Y2 and Y4 are in the sustained mode. On the other hand, switch I3 is switched to receive an address signal RAS formed from selective and semi-selective signals, such that row Y3 is the addressed row.

As shown in FIG. 2, the column drive CD also includes switches I'1, I'2, I'3, I'4, and I'5. These switches are connected to the column address signal generator C
Receive the address signal CAS coming from the ASG, or
It may be grounded as indicated by line M. The states of switches I'1 through I'5 are controlled by a signal V corresponding to the video content of the addressed row. In the illustrated embodiment, switches I'1, I'2 and I '
5 is grounded so that the cell at the intersection between row Y3 and columns X1, X2 and X5 is in the "ON" state as indicated by the symbol "*", and switches I'3 and I'4 are , Row Y
Cell C at the intersection between column 3 and columns X3 and X4 is connected to receive column address signal CAS from column address signal generator CASG so as to be in the "off" state as indicated by the symbol "0". You. Cells in other rows are in a persistent state as indicated by the symbol "S".

A matrix type PDP as shown in FIG.
The waveforms of the address and persistence signals according to the present invention applied to FIG. 3 will be described with reference to FIGS. 3A and 3B. The addressing described with reference to FIGS. 3a and 3b results in a "multi-pulse" address. However, it is clear to a person skilled in the art that the present invention can be applied to a single pulse address. In this case, the applied duration signal on the line Y _A is the duration of the low level voltage V1 T2 and comprises a square wave having a duration T2 of the high level voltage V2 subsequently. The sustained signal shown does not have a median level at the average voltage V0, but the present invention relates to a sustained signal having this median level, as disclosed in patent application No. 96/01060 filed by THOMSON-CSF. Can also be applied. In a known manner, an address signal can be superimposed on this persistence signal, wherein the address signal is a semi-selective signal, in this embodiment an erase signal, and a selective signal, in this embodiment a write signal. It is a type including.

According to the present invention, the semi-selective erase signal is:
Includes signals applied during the high level of the persistence signal, ie, during period T2, ie, during the same cycle time as receiving the selective write signal.

As shown in FIG. 3a, this semi-selective erase signal includes a rising ramp r, starting from a voltage V3 slightly higher than the intermediate voltage V and rising to a high level voltage V2.

[0029] As shown in Figure 3a, during the time corresponding to selective addressing time T2, as shown in V _X, column pulse IS1 to row driver CD is selected, IS
Send 2 etc. Therefore, the signal _Y A -V _X shown in FIG. 3b in a matrix type PDP is obtained at the terminals of the addressed cell. The signal obtained during the erasure period is
Irregular short erase pulse I'S having an amplitude controlled by slope r, rather than a continuous slope
1, continuous I'S2, etc. Thus, the cells are treated by continuously discharging at gradually changing voltages. This type of erase discharge is also possible for the structural uniformity of the various cells, and lasts long enough for the discharge to stabilize before the next sustaining pulse.

FIG. 3b shows that after the erasing period P, a plurality of pulse writing periods P 'of known type are obtained. The pulses I'S1 and I'S2 are shown with a fixed width. However, those skilled in the art will recognize that the pulse may vary in width, typically 1.5 μs, but in particular from 0.5 μs to 10 μs.
It is clear that it can have a width that varies between less than μs. In addition, the spacing between the pulses can be adjusted in the same order of magnitude.

FIG. 4 shows another embodiment according to the invention, in which the long erasure described above is supplemented by a short erasure pulse during the duration T1 of the sustain pulse, which erasure pulse is National Patent Application No. 96/01060 (THOMSON-CS
F) of the type disclosed.

In the embodiment shown in FIG. 4, the semi-selective address signal in the erase mode includes a signal portion V 'whose slope decreases above the low level V1 of the sustain signal, which signal portion V' It is between the low level potential V1 and the center potential V0, starts at an intermediate potential V4 with respect to the low level potential V1, and ends near the low level potential V1. This conventional erase signal is followed by a semi-selective address signal in an erase mode of the type described with reference to FIGS. 3a and 3b. It will be apparent to those skilled in the art that a semi-selective address signal in the erase mode may be provided with other waveforms as disclosed in the above-referenced patent application.

Another embodiment of the present invention, particularly applicable to a coplanar plasma display panel, is described with reference to FIGS.

As shown in FIG. 5, a coplanar PD
P is two parallel arrays of electrodes Ys1... YsN and Y's1... Y 'of electrodes called row electrodes that intersect a second array of electrodes X'1 to X'N called column electrodes. It has a screen formed from the set of sN. The cell Ce bounded by the barrier B corresponds to each intersection of a row electrode and a column electrode. In the case of a coplanar PDP, two parallel arrays of row electrodes consist of sustaining electrodes, between which sustaining signals are applied and address signals are applied between one row and column electrode array. Applied.

As shown in FIG. 6, according to the present invention,
The arrays of sustained electrodes Ys1 to YsN receive a low level square wave pulse of duration T′1, followed by a high level 2 of duration T′2 corresponding to the time required for the selective write operation; Thereafter, a pulse of the duration T'3 follows, and the level becomes low again in the duration T'1. The combination of durations T'1, T'2 and T'3 corresponds to a base cycle.

According to the present invention, as indicated by Y's in FIG. 6, the second array of sustaining electrodes Y's1 to Y'sN receives an address pulse which has a duration T '. During the first high level of s, the duration T ', which is slightly shorter than T's but for which the erase signal is normally applied
It has an erase signal Ve of a duration lasting longer than one. Between two parallel arrays Y's to Ys and Y's1 to Y'sN of the row electrodes, the signals shown as Y's-Ys in FIG. 6 are obtained. During a period T's different from the base cycle, a selective write signal is applied and a pulse Ie is applied.
give. The electrode array X 'is a pulse I
S′1... IS′n are received.

Thus, with the present invention, the duration T'1 is used because the duration is no longer used to erase.
Can be significantly reduced compared to conventional durations. As a result, the base cycle is also shortened.

In fact, the generation of a signal enabling the present invention to be realized is performed, particularly in a matrix type AC plasma display panel, in which the voltage value of the semi-selective erase signal is the reciprocal of the voltage value of the selective write signal. There are restrictions due to the existence. This requires a high voltage drive that operates at both positive and negative voltages. One solution that allows the present invention to be easily implemented is to use one amplifier per driver circuit and incorporate a semi-selective erase signal into the sustain signal. A similar type of constraint
The same applies to coplanar plasma display panels.

[Brief description of the drawings]

FIG. 1 is a timing chart of an address signal and a sustain signal applied to a row of a conventional MAC PDP type plasma display panel.

FIG. 2 shows a MA to which the first embodiment of the method of the present invention is applied.
1 is a schematic view of a structure of a plasma display panel of a C PDP type.

FIG. 3 is a timing chart of an address signal and a sustain signal according to the present invention applied to the PDP of FIG. 2;

FIG. 4 is a timing chart of an address signal and a sustain signal according to a modification of the present invention.

FIG. 5 shows a coplanar PD to which the method of the present invention can be applied.
FIG.

FIG. 6 is a timing chart of an address signal and a sustain signal applied to the electrodes of the PDP of FIG. 5 according to the present invention;

Claims (9)

[Claims] 1. A memory effect display panel having a cell defined at the intersection of an array of intersecting electrodes and having two states, a "write" state and an "erase" state.
A sustaining signal for generating a sustained discharge in the cell in the written state is applied to all the cells over a given cycle time, and an address signal having a semi-selective signal and a selective signal is applied to one of the electrodes. The method of addressing, wherein the semi-selective signals are applied simultaneously to different electrodes during at least a portion of a cycle time of the selective signals. 2. When addressing while displaying,
The persistent signal comprises a square wave having at least two threshold levels on either side of a central potential, and the semi-selective signal is applied to at least a portion of the limit level of the continuous signal to which the selective signal is applied. The method of claim 1, wherein: 3. The method of claim 2, wherein said semi-selective signal is applied during a high level or a low level of said square wave duration signal. 4. The semi-selective signal includes a signal portion having a rising slope, the signal portion starting at an intermediate potential between the central potential and the limit level potential and ending at the limit level. The method according to claim 2 or 3, wherein: 5. The method according to claim 1, wherein the semi-selective signal obtained in the cell forms a continuous pulse of varying amplitude. . 6. The pulse according to claim 1, wherein the pulse is about 0.5 μs to 10 μs.
The method of claim 5 having a width that varies between less than. 7. The method according to claim 1, wherein an additional optional signal is applied during said other limit level of said sustained signal. 8. The method according to claim 1, wherein the method is applied to a matrix type AC plasma display panel. 9. The method according to claim 1, wherein the method is applied to a coplanar AC plasma display panel.