JP2001007302A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce leakage current in the diffused layer of a memory cell. SOLUTION: A diffused layer 2 in a memory cell is an n-type semiconductor memory, and the memory cell has an n-type region 4. The region 4 is one formed directly under a p-type well 3 under at least an element isolation oxide film and the concentration in the region 4 is set higher than that in the layer 2. This region 4 is turned into a gettering layer, and a leakage current in the memory cell is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a semiconductor memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art A DRAM is a memory having a mechanism for storing data on the principle of storing electric charge in a capacitance generated due to the structure of a MOS transistor. In a DRAM, as the degree of integration increases, it becomes difficult to maintain the data retention time.

[0005] The data retention time of a DRAM is mainly determined by the np junction of the capacitor contact portion. One of the factors that increase the junction leakage is a heavy metal contamination element.

[0004] Heavy metal contaminants such as Fe, Ni, Cu, etc., form a solid solution in Si to form a deep level,
In addition, when the solid solubility is exceeded, there is a problem that it precipitates as silicide and deteriorates bonding characteristics.

[0005] In general, heavy metal contaminants are mixed in LSI manufacturing equipment and materials used in LSI manufacturing. Therefore, these production equipment and materials should be thoroughly cleaned. However, since the cost required to maintain a stable cleanness is enormous, a gettering technique is generally used to compensate for this.

[0006] The gettering technique recognizes the presence of some heavy metal contaminant elements in Si and, as far as possible, from the operating region of the device (for example, the region where the aforementioned np junction is formed). This technology removes heavy metal contaminants.

[0007] The removed heavy metal contaminating element is captured by a gettering site provided beforehand outside the operation region of the device. As a metal contamination gettering technique using ion implantation, various methods have been conventionally known. For example, a method of performing a heat treatment after implanting phosphorus, boron, oxygen, silicon, or the like to generate secondary defects. All of them have the ability to getter metal contamination.

In Japanese Patent Application Laid-Open No. 63-248159 (Prior Art 1), a carrier generated in a light receiving element is gettered to prevent crosstalk between light receiving elements. Also, [JP-A-3-215943]
In (Prior Art 2), after forming a trench isolation groove, the method is used for gettering defects generated at the time of heat treatment applied to form an element.

In the preceding example 2, since the defects are generated during the heat treatment and the defects are generated from the corners of the groove, it is considered that the gettering is probably interstitial silicon.

[0010] As described above, as the DRAM becomes more highly integrated, the allowable heavy metal contamination amount is limited to a very low concentration range. For example, SIA (Semicond
uctor Industry Association) Roadmap (The N
ational Technology Roadmap for Semiconductor)
According to the generation of the 0.18-micron rule, Fe is required to be 1010 cm ^-3 or less.

[0011] Among heavy metal contaminants, Cu and Ni are relatively easily gettered due to rapid diffusion in silicon. On the other hand, Fe is an element that diffuses slowly and is hard to getter. As a method of effectively gettering Fe, a method of forming a high-concentration B region on a p-type (B-doped) wafer and performing gettering as described below is known.

One method is to use a p / p ⁺ epi wafer (M. Sano, S. Sumita, T. Shigematsu, and
N. Fujino, in Semiconductor Silicon, edited
byH.R.Huff, W. Bergholz, and K. Sumino (El
ectrochemical Society, Pennington, NJ, 1994),
See p784).

The p / p ⁺ epi wafer is a wafer in which a low-concentration B epitaxial layer is formed on a high-concentration B wafer, and is a method in which Fe is gettered on the high-concentration B wafer. According to this method, the device is formed on the epitaxial layer, and is not affected by Fe.

Another method is to form a gettering layer of Fe by implanting B ions into a p-type (B-doped) wafer (PAStolk, JLBenton, DJEagl).
esham, DCJacobson, JYCheng, and JMPoate,
Appl. Phys. Lett. 68, 51 (1996)).

According to this method, a gettering layer is provided in a portion deeper than a device formation region. These reports show that the high concentration B region has a very strong Fe gettering force.

Therefore, when a transistor structure was formed on a p / p ⁺ wafer contaminated with a small amount of Fe and the diffusion layer leakage was measured, it was found that the diffusion layer leakage caused by Fe contamination was reduced even when p / p ⁺ was used. Could not.

The cause is understood as follows. That is, when there is no gettering site other than the high concentration B region, Fe is gettered there without any problem. The above report corresponds to such a situation.

[0018]

However, when a transistor is formed, there is a gettering site other than the high concentration B region. Such as, for example, P or As
, An n-type diffusion layer formed by doping, an element isolation structure, and the like.

In these examples, other gettering sites work, and Fe is not gettered into the high-concentration B region but gettered into the n-diffusion layer or the element isolation structure. Therefore, the diffusion layer leakage cannot be reduced even with a p / p ⁺ wafer. It can be said that.

Therefore, in order to improve the data retention characteristics of the DRAM, it is necessary to solve the above-mentioned problems.

An object of the present invention is to provide a structure of a semiconductor memory which reduces a leak current of a diffusion layer of a memory cell and a method of manufacturing the same.

[0022]

In order to achieve the above object, a semiconductor memory according to the present invention is a semiconductor memory in which a diffusion layer of a memory cell is of an n-type and has an n-type region. Is at least p below the element isolation oxide film.
It is formed immediately below the mold well, and the concentration of the n-type region is not lower than the concentration of the n-type diffusion layer.

A semiconductor memory in which a diffusion layer of a memory cell is an n-type has an n-type region, and the n-type region is formed at least immediately below a p-type well under an oxide film to be an element isolation region. And the volume of the n-type region is
It is not smaller than the volume of the mold diffusion layer.

The n-type region is provided as a gettering region stronger than the n-type diffusion layer of the memory cell.

The concentration of the n-type region is higher than the concentration of the n-type diffusion layer, and the volume is larger than that of the n-type diffusion layer.

The n-type region is formed by doping P, and the n-type diffusion layer 2 is formed by doping P and As.

A p-type well formed by doping B is formed outside the n-type diffusion layer below the capacitor electrode. The p-type well is also formed below the element isolation region. Below and just below the p-type well, the n-type region becomes a gettering layer and reduces the leak current of the memory cell.

Further, in the method of manufacturing a semiconductor memory according to the present invention, the semiconductor memory performs groove opening processing, ion implantation processing, oxide film forming processing, planarization processing, and n-type diffusion layer forming processing in this order. In the manufacturing method, the groove opening process is a process of sequentially laminating an oxide film and a nitride film on a substrate on which a p-type well is formed, applying a resist to the lamination, and opening a groove reaching the substrate by etching. The ion implantation process is a process of ion-implanting P to form an n-type region just below the etched groove and immediately below the p-type well.
The oxide film forming process is a process for forming a buried oxide film that becomes an element isolation structure, the planarization process is a process for flattening the buried oxide film, and the n-type diffusion layer forming process is a process for forming a lower portion of the element isolation region. This is a process for forming an n-type diffusion layer at a location corresponding to.

In the ion implantation process, the implantation energy and the resist have P
The conditions were chosen so that no ions were struck.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a semiconductor memory according to the present invention. The figure simply shows the structure of the memory cell area. In this embodiment, the purpose is to reduce the junction leakage current of the n-type diffusion layer 2 under the capacitance electrode 1.

For this purpose, in the present invention, an n-type diffusion layer 2 is provided below the capacitor electrode 1, and a p-type well 3 formed by doping B is provided outside the n-type diffusion layer 2.
Are also formed below the element isolation region 5.

The present invention is characterized in that an n-type region 4 is provided below the element isolation region 5 and directly below the p-type well 3. This n-type region 4 becomes a gettering layer,
The leak current of the memory cell can be reduced.

If there is no n-type region 4, heavy metal contamination is gettered to the n-type diffusion layer 2 and the leakage current increases. In this example, the n-type diffusion layer 4 of the memory cell
Is formed by doping. In this regard, in the conventional structure, as described above, the n-type diffusion layer 2 functions as a gettering site, and as a result, there is a problem that the leakage current of the n-type diffusion layer 2 increases.

The gettering strength of the diffusion layer is related to the P concentration. The reason is that the higher the P concentration, the higher the solid solubility of the heavy metal element. Therefore, in the present invention, the n-type region 4 is provided as a gettering region stronger than the n-type diffusion layer 2 of the memory cell.

In order to make the n-type region 4 a gettering site stronger than the n-type diffusion layer 2, there are the following methods. For example, if the n-type region 4 has the same volume as the n-type diffusion layer 2,
This is a method in which the P concentration of the n-type region 4 is made higher than that of the n-type diffusion layer 2.

It is assumed that the P concentration of the n-type region 4 is
With an order of magnitude higher density, the gettering force is approximately doubled. The concentration can be designed by the dose amount of the ion implantation and the diffusion depth by the heat treatment.

Another method is to make the volume of the n-type region 4 larger than that of the n-type diffusion layer 2 by making the P concentration the same. According to this method, the gettering force increases in proportion to the volume ratio. The volume can be designed by the area of the element isolation region 5 and the depth after ion implantation. Practically, it is desirable to use these two methods in combination.

That is, the P concentration of the n-type region 4 is made higher than that of the n-type diffusion layer 2 and the volume is made larger. Next, a method of manufacturing the structure of the semiconductor device as shown in FIG. 1 will be described with reference to FIG.

In the method of manufacturing a semiconductor memory according to the present invention, a groove opening process, an ion implantation process, an oxide film forming process, a planarizing process, and an n-type diffusion layer forming process are sequentially performed.

In FIG. 2, the STI (S
Hallow Trench Isolation) will be described. FIG. 2A is a cross-sectional view when the element isolation region 5 serving as the STI portion is etched.

That is, an oxide film 12 and a nitride film 13 are laminated on a wafer 11 as a substrate as a groove opening process, a resist 14 is applied to the laminated film, and the substrate 11 is etched.
Open the groove to reach. Note that the p-type well 3 has already been formed. In FIG. 2B, next, as an ion implantation process, P is ion-implanted in order to form an n-type region 2 directly below the p-type well under the etched groove.

At this time, conditions for the implantation energy and the resist are selected so that P ions are not implanted into the silicon except for the groove portion. Next, as an oxide film forming process, as shown in FIG. 2C, a buried oxide film 15 to be an element isolation region by STI is formed by CVD. Then, as a planarization process, CMP (Chemical Mechanical P
The buried oxide film 15 is planarized by an olishing process.

Thereafter, as an n-type diffusion layer forming process, an n-type diffusion layer is formed at a position corresponding to a lower portion of the element isolation region. FIG. 2D shows a state at the time of forming up to the n-type diffusion layer 2. In the present invention, FIGS.
As shown in the above, the n-type region 4 for gettering is
It is formed below the element isolation region. The method of FIG. 2 has the following advantages.

That is, since the n-type region 4 is formed in the portion where the groove is formed in advance, the energy of ion implantation can be reduced. Therefore, the possibility that crystal defects occur in the well portion immediately above n-type region 4 is reduced. Further, at the stage of the ion implantation process for forming the n-type region 4, no ions are implanted into the region to be the n-type diffusion layer 2, so that the n-type diffusion layer 2 to be formed later is adversely affected. There is no.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following embodiment is an example in which a semiconductor memory is manufactured by using the method shown in FIG. A specific manufacturing method will be described in detail with reference to FIG. The same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 3A, the depth of the groove of the STI formed by the groove opening process is 400 nm. In order to form the n-type region 4 in this groove portion, as an ion implantation process, a P amount of 2 × 10 ¹⁵ cm ⁻² ,
The injection was performed at an energy of 1.5 MeV. (FIG. 3 (b)).

After the implantation, as a process for forming an oxide film, the resist was peeled off and embedded by CVD to form an oxide film 15 (FIG. 3C). Next, as a flattening process, the buried oxide film 15 was flattened by CMP (FIG. 3D).

Next, the nitride film 13 was removed, and B for adjusting the threshold value of the transistor was ion-implanted prior to the process of forming the n-type diffusion layer (FIG. 3D). Subsequently, structures of the gate oxide film 16 and the gate electrode 17 were formed (FIG. 3E).

Next, an n-type diffusion layer 2 was formed, and a lower capacitor electrode was formed of P-doped polysilicon (FIG. 3).
(f)). The n-type diffusion layer 2 has a P ion dose of 3 × 10
^The implantation was performed under conditions of ¹³ cm ^-2 and energy of 50 KeV. Junction leak characteristics were measured by extracting polysilicon used for the lower electrode of the capacitor and forming a PAD electrode.

However, the area of the n-type diffusion layer 2 was measured in a large pattern of the order of 1 mm ² so that it could be directly measured with a prober. The data retention characteristics were measured by fabricating a 64 Mbits DRAM by the same method.

After forming the capacitor lower electrode 19, the MIS
A stacked capacitor was formed. The area ratio between the element isolation region and the n-type diffusion layer 2 was set to almost 1 in both the pattern in which the junction leak was measured and the DRAM in which the data retention characteristics were measured.

For reference, a device without the n-type region 4 in the above-described process was manufactured as a comparative example. The wafer has p / p ⁺
An epiwafer and p-type Cz were used. p + substrate, the B concentration of the p-type Cz and p-type epitaxial layer at a B concentration 10 ^{1 9} cm about ^-3 is approximately 10 ¹⁵ cm ^-3.

The reason why the leak current of the n-type diffusion layer 2 can be reduced by manufacturing the structure shown in FIG. 1 will be described below. The cause of the leakage current is a defect existing in the depletion layer at the junction between the n-type diffusion layer 2 and the p-type well. This defect is a defect in a broad sense, including crystal defects caused by ion implantation and dry etching damage,
There are oxygen precipitates and heavy metal contamination.

Heavy metal contamination forms a deep level even if it is dissolved as a point defect. If a silicide is formed without being completely dissolved, it is fatal as a semiconductor memory. In addition, heavy metal contamination may catch a defect caused by ion implantation or dry etching damage, which may cause a problem.

According to the present invention, defects due to heavy metal contamination in the depletion layer can be reduced. Heavy metal elements (Fe,
Cu, Ni, etc.) diffuses much faster in Si than dopants (P, As, B, etc.). Nevertheless, there are various problems for gettering by diffusing from the device area.

Among the heavy metal elements, Fe is a problem because it is slow in diffusion and hard to getter. As a method of efficiently gettering Fe, there is a method of using a high-concentration B layer as a gettering layer.

Of course, since the high concentration B layer is higher than the B concentration of the p-type well forming the np junction, it is possible to prevent gettering in the p-type well.

However, the gettering force of the n-type diffusion layer is
Stronger than high concentration B layer. Therefore, in the n-type diffusion layer 2 or n
Fe is increased in the p-type well near the type diffusion layer 2.
As a result, junction leakage increases.

Most of the thickness of the p / p ⁺ wafer is the p ⁺ substrate, and it is not possible to increase the gettering force by increasing the thickness further or increasing the B concentration of the p ⁺ substrate further. .

In the present invention, the n-type region 4 is formed as a gettering site stronger than the n-type diffusion layer 2. As described above, Fe diffuses slowly from the viewpoint of gettering. Therefore, it is desirable that the n-type region 4 is arranged near the n-type diffusion layer 2.

In this embodiment, the junction depth between the n-type diffusion layer 2 and the p-type well 3 is about 0.2 μm and the n-type region 4
Is about 1.5 microns deep. Therefore, Fe only needs to be able to diffuse 1.3 microns.

Further, in the experiment of the inventor, it has been found that the gettering force of the n-type diffusion layer 2 and the n-type region 4 is determined by the P concentration and the volume of the n-type portion. In this embodiment, as described above, the area ratio between the n-type diffusion layer 2 and the n-type region 4 is 1, but the dose ratio is approximately 100. as a result,
The gettering force of the n-type region 4 is definitely higher than that of the n-type diffusion layer 2.

Since the cause of the leak current is all heavy metal elements, and most of them cannot be said to be Fe, a quantitative explanation is difficult. Thus, it is assumed that the gettering force has increased 100 times. That is, 10 ¹² cm
^When there is heavy metal contamination of ^-3, the concentration of heavy metal contamination in the n-type diffusion layer 2 can be reduced to about 10 ¹⁰ cm ^-3 .

With this method, the concentration in the n-type diffusion layer 2 can be reduced by two orders of magnitude from the amount of heavy metal contamination existing in the production line by cleaning the LSI production process.

In the case of the conventional structure, heavy metal contamination during diffusion diffused to the n-type diffusion layer 2 is present, so that the concentration of the contamination in the p-type well also increases.

According to the present invention, the heavy metal contamination that diffuses toward the n-type diffusion layer 2 is reduced, so that the contamination concentration in the p-type well 3 is also reduced. For the above reasons, the amount of heavy metal contamination in the n-p junction depletion layer in question is reduced, and the junction leakage is reduced. As a result, it is possible to improve the DRAM data retention characteristic in which the junction leak is dominant.

FIG. 4A shows a comparison of the current-voltage characteristics of the junction leak having a junction area of 1 mm ² between the present invention and the conventional example. As is apparent from the figure, according to the present invention, it is understood that the junction leakage reduction effect is remarkable especially on the low voltage side.

FIG. 4B shows a comparison of the holding characteristics of the DRAM between the present invention and the conventional example. As you can see in the figure,
According to the present invention, it can be seen that the data retention characteristics of the DRAM are improved.

In the embodiment described above, both the n-type diffusion layer 2 and the n-type region 4 are formed by doping P. However, the present invention is also effective when the n-type diffusion layer 2 is formed by doping As. As for P and As, gettering of the n-type diffusion layer 2 is higher when P is doped.

Therefore, when the n-type diffusion layer 2 is formed by doping As, the gettering can be more easily performed on the n-type region 4 formed by doping P.

The ratio between the n-type diffusion layer 2 and the dose of the n-type region 4 is about 100 times, and the n-type region 4 is higher. Since the amount of contamination in the target depletion layer has a problem of an absolute value, the n-type region 4 can be obtained even if the ratio of the dose is further reduced when the production line is cleaned and the total amount of contamination is reduced. The gettering effect is satisfactory.

When the amount of contamination on the production line is very small, even if the ratio of the dose amount is 1, it is effective. Conversely, when the amount of contamination on the production line is large, it is better to increase the ratio of the dose amount.

In the above embodiment, the element isolation structure is S
Although it has a TI structure, the present invention
The structure is also effective. In the case of the recessed LOCOS structure,
LOCOS After etching the region to be oxidized,
Before OS oxidation, P ions are implanted to form an n-type region.

[0074]

As described above, according to the present invention,
The gettering ability of heavy metal contamination is improved, and np junction leakage can be reduced. In addition, an excellent junction leakage reduction effect can be obtained particularly on the low voltage side. Further, according to the present invention, D
It also has the effect of improving the data retention characteristics of the RAM.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a semiconductor memory according to the present invention.

FIG. 2 is a diagram showing a step of forming an n-type region below the element isolation region by using STI for the element isolation structure.

FIG. 3 is a diagram showing a manufacturing process of a semiconductor memory according to the present invention in the order of processes.

FIG. 4A is a graph showing a comparison of current-voltage characteristics of a junction leak having a junction area of 1 mm ² between the present invention and a conventional example. (B) is a graph showing a comparison of the holding characteristics of the DRAM between the present invention and the conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 capacitor electrode 2 n-type diffusion layer 3 p-type well 4 n-type region 5 element isolation region 11 wafer 12 oxide film 13 nitride film 14 resist 15 buried oxide film 16 gate oxide film 17 gate electrode

Claims (8)

[Claims] 1. A semiconductor memory in which a diffusion layer of a memory cell is an n-type having an n-type region, wherein the n-type region is formed at least immediately below a p-type well under an oxide film to be an element isolation region. Wherein the concentration of the n-type region is not lower than the concentration of the n-type diffusion layer. 2. A semiconductor memory in which a diffusion layer of a memory cell is an n-type having an n-type region, wherein the n-type region is formed at least immediately below a p-type well under an oxide film to be an element isolation region. Wherein the volume of the n-type region is not smaller than the volume of the n-type diffusion layer. 3. The semiconductor memory according to claim 1, wherein the n-type region is provided as a gettering region stronger than the n-type diffusion layer of the memory cell. 4. The semiconductor memory according to claim 1, wherein the concentration of the n-type region is higher than the concentration of the n-type diffusion layer, and the volume is larger than that of the n-type diffusion layer. 5. The n-type region is formed by doping P, and the n-type diffusion layer 2 is formed by doping P and As. Or 4
A semiconductor memory according to claim 1. 6. A semiconductor device, comprising:
A p-type well formed also under the element isolation region, having an n-type region under the element isolation region and directly below the p-type well, A semiconductor memory, wherein the region serves as a gettering layer to reduce leakage current of a memory cell. 7. A method of manufacturing a semiconductor memory in which a groove opening process, an ion implantation process, an oxide film forming process, a planarization process, and an n-type diffusion layer forming process are sequentially performed. An oxide film,
This is a process in which a nitride film is sequentially stacked, a resist is applied to the stacked film, and a groove reaching the substrate is opened by etching. In the ion implantation process, an n-type region is formed immediately below the p-type well under the etched groove. Therefore, the process of ion-implanting P is performed. The process of forming an oxide film is a process of forming a buried oxide film having an element isolation structure. The planarization process is a process of planarizing a buried oxide film. The method of manufacturing a semiconductor memory, wherein the type diffusion layer forming process is a process of forming an n-type diffusion layer at a position corresponding to a lower portion of the element isolation region. 8. In the ion implantation process, conditions for the implantation energy and the resist are selected so that P ions are not implanted into silicon other than the trench portion. Item 8. A method for manufacturing a semiconductor memory according to item 7.