JP2007221160A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a silicide layer with uniform film thickness and film quality can be formed on a source drain region, junction leak in an MOS structure can be suppressed low, and good electrical connection between the silicide layer and metal wiring can be assured. <P>SOLUTION: The semiconductor device includes a gate electrode formed on a silicon substrate through a gate insulating film, a sidewall insulating film formed on the side part of the gate electrode, a source drain region formed in the silicon substrate corresponding to the gate electrode, and an As doped NiSi layer formed on the source drain region. The NiSi layer has the local maximum concentration point of As in the center part in the film thickness direction, and the concentration of As atom of the center part in the film thickness direction is ≥1.25×10<SP>17</SP>cm<SP>-3</SP>and ≤2.5×10<SP>18</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device suitable for large-scale integration, and more particularly to a field effect transistor (hereinafter abbreviated as MOSFET) having silicided source / drain electrodes.

  In recent years, MOSFETs are increasingly required to be miniaturized for large-scale integration of semiconductor devices, and so-called short channels in which the threshold voltage decreases as the channel length of the MOSFET (ie, the length of the gate electrode) decreases. The effect is a problem. The short channel effect can be avoided by bringing the position of the pn junction forming the source and drain of the MOSFET closer to the semiconductor surface (that is, making the pn junction shallow). However, if the pn junction is simply made shallow, the resistance of the source / drain electrodes formed thereby increases, which impedes high-speed transmission of signals transmitted through the element.

  In order to reduce the resistance of the source / drain electrodes, the upper portions of the source / drain regions are combined (silicided) with a metal such as Co or Ni. However, when the silicide is formed or during the subsequent heat treatment, these metal atoms diffuse rapidly in the silicon forming the source / drain regions, and when the shallow junction is formed, the metal reaches the junction. For this reason, junction leakage is caused (for example, see Patent Document 1).

In fact, in the case of Co, rapid heat treatment at 800 ° C. for 30 seconds is required to form CoSi ₂ in a low resistance phase, but this Co atom diffusion is extremely fast, and only 150 nm is obtained by performing this heat treatment. It reaches the depth. In addition, in the case of Ni, after forming NiSi of a low resistance phase, a low-temperature heat treatment of about 500 ° C. for about 90 minutes is required to obtain an electrical junction between the silicide layer and the metal wiring. Atoms diffuse rapidly, and even after this heat treatment, the depth reaches 140 nm. Metal atoms that have penetrated deep into the silicon substrate cause leakage current.

  In order to cope with such a problem, a semiconductor material is selectively grown on a surface portion of a semiconductor substrate where a source / drain electrode is to be formed, and a source / drain pn junction is formed through the additionally formed surface, and By forming the silicide layer, the position of the junction with respect to the original semiconductor surface (that is, the surface on which the channel is formed) is ensured while ensuring the thickness of the electrode portion forming the source / drain (thickness of the diffusion layer). Has been used (Elevated source drain method).

  However, it is extremely difficult to make the film thickness and film quality (existence of defects) of the silicon layer additionally formed by selective growth uniform. If the film thickness is not uniform, it becomes extremely difficult to form the junction portion of the pn junction near the original semiconductor substrate surface (that is, the surface on which the channel is formed). In addition, even when the film quality is not uniform, it is difficult to accurately match the junction portion of the pn junction with the target position below the surface of the semiconductor substrate. The same applies to the diffusion of metal atoms accompanying silicidation. If the film thickness and film quality are not uniform, even if a silicon layer is additionally formed, metal atoms project from the thin film thickness or poor film quality and easily reach the bonding surface. As a result, junction leakage occurs.

On the other hand, regarding the silicide metal species, in the case of Co, Co atoms inevitably diffuse into the silicon substrate accompanying the silicidation reaction. On the other hand, the metal compounding reaction (silicidation reaction) between Si and Ni can be performed at 450 ° C., which is lower than 800 ° C., which is the formation temperature of CoSi ₂ . Therefore, in order to suppress the diffusion of metal atoms, it is desirable to use NiSi that can form a low resistance phase at a low temperature.

However, even if heat treatment is performed at 500 ° C. for 90 minutes, which is much lower than the phase transition temperature to NiSi ₂ , which is 750 ° C., Ni atoms can diffuse and penetrate deep into the silicon substrate and cause leakage. Explained earlier. Naturally, in order to prevent infiltration of Ni atoms into the silicon substrate, it is required to strictly limit the heat treatment temperature to less than 450 ° C.

On the other hand, when trying to achieve good electrical connection between NiSi and the electric wiring material formed in the narrow source / drain region of the fine MOSFET through the contact hole of the opening smaller than the source / drain region. Heat treatment at around 500 ° C. (450 ° C. to 550 ° C.) is indispensable. This is because, at temperatures below this temperature, it is impossible to sufficiently melt and remove the oxide-derived insulating material slightly formed between NiSi and the wiring metal.
JP 2002-368008 A

  As described above, conventionally, with the miniaturization of the element, it is necessary to form a silicide layer on the source / drain region in order to keep the source / drain electrode electrical resistance low while keeping the source / drain junction position shallow. However, it becomes difficult to suppress the high-speed diffusion of the metal atoms forming the silicide and the junction leakage caused thereby.

  Even if the Elevated Source Drain structure is adopted to eliminate this difficulty, it is extremely difficult to form a uniform and homogeneous silicon layer, and the function of suppressing junction leakage is limited. Further, if all the process temperatures after the silicide process are limited to 450 ° C. or lower in order to suppress high-speed diffusion of metal atoms, the electrical connection between the fine silicide layer and the metal wiring is impaired.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to form a silicide layer having a uniform film thickness and film quality on the source / drain regions, and to keep junction leakage low. Another object of the present invention is to provide a semiconductor device capable of ensuring good electrical connection between a silicide layer and a metal wiring.

  In order to solve the above problems, the present invention adopts the following configuration.

That is, according to one embodiment of the present invention, in a semiconductor device having silicided source / drain electrodes, a gate electrode formed over a silicon substrate with a gate insulating film interposed therebetween and formed on a side portion of the gate electrode A sidewall insulating film; a source / drain region formed in the silicon substrate corresponding to the gate electrode; and an As-doped NiSi layer formed on the source / drain region. The layer has a local maximum point of As in the central portion in the film thickness direction, and the concentration of As atoms in the central portion in the film thickness direction is 1.25 × 10 ¹⁷ cm ⁻³ or more and 2.5 × 10 ¹⁸ cm. ^-3 or less.

According to the present invention, the concentration of As atoms in the central portion of the silicide layer on the source / drain region in the film thickness direction is set in the range of 1.25 × 10 ¹⁷ cm ^{−3 to} 2.5 × 10 ¹⁸ cm ^−3. By doing so, the thermal stability of the silicide layer can be improved. Therefore, a heat treatment at about 500 ° C. can be applied without causing high-speed diffusion of a silicide metal such as Ni, thereby realizing a good electrical connection between the silicide layer and the metal wiring.

  Before describing the embodiment, the basic principle of the present invention will be described.

  The present inventors examined in detail how the thermal instability of NiSi, which is a problem in ensuring sufficient electrical contact with the wiring metal, changes due to the presence of impurities in silicon. . As a result, prior to the formation of NiSi, the introduction of As atoms that do not replace silicon atoms (hereinafter referred to as off-lattice As) will rapidly improve the thermal stability of NiSi. Newly discovered. In the case of NiSi with improved thermal stability, it is possible to effectively avoid the occurrence of junction leakage due to Ni without restricting the subsequent heat treatment temperature to less than 450 ° C., and sufficient electrical contact with the wiring metal It was found that it can be secured.

  Hereinafter, this will be described in detail with reference to FIGS.

  As described in (Background Art), after forming NiSi of a low resistance phase on a silicon layer, a low-temperature heat treatment at 500 ° C. for about 90 minutes is performed in order to obtain an electrical junction between the silicide layer and the metal wiring. However, at this time, Ni atoms diffuse rapidly, and even if this heat treatment is performed, the depth reaches 140 nm. Metal atoms that have penetrated deep into the silicon substrate cause leakage current.

First, as shown in FIG. 1, the present inventors discovered that the NiSi phase behaves extremely thermally unstable long before the phase transition reaction occurred. Actually, even if a heat treatment of 500 ° C. and 90 minutes, which is much lower than 750 ° C. which is the phase transition temperature to NiSi ₂ , is performed, junction leakage already occurs at a junction depth of 140 nm much deeper than the silicide film.

  Next, in order to prove that this is a result of diffusion of Ni atoms into the substrate, the present inventors have investigated the junction depth dependency of the leakage current and the depth of the concentration of Ni atoms diffused and penetrated into the silicon substrate. I checked the dependence.

  First, a silicon substrate on which pn junctions with various depths are formed is prepared. After Ni is deposited thereon, RTA (Rapid Thermal Annealing) treatment is performed in a nitrogen atmosphere at 450 ° C., and NiSi is formed to a thickness of 30 nm. Formed. Thereafter, heat treatment was performed at 500 ° C. for 10, 30, 60, and 90 minutes, and the generated junction leakage current density was observed at various junction depths. The raising and lowering temperature of the heat treatment was set to 100 ° C./min. Moreover, the depth distribution of the concentration of Ni contained in the silicon substrate of each sample was determined by using the backside SIMS method. The backside SIMS method is a method in which the sample is polished from the back surface to the front surface, and SIMS analysis is performed from the back surface. Knocking from NiSi on the surface is suppressed, and an accurate Ni concentration in the Si substrate is required. .

  FIG. 2 shows the observed junction leakage current density (right vertical scale) as a function of pn junction depth for each heat treatment condition. Further, accompanying this, the depth distribution of the concentration of Ni (left vertical scale) contained in the Si substrate of each sample obtained by using the backside SIMS method is also shown in a corresponding manner. . The junction depth distribution of the junction leakage current density and the depth distribution of the Ni concentration are very well matched, and there is no doubt that the origin of the leak is due to Ni that diffuses and penetrates into the Si substrate along with the heat treatment. Absent.

  From the above results, it has been clarified that the cause of the leak is the penetration and diffusion of Ni atoms into the silicon substrate due to the thermal instability of NiSi. Therefore, in order to investigate the effect of impurities on the occurrence of junction leakage due to thermal instability of NiSi, how the penetration of Ni atoms into the silicon substrate is modulated by the presence of impurities It can be seen that attention should be paid to.

Therefore, the present inventors ion-implanted As and Ge into the silicon substrate surface under the conditions of 2.5 × 10 ¹³ cm ⁻² , 1.0 × 10 ¹⁴ cm ^{−2 and} acceleration energy of 30 keV before forming NiSi. After that, NiSi was formed by deposition and silicidation of the Ni film, and this was subjected to a heat treatment at 500 ° C. for 90 minutes to observe how the diffusion of Ni atoms into the silicon substrate changed.

  FIG. 3 shows the depth distribution of Ni concentration when Ge ion implantation is performed after heat treatment at 500 ° C., 10 minutes, 30 minutes, 60 minutes, and 90 minutes when no ion implantation is performed for reference. It is shown in comparison with the depth distribution of the concentration of Ni. Similarly, FIG. 4 shows the depth distribution of Ni concentration when As ion implantation is performed at 500 ° C., 10 minutes, 30 minutes, 60 minutes, and 90 minutes when no ion implantation is performed for reference. It is shown in comparison with the depth distribution of the Ni concentration after the heat treatment.

In the case of Ge ion implantation, diffusion penetration of Ni into the silicon substrate is suppressed in the region immediately below NiSi, but the effect of suppression is reduced as the substrate goes deeper, and at a depth of 100 nm, 1.0 × 10 ^14. Even when cm ^{−2 is} implanted, the concentration is the same as the reference concentration after heat treatment at 500 ° C. for 60 minutes. Further, it can be seen that the method of attenuation of the Ni concentration in the depth direction deviates from a pure complementary error function type as seen for reference and attenuates almost linearly. That is, it can be said that intrusion diffusion of Ni into the silicon substrate is not a pure diffusion mechanism but some speed-up diffusion mechanism is working. Therefore, it is considered that the diffusion suppressing effect is further diminished as the depth of the substrate is increased.

On the other hand, in the case of As ion implantation, even if the implantation amount is 2.5 × 10 ¹³ cm ⁻² at most, the diffusion of Ni atoms into the silicon substrate is extremely effectively suppressed, and the Ni concentration distribution is 500 ° C. for 90 minutes. In spite of the heat treatment, the Ni concentration for reference is equivalent to 500 ° C. for 30 minutes. That is, diffusion corresponding to 60 minutes in terms of a heat treatment time of 500 ° C. is suppressed. Further, the abnormal concentration attenuation of the non-complementary error function type of Ni atoms as seen in the Ge ion implantation is not observed, and the method of attenuation of the Ni concentration in the depth direction is almost the same as that of the reference data. Matches perfectly and decays rapidly.

From this, it is understood that the intrusion diffusion of Ni into the silicon substrate follows a pure diffusion mechanism, and an abnormal enhanced diffusion mechanism as in the case of Ge ion implantation does not appear. Therefore, it is concluded that the Ni diffusion suppression effect by As is maintained as it is even deep in the substrate. Furthermore, even if the injection amount is increased to 1.0 × 10 ¹⁴ cm ⁻² , the effect of suppressing the diffusion of Ni does not change greatly. In the case of As, an extremely small amount of 2.5 × 10 ¹³ cm ⁻² is already sufficient. It is shown that a full inhibitory effect is achieved.

  Therefore, in order to suppress the diffusion of Ni into the silicon substrate and prevent the occurrence of leakage current, it is considered promising to introduce a small amount of As with high suppression effect into the silicon substrate as an impurity. However, there are roughly two forms in which As is introduced into the silicon substrate. When the As atom replaces the Si atom and replaces the lattice position (referred to as on-lattice), and the As atom does not occupy the silicon lattice position and exists between them (referred to as off-lattice) ).

  Therefore, the present inventors further verified whether or not a difference occurs in the leakage current suppression effect depending on the form of As in silicon. That is, immediately after As ion implantation, rapid heat treatment was performed to convert As atoms in off-lattice to on-lattice, and how the leakage current changed due to this was actually measured.

FIG. 5 shows the leakage current density as a function of the implantation amount when As ion implantation is performed prior to NiSi formation. The implantation energy was 30 keV, and the amount of implantation was changed in the range of 2.5 × 10 ¹³ cm ^{−2 to} 1.0 × 10 ¹⁴ cm ⁻² . The junction depth was 106 nm. In order to see the effect of on-lattice As, after As injection, NiSi was subjected to a rapid heat treatment at 700 ° C. for 30 seconds, and in order to see the effect of off-lattice As, the rapid heat treatment was not applied. In order to measure the junction leakage caused by As ion implantation itself, NiSi was not formed, and each was subjected to a heat treatment at 500 ° C. for 90 minutes, and then the leakage current observed in these was compared. Show.

  First, the effect of As in silicon on leakage suppression can be measured by comparing the presence or absence of rapid thermal processing. Obviously, the leakage current density is remarkably increased to two digits or more when the rapid heat treatment is performed and the As is in the on-lattice state. Therefore, it has been proved that the effective Ni diffusion suppression effect by introducing As is an effect that is specifically expressed when As is off-lattice.

In addition, by observing the dependency of leakage suppression on the implantation amount, it is possible to assess the damage of the silicon substrate surface due to ion implantation and the influence of amorphization. Amorphization by ion implantation proceeds with an implantation amount higher than this at an implantation amount of 5.0 × 10 ¹³ cm ⁻² . However, there is no significant difference in the leakage current density after 2.5 × 10 ¹³ cm ⁻² implantation amount. Therefore, the effective Ni diffusion suppression effect due to the introduction of As is the effect of off-lattice As itself, and the substrate surface damage accompanying the ion implantation including the amorphization of the silicon substrate itself It became clear that it was not necessary.

  Finally, by looking at the leakage current density of the sample in which As ion implantation did not form NiSi, it is possible to evaluate the leakage current derived from crystal defects generated in the silicon substrate by As ion implantation itself. In the 30 keV As implantation, As atoms themselves are introduced within 30 nm of the silicon surface. However, the kinetic energy of the injected As atoms blows off Si atoms in the substrate, and the blown Si atoms penetrate into the substrate deeper than 100 nm and generate crystal defects. Obviously, at the junction depth of 106 nm, the leakage current derived from this defect has reached almost the same magnitude as the leakage current suppressed by off-lattice As.

  Such bounced Si atoms move very rapidly, and the formed crystal defects reach very deep in the silicon substrate. Of course, the amount does not decrease rapidly with depth. Therefore, as it goes deeper into the substrate, the junction leakage due to the ion implantation itself exceeds the leakage current derived from the diffusion of Ni.

  In order to eliminate these crystal defects, heat treatment at a high temperature used for activation or the like is necessary. As soon as such heat treatment is performed, As becomes an on-lattice state, and Ni diffusion suppression effect is exerted. Lost. On the other hand, needless to say, if such high-temperature heat treatment is performed after NiSi is formed, this itself induces diffusion of Ni and consumes all the advantages obtained by improving the heat resistance of NiSi. Therefore, when off-lattice As is introduced by ion implantation and Ni diffusion is to be suppressed, a junction leak derived from the ion implantation itself is generated deeply in the substrate. As a result, it has been found that the effect of reducing junction leakage by suppressing Ni diffusion is significantly limited.

  In summary of the above findings, the suppression of the diffusion of Ni into the silicon substrate is a peculiar effect expressed by off-lattice As itself, and the generation of physical damage accompanying ion implantation is given to this. Not. Rather, it has been clarified that ion implantation generates crystal defects deep in the silicon substrate and offsets the reduction of junction leakage due to suppression of Ni diffusion. That is, effective suppression of the diffusion of Ni into the silicon substrate can be achieved for the first time by introducing off-lattice As without damaging the silicon substrate.

  In order to introduce off-lattice As to a silicon substrate without causing damage, As may be chemically adsorbed on the silicon surface. Of course, the silicon substrate is not damaged. As is adsorbed on the surface and does not replace the lattice position of Si. Therefore, if Ni is deposited thereon and silicidized, diffusion of Ni into the silicon substrate can be effectively suppressed and leakage can be reduced without causing the problems associated with the ion implantation described above. It will be.

Finally, in order to examine how As introduced as off-lattice is reflected in the NiSi film formed thereafter, As was implanted at 30 keV and 1.0 × 10 ¹⁴ cm ⁻² , 30 nm NiSi was formed, and As contained therein was measured by SIMS analysis.

  FIG. 6 shows the results of SIMS analysis of the concentration of As contained in NiSi and in the silicon substrate below the NiSi. In order to see the effect of off-lattice As, NiSi is formed without performing a rapid heat treatment after ion implantation, and in order to observe the effect of on-lattice As, NiSi is formed after performing a rapid heat treatment after ion implantation. The comparison is shown. In the case of On-lattice As, As is segregated at the NiSi / Si interface so as to be pushed out of the NiSi film to the Si substrate with the silicidation reaction. On the other hand, in the case of off-lattice As, it can be seen that some As atoms remain in the NiSi film, particularly in the center of the film thickness. In the case of silicidation of on-lattice As in which As does not remain, no improvement in thermal stability is observed, and in the case of silicidation of off-lattice As in which As remains, the thermal stability is significantly improved. It was observed. From this, it can be seen that As remaining in the central portion of the NiSi film is greatly related to the improvement of the thermal stability of the NiSi film.

  If such As is to be introduced by implanting As after forming NiSi, not only crystal defects associated with the ion implantation are caused deep in the silicon substrate as described above, but also Ni atoms are introduced. Needless to say, it is repelled by the silicon substrate and induces a large leakage current.

  As described above, if off-lattice As is introduced without damaging the silicon substrate by adsorption prior to the silicidation process, As is incorporated into the NiSi film along with silicidation, and the heat resistance of the film is reduced. It will be significantly improved. On the other hand, since no new leak accompanying the ion implantation occurs, it is possible to effectively suppress the diffusion of Ni into the silicon substrate and reduce the leak.

  Further, since the heat resistance of the NiSi layer is improved, the NiSi layer formed on the fine source / drain regions and the metal material contacting the NiSi layer through the opening of the contact hole are heated to 450 ° C. or more. It becomes easy to hold and ensure electrical contact. As a result, a silicide layer can be formed while maintaining a shallow source / drain junction position, and a high-speed, high driving power miniaturized MOSFET without a short channel effect can be realized.

(Embodiment)
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  The present embodiment has an elevated source drain structure that suppresses diffusion of Ni atoms into the substrate and partially extends on the element isolation region, and further, a NiSi layer is formed on the source, drain, and gate electrodes in a self-aligning manner. Forming. Also, a complementary MOSFET having a local wiring made of a NiSi layer and ensuring good electrical contact with the wiring metal by improving the thermal stability of the NiSi layer and having a shallow source / drain diffusion layer Implement a simple manufacturing process of the structure.

  First, as shown in FIG. 7, shallow trenches 101, 102, 103 are formed in the surface portion of a p-type silicon substrate 100, and an insulating film 104 such as a silicon oxide film is formed in these trenches 101-103. Embedded. The grooves 101 to 103 on the substrate surface are formed by a lithography process, an RIE process, and the like, and the buried insulating film 104 is publicly known, for example, deposited by a CVD (chemical vapor deposition) method, and further planarized by a CMP (chemical mechanical polishing) method. This can be achieved with In the silicon substrate 100, a p-type well region 100a and an n-type well region 100b are formed by a known technique such as ion implantation and heat treatment.

  Next, as shown in FIG. 8, a thermal oxide film is formed on the entire surface of the substrate as a gate insulating film 200 by a thermal oxidation method to a thickness of 5 nm. Subsequently, a polysilicon layer as a gate electrode constituent material 300 is deposited to a thickness of 200 nm using a known technique such as a CVD method. Next, after forming a photoresist (not shown) as a mask material by a lithography method, the polysilicon layer 300 and the gate insulating film 200 are selectively etched by an RIE method to process them into a gate structure. That is, the gate insulating film 200a and the gate electrode 300a are formed on the p-type well region 100a, and the gate insulating film 200b and the gate electrode 300b are formed on the n-type well region 100b.

  Next, using a photoresist (not shown) covering the well region having the different polarity with the gate electrode as a mask, the left and right sides of the gate electrodes 300a and 300b had conductivity opposite to that of the well region serving as the source and drain extension regions. A shallow diffusion layer is formed by ion implantation. That is, in the p-type well region 100a, n-type diffusion layers 111a and 112a are formed on both sides of the gate electrode 300a, and in the n-type well region 100b, p-type diffusion layers 111b and 112b are formed on both sides of the gate electrode 300b.

  Next, as shown in FIG. 9, after depositing a silicon nitride film by 20 nm, for example, by the CVD method, the silicon nitride film is formed on the left and right sides of the gate electrodes 300a, 300b by etching back by anisotropic etching such as RIE process. A gate sidewall insulating film is formed by selectively remaining. That is, gate sidewall insulating films 301a and 302a are formed on the left and right sides of the gate electrode 300a, and gate sidewall insulating films 301b and 302b are formed on the left and right sides of the gate electrode 300b.

  Thereafter, using a photoresist (not shown) covering the gate electrode, the gate side wall, and the well region with different polarities as masks, the left and right sides of the gate electrode had conductivity opposite to that of the well region serving as the source / drain regions. A diffusion layer is formed by ion implantation. That is, n-type diffusion layers 121a and 122a are formed in the p-type well region 100a, and p-type diffusion layers 121b and 122b are formed in the n-type well region 100b. At this time, conductive impurities opposite to the well region are also implanted into the gate electrodes 300a and 300b. Furthermore, the impurities are activated by subjecting this to rapid heating / cooling heat treatment. The diffusion layers 121a, 122a, 121b, and 122b are formed from the surface of the silicon substrate 100 to a depth of, for example, 90 nm.

  Next, as shown in FIG. 10, a silicon film 400 is deposited on the entire surface to a thickness of 20 nm by using, for example, a CVD method. Thereafter, as will be described later, unnecessary portions of the silicon film 400 are formed except for the portions 401 and 403 that are used as an Elevated Source Drain structure and are used as a local wiring between the devices. It is removed by lithography or RIE.

  Here, the deposition of the silicon film 400 by the CVD method can be performed uniformly, and non-uniformity in film thickness and film quality as seen in the epitaxial growth technique can be avoided. Accordingly, protrusion of the silicide metal due to the nonuniformity of the film thickness and film quality is prevented, and a stable silicide layer can be formed. It should also be noted that since part of the source and drain electrodes extend on the element isolation region, the coupling capacitance with the substrate is reduced and the element can be operated at high speed.

The substrate is then exposed to a carbon-containing plasma. The carbon-containing plasma can be generated in an effective manner within the known art. The source of carbon can be any source that can supply carbon into the plasma. For example, the carbon-containing plasma can be generated by supplying a gas such as CF ₄ , CHF ₃ , CCl, or CH ₄ into the plasma. In addition, when the substrate has a carbon-containing material such as a photoresist mask, carbon can be supplied from here using ion bombardment accompanying RIE.

  In general, the plasma becomes positive with respect to surrounding materials in order to maintain the state. As a result, an electric field is generated from the plasma in a direction in which particles having a positive charge with respect to the surrounding substance are vertically incident. Therefore, positively charged carbon particles in the plasma collide perpendicularly with the gate electrodes 300a and 300b and the silicon film 400. For this reason, carbon particles are injected only on the horizontal surface, and no carbon particles are injected on the vertical surface. Thus, a carbon-containing silicon layer is formed on the horizontal surface. Since incident particles from a commonly used RIE plasma are accelerated at 1 kV or less, the thickness of the carbon-containing silicon layer is only tens of angstroms. The carbon content of the carbon-containing silicon layer may be 1 at% or more.

  When this carbon-containing silicon layer is thermally oxidized according to the principle disclosed in a known document (USP 6,271,566 B1 (M. Tsuchiaki, Toshiba)), an oxide film that is not etched in an HF solution is formed. Since a normal oxide film is formed in the vertical portion, it is possible to selectively leave the oxide film only on the horizontal surface of the silicon film 400 by immersing it in an HF solution after thermal oxidation. Using this oxide film as a mask, only the vertical portion of the silicon film 400 can be removed by an isotropic etching process of silicon having selectivity with respect to the oxide film, for example, an etching process such as CDE (Chemical Dry Etching). Thereafter, the oxide film remaining on the horizontal surface of the silicon film 400 is removed by, for example, the RIE method.

  By such a process, the additional source and drain-silicon layers 401 and 403 partially extending to the element isolation additional region, the silicon layer 402 in which local wiring between elements is to be formed, and the additional silicon layer 430a on the gate electrode , 430b. FIG. 11 is a cross-sectional view of the element structure at this stage.

  Here, since the silicide layer is formed from the upper surface of the additionally formed silicon layer, it should be noted that the effective junction depth is 20 nm + 90 nm = 110 nm in performing the silicide process. .

Next, by exposing the silicon film 400 to an AsH ₃ gas diluted to 5% with He under conditions of a temperature of 600 ° C. and a pressure of 1 Torr, As atoms are exposed to the surface of the silicon film 400 as shown in FIG. Adsorb selectively. The adsorption amount is saturated at about 5 × 10 ¹⁴ cm ⁻² , and no more As is adsorbed even if the treatment time is extended. As described above, this adsorption amount is sufficient to improve the thermal stability of Ni. On the other hand, even if this level of As is introduced, the polarity of the p ⁺ source / drain region does not invert, so that this method can be stably applied to the manufacture of a complementary MOSFET circuit (CMOS circuit). Can do.

In addition, if the adsorption amount of As is 2.5 × 10 ¹³ cm ⁻² or more as described above, there is an effect of suppressing the diffusion of Ni. Therefore, the time of exposure to AsH ₃ gas may be adjusted so that As atoms of 2.5 × 10 ¹³ cm ⁻² or more and 5 × 10 ¹⁴ cm ⁻² or less are adsorbed.

  Next, as shown in FIG. 13, a Ni film 500 is deposited on the entire surface to a thickness of 12 nm by using, for example, a sputtering method. If necessary, a metal material that becomes Cap, such as a material such as Ti or TiN, may be further deposited thereon. Subsequently, this substrate is rapidly heat-treated in nitrogen under conditions of, for example, 450 ° C. for 30 seconds, and a silicidation reaction is selectively advanced with silicon in direct contact with Ni. Unreacted Ni is selectively removed by dipping in a mixed solution of sulfuric acid and hydrogen peroxide.

  As a result, NiSi layers 501, 502, and 503 are formed on the additional source, drain-silicon layers 401 and 403, and the silicon layer 402 where local wiring between the elements is to be formed, respectively, and the additional silicon layer 430 a on the gate electrode is formed. , 430b, NiSi layers 530a and 530b are respectively formed. At this time, the film thickness of NiSi is 28 nm to 30 nm. Due to the silicidation reaction, the additional silicon layer is almost completely consumed.

At this time, when As atoms of 2.5 × 10 ¹³ cm ⁻² or more and 5 × 10 ¹⁴ cm ⁻² or less are adsorbed, the concentration of As atoms in the central portion of the NiSi film is 1.25 × 10 10. ¹⁷ cm ⁻³ or more and 2.5 × 10 ¹⁸ cm ⁻² or less. As is incorporated in this way, the thermal stability of NiSi is improved, and even if a heat treatment is performed at 500 ° C. for 90 minutes, no leakage occurs.

  The NiSi layers 530a and 530b formed on the gate contain only As regardless of the polarity of the MOSFET. It is known that the resistivity of NiSi obtained by siliciding silicon containing both n-type and p-type conductive impurities is higher than that of NiSi obtained by siliciding silicon containing only one of them. Yes.

  In the conventional CMOS forming method, both conductive impurities may be introduced into a part of the gate polysilicon electrode that connects the n-MOSFET and the p-MOSFET. Since silicon layers 430a and 430b containing only As are formed on the gate polysilicon electrode and silicided, an increase in the resistivity of NiSi can be avoided. Therefore, it is possible to efficiently reduce the electrical resistance of the thin line-shaped gate polysilicon electrode connecting the n-MOSFET and the p-MOSFET.

  Of course, since the local wiring is completed simultaneously with silicidation, it goes without saying that the element manufacturing process is simplified. Furthermore, it is known that when a silicon layer containing As is converted to NiSi, the work function of NiSi approaches the center of the forbidden band of intrinsic silicon. Therefore, as in the present embodiment, when the As-containing silicon layer is converted to NiSi to form local wiring between elements crossing the n-type well region and p-type well region, the work function of the local wiring is made of intrinsic silicon. Since it is close to the forbidden band center, no matter which polarity potential is applied, any well region is not easily inverted. As a result, the range of potentials that can be applied can be expanded. As a result, it is possible to reduce the insulating film thickness for element isolation, and the fine element isolation can be realized by a shallower groove than the conventional one, so that the element isolation process is facilitated.

Next, first, a silicon nitride film 600 is uniformly deposited on the surface of the substrate with a thickness of, for example, 20 nm so as to cover the NiSi regions 501, 503, 502, 530a, and 530b. The uniform deposition of the silicon nitride film at low temperature is performed by a CVD method using Si ₂ Cl ₆ and NH ₃ as supply gases, or an atomic layer deposition method (ALD, atomic layer deposition) using SiH ₂ Cl ₄ and NH _3. Can be realized.

  The silicon nitride film 600 functions as a barrier layer, an etching stop layer, that is, a liner layer, when forming an interlayer insulating film and forming a contact hole therethrough. By providing such a liner layer uniformly on the surface of the substrate including the element isolation region, contact holes can be formed without necessarily being precisely aligned with the NiSi region (Boarderless Contact formation). For this reason, the element manufacturing process can be simplified and the manufacturing cost can be reduced.

Further, a silicon oxide film 700 serving as an interlayer insulating film is deposited on the silicon nitride film 600 as the liner layer. A silicon oxide film exhibiting surface flatness at a low temperature can be realized by supplying O ₃ , Si (OC ₂ H ₅ ) ₄ (TEOS) gas at 400 ° C., for example. Further, a material containing a material material of a silicon oxide film exhibiting fluidity such as SOG (Spin on Glass, silicon compound RnSi (OH) 4-n, R: organic molecule and additive) is rotated using, for example, a spinner. The silicon oxide layer 700 may be formed by removing the components other than the material substance of the silicon oxide film by applying and then heat-treating in a nitrogen atmosphere at 300 ° C. for 30 minutes, for example.

  Thereafter, the silicon oxide layer 700 is selectively etched using a known method such as lithography or RIE to form contact holes 701 and 703 that reach the NiSi region 501 on the source and the NiSi region 503 on the drain. . At this time, RIE is preferably performed in two stages. First, selective oxide film etching is performed on the silicon nitride film 600, and the silicon nitride film liner layer 600 is used as an etching stopper for RIE. Subsequently, the thin silicon nitride liner layer 600 remaining at the bottom of the contact is removed by a short etching process.

  In this way, since etching can be completed in a short time, plasma damage to the underlying NiSi regions 501 and 503 can be reduced. Even when a part of the bottom of the contact overlaps the element isolation region, it is possible to prevent the contact hole from penetrating into the element isolation region at this part.

Next, the NiSi regions 501 and 503 exposed at the bottom of the contact are exposed to a plasma containing, for example, NF ₃ for a short time to clean the surface, and then a metal material 800 having a barrier property, eg, Ti, is applied to the entire surface of the semiconductor substrate. For example, it is formed by a sputtering method, for example, with a thickness of 5 nm. FIG. 14 shows a cross-sectional view of the element at this stage.

  Thereafter, heat treatment is performed at, for example, 500 ° C. in a nitrogen atmosphere in order to improve electrical contact between the metallic substance 800 having a barrier property and the NiSi regions 501 and 503. By this heat treatment, the thin oxide formed on the upper portions of the NiSi regions 501 and 503 is reduced and removed by Ti, and good electrical contact is ensured. On the other hand, since NiSi is obtained by siliciding a silicon layer that has adsorbed As, no leak occurs even if heat treatment is performed at 500 ° C. for 90 minutes.

After this heat treatment, for example, the W film 900 is filled in the contact holes 701 and 703 by a CVD method using WF ₆ and H ₂ as supply gases. Since the surface of the metal material 800 having a barrier property has been changed to a sufficiently dense structure by heat treatment at 500 ° C. for 90 minutes, reaction with F contained in the CVD supply gas is suppressed, and the underlying NiSi region 501 It is possible to prevent 503 parts from being eroded by F. Therefore, it is possible to avoid that the yield of the electric wiring is lowered and the advantage of forming the silicide is completely lost.

  Thereafter, a silicon oxide film 1000 which is an interlayer insulating film is further deposited, and trenches 1001 and 1002 to be filled with a wiring material are formed thereon by using a known method such as a lithography method or an RIE method. A metal material, for example, a Cu film 1100 is filled and formed in the groove by a damascene method. Subsequently, an insulating material such as a silicon oxide film 1200 is further deposited so as to cover the upper portion of the wiring material. FIG. 15 shows a cross-sectional view of the element at this stage.

  Furthermore, if necessary, a multilayer wiring is constructed, and a semiconductor device is completed through a mounting process and the like.

  As described above, according to the present embodiment, the gate, the source, and the drain are silicided with a uniform film thickness and film quality while having the very shallow source / drain diffusion layer, and the source / drain region is formed on the element isolation region. The structure can be realized by extending partly. For this reason, the coupling capacitance with the substrate is reduced, the device can be operated at high speed, and the increase in the resistivity of NiSi on the gate polysilicon electrode connecting the n-MOSFET and the p-MOSFET is avoided. Since the diffusion of metal atoms is suppressed, junction leakage is suppressed to a very low level. In addition, the inclusion of As has improved the heat resistance, so that a high electric power MOSFET is ensured in good electrical contact with the wiring metal. The element is completed.

  That is, since the deposited silicon film formed by the CVD method is silicided, a silicide layer having a uniform film thickness and film quality can be obtained, and non-uniform film thickness and film quality as seen in the epitaxial growth technique can be avoided. Therefore, the silicidation metal protrusion due to the nonuniformity of the film thickness and film quality is prevented, and a stable silicide layer can be formed. In addition, since part of the source / drain electrodes extends on the element isolation region, the coupling capacitance with the substrate is reduced, and the element can be operated at high speed.

In addition, silicidation is performed after As is adsorbed on the silicon layer, thereby improving the thermal stability of NiSi without causing damage to the silicon substrate. Even in a very shallow source / drain diffusion layer, junction leakage is prevented. Generation can be suppressed. Since the adsorption amount of As is automatically limited to 5 × 10 ¹⁴ cm ⁻² or less, the polarity of the p ⁺ source / drain region is not reversed, and can be stably applied to the manufacture of a CMOS circuit. .

  Further, since NiSi is formed by silicidation after forming the Ni layer on the surface on which As is adsorbed, the NiSi layer contains As, and the thermal stability of the NiSi layer on the source / drain regions. Improves. For this reason, heat treatment at about 500 ° C. in a nitrogen atmosphere is possible, and good electrical contact between the NiSi layer and the wiring metal is ensured.

  In addition, since the NiSi layer formed on the gate contains only As regardless of the polarity of the MOSFET, the resistivity of the upper NiSi of the gate polysilicon electrode connecting the n-MOSFET and the p-MOSFET is increased. A rise can be avoided. Furthermore, since the silicon layer containing As was converted to NiSi, the work function of NiSi approaches the center of the forbidden band of intrinsic silicon, and the range of potentials that can be applied can be expanded. As a result, it is possible to reduce the insulating film thickness for element isolation, and the fine element isolation can be realized by a shallower groove than the conventional one, so that the element isolation process is facilitated.

  In addition, by inserting Ti as a metal material having a barrier property between the wiring metal and NiSi, and performing sufficient heat treatment to realize a dense structure, impurities mixed during the formation of the wiring metal, For example, it can be prevented that F or the like mixed when filling a contact hole with W deteriorates NiSi. For this reason, the yield of electrical wiring is improved, and the advantage of forming silicide can be fully utilized.

(Modification)
In addition, this invention is not limited to embodiment mentioned above. The embodiments have been described using a set of complementary MOSFETs, but the present invention can be similarly applied to a plurality of sets of elements, and further to a group of elements forming a part of a semiconductor device. Needless to say, it can be applied selectively.

  Further, in the embodiment, the Elevated Source Drain structure having the local wiring structure has been described. However, the method of performing the adsorption of As before forming the NiSi is further improved by the epitaxial selective growth method for the normal MOSFET structure. Needless to say, the present invention can be similarly applied to the Elevated Source Drain structure using the.

  Further, in the embodiment, NiSi is formed by forming a Ni film and then forming a silicide, but the present invention is effective for any silicided metal whose inclusion of As improves thermal stability. That is, it is possible to use other than Ni as the metal formed on the silicon layer. Further, the silicon substrate for forming elements is not necessarily limited to a bulk substrate, and may be any substrate having a single crystal silicon layer on the surface.

  In addition, it goes without saying that the formation method of each layer, the conditions at that time, the film thickness, and the like can be appropriately changed according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

(Summary)
As described above, the present invention is characterized by adopting the following configuration.

That is, a semiconductor device according to the present invention includes a gate electrode formed on a silicon substrate via a gate insulating film, a sidewall insulating film formed on a side portion of the gate electrode, and the gate electrode corresponding to the gate electrode. A source / drain region formed in the silicon substrate; and an As-doped NiSi layer formed on the source / drain region, wherein the NiSi layer is locally located at the center in the film thickness direction. It has a maximum point, and the concentration of As atoms in the center in the film thickness direction is 1.25 × 10 ¹⁷ cm ⁻³ or more and 2.5 × 10 ¹⁸ cm ⁻³ or less.

  Here, preferred embodiments of the present invention include the following.

  (1) The silicide layer must be made of NiSi.

  (2) A metal material containing Ti is formed on the NiSi layer, constitutes part of the electrical wiring, and the depth of the source / drain region in the silicon substrate is 100 nm or less.

  (3) The semiconductor device is a p-type MOSFET.

  (4) A part of the silicide layer extends to the element isolation region.

  (5) A silicide layer is formed for a plurality of MOSFETs, and a part of the silicide layer electrically connects the sources or drains of different MOSFETs.

  (6) The silicide layer is also formed on the gate electrodes of a plurality of MOSFETs having different polarities.

  (7) The silicide layer is located above the semiconductor main surface on which the MOSFET channel is formed.

  (8) A silicon nitride film and a silicon oxide film are stacked on the silicide layer, and these are selectively etched to form a contact hole, and a metal material filling the same is provided.

  (9) The metal material is composed of a laminate of Ti and W.

The characteristic view which shows the relationship between pn junction depth and leakage current density. The characteristic view which shows the relationship between pn junction depth, leakage current density, and Ni density | concentration. The characteristic view which shows the relationship between pn junction depth at the time of implanting Ge ion, and Ni density | concentration. The characteristic view which shows the relationship between pn junction depth at the time of implanting As ion, and Ni density | concentration. The characteristic view which shows the relationship between As implantation amount at the time of implanting As ion, and leakage current density. The characteristic view which compares and compares the density | concentration of As contained in the silicon substrate in NiSi and under it with off-lattice As and on-lattice As. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning one Embodiment of this invention.

Explanation of symbols

100 ... p-type silicon substrate 100a ... p-type well region 100b ... n-type well region 101,102,103 ... element isolation region 111a, 112a, 111b, 112b ... n-type diffusion layer (source / drain extension region)
121a, 122a, 121b, 122b ... n-type diffusion layers (source / drain regions)
200, 200a, 200b ... Gate insulating film 300, 300a, 300b ... Gate electrode 301a, 302a, 301b, 302b ... Gate sidewall insulating film 400 ... Silicon film 401, 403 ... Silicon layer on source / drain region 402 ... Between elements Silicon layer 430a, 430b ... Additional silicon layer on gate 500 ... Ni film 501, 503 ... NiSi region on source / drain region 502 ... NiSi region between elements,
530a, 530b ... NiSi region on the gate 600 ... silicon nitride layer 700 ... silicon oxide film 701, 703 ... contact hole 800 ... Ti film 900 ... W film 1000 ... silicon oxide film 1001, 1002 ... groove 1100 ... Cu film 1200 ... silicon oxide film

Claims (5)

A gate electrode formed on a silicon substrate via a gate insulating film, a sidewall insulating film formed on a side portion of the gate electrode, and a source / drain formed in the silicon substrate corresponding to the gate electrode A region, and an As-doped NiSi layer formed on the source / drain region,
The NiSi layer has a local maximum point of As in the central portion in the film thickness direction, and the concentration of As atoms in the central portion in the film thickness direction is 2.5 × 10 ¹⁷ cm ⁻³ or more. A semiconductor device characterized by being ¹⁸ cm ⁻³ or less.   2. The semiconductor device according to claim 1, wherein the NiSi layer is formed by taking In adsorbed on the source / drain regions.   The semiconductor device according to claim 1, wherein the NiSi layer has a thickness of 30 nm or less.   2. The semiconductor device according to claim 1, wherein the NiSi layer is formed for a plurality of MOSFETs, and a part of the NiSi layer electrically connects between sources or drains of different MOSFETs. .   2. The semiconductor device according to claim 1, wherein the NiSi layer is also formed on gate electrodes of a plurality of MOSFETs having different polarities.

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