JP3420116B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art A DRAM is a memory that retains data on the principle that charges are stored in a capacitance generated due to the structure of a MOS transistor. In the DRAM, it becomes difficult to maintain the data retention time as the integration degree increases.

The data retention time of the DRAM is mainly determined by the np junction of the capacitance contact portion. One of the factors that increase the junction leak is a heavy metal contaminant element.

Heavy metal contaminant elements such as Fe, Ni, Cu, etc. form a solid solution in Si to form deep levels,
Further, when the solid solubility is exceeded, there is a problem in that it precipitates as silicide and deteriorates the bonding characteristics.

In general, heavy metal pollutant elements are mixed from LSI manufacturing equipment and materials used for LSI manufacturing. Therefore, these manufacturing equipments and materials should be thoroughly cleaned. However, since the cost required to maintain a stable cleanliness is enormous, a gettering technique is generally used to compensate for this.

The gettering technique recognizes that some heavy metal contaminating elements are present in Si and, if possible, from the operating region of the device (for example, the region where the np junction is formed). It is a technology to remove heavy metal pollutant elements.

The removed heavy metal pollutant element is trapped at a gettering site provided outside the operating region of the device in advance. Various methods are conventionally known as a metal contamination gettering technique using ion implantation. For example, there is a method in which phosphorus, boron, oxygen, silicon, etc. are implanted and then heat treatment is performed to generate secondary defects. All of them have gettering power for metal contamination.

In Japanese Patent Laid-Open No. 63-248159 (Prior Art 1), carriers generated in light receiving elements are gettered and used to prevent crosstalk between the light receiving elements. In addition, [JP-A-3-215943].
In (Prior example 2), it is used to getter a defect generated during heat treatment applied to form an element after forming a trench isolation groove.

In the prior art example 2, it is considered that interstitial silicon is probably gettered because the defects are generated during the heat treatment and the defects are generated from the corners of the groove.

By the way, as described above, as the DRAM is highly integrated, the allowable amount of heavy metal contamination is limited to a very low concentration range. For example, SIA (Semicond
uctor Industry Association Roadmap (The Nati
According to onal Technology Roadmap for Semiconductor), Fe is 10 ^{10 in} the generation of 0.18 micron rule.
It is required to be cm ^-3 or less.

Among the heavy metal contaminating elements, Cu and Ni are relatively easy to getter because they diffuse quickly in silicon. On the other hand, Fe is an element that diffuses slowly and is difficult to getter. As a method of effectively gettering Fe, a method of forming a high concentration B region on a p-type (B-doped) wafer and performing gettering as described below is known.

One is a method using a p / p ⁺ epi-wafer (M. Sano, S. Sumita, T. Shigematsu, and
N. Fujino, in Semiconductor Silicon, edited
byH.R.Huff, W. Bergholz, and K. Sumino (El
ectrochemical Society, Pennington, NJ, 1994),
(See p784).

The p / p ⁺ epi-wafer is a wafer in which a low-concentration B epitaxial layer is formed on a high-concentration B wafer, and is a method of gettering Fe on the high-concentration B wafer. According to this method, the device is formed in the epitaxial layer, so that it is not affected by Fe.

Another method is to implant B into a p-type (B-doped) wafer to form a gettering layer of Fe (PAStolk, JLBenton, DJEagl).
esham, DCJacobson, JYCheng, and JMPoate,
Appl. Phys. Lett. 68, 51 (1996)).

According to this method, the gettering layer is provided in a portion deeper than the device forming region. These reports indicate that the high concentration B region has a very strong Fe gettering force.

Therefore, when a transistor structure was formed on a p / p ⁺ wafer contaminated with a small amount of Fe and the diffusion layer leak was measured, the diffusion layer leak due to Fe contamination could be reduced even if p / p ⁺ was used. I couldn't.

The cause of this is understood as follows. That is, if there is no gettering site other than the high concentration B region, Fe is gettered there without any problem. The above report corresponds to this situation.

[0018]

However, when a transistor is formed, there is a gettering site other than the high concentration B region. As such, for example, P or As
There are an n-type diffusion layer formed by doping the element, an element isolation structure, and the like.

In these examples, other gettering sites work and Fe is not gettered in the high-concentration B region, but is gettered in the n diffusion layer and the element isolation structure, so that the diffusion layer leak cannot be reduced even in the p / p ⁺ wafer. It can be said that

Therefore, in order to improve the data retention characteristic of the DRAM, it is necessary to solve the problems described above.

An object of the present invention is to provide a structure of a semiconductor memory and a method of manufacturing the same for reducing a leak current of a diffusion layer of a memory cell.

[0022]

To achieve the above object, according to an aspect of, in the semiconductor memory according to the present invention, the diffusion layer of the memory cell is a semiconductor memory which is n-type, has an n-type region, the n-type The area must be at least the element isolation area.
That has been formed just below the p-type well under oxide film, the concentration of the n-type region is not lower than the concentration of the n-type diffusion layer, the n-type region, from the n-type diffusion layer strong
It is provided as a gettering region .

Further, in the semiconductor memory in which the diffusion layer of the memory cell is n-type, it has an n-type region, and the n-type region is formed at least directly under the p-type well below the oxide film to be the element isolation region. The volume of the n-type region is
It is not smaller than the volume of the mold diffusion layer.

The n-type region is provided as a gettering region stronger than the n-type diffusion layer of the memory cell.

The concentration of the n-type region is higher than that of the n-type diffusion layer, and the volume thereof is larger than that of the n-type diffusion layer.

The n-type region is formed by doping P, and the n-type diffusion layer 2 is formed by doping P and As.

Further, on the outside of the n-type diffusion layer beneath the capacitor electrode has a p-type well formed by doping B, the p
Type well is also formed under the element isolation region has an n-type region directly under the lower a and the p-type well of the isolation region, the n-type region is stronger getter than the n-type diffusion layer
It serves as a gettering layer provided as a ring region and reduces the leak current of the memory cell.

Further, in the method for manufacturing a semiconductor memory according to the present invention, the groove opening process, the ion implantation process, the oxide film forming process, the flattening process, and the n-type diffusion layer forming process are sequentially performed. In the manufacturing method, the groove opening process is a process of sequentially stacking an oxide film and a nitride film on a substrate on which a p-type well is formed, applying a resist to the stack, and opening a groove reaching the substrate by etching. The ion implantation process is a process of ion-implanting P to form an n-type region immediately below the p-type well under the etched groove.
The oxide film forming process is a process of forming a buried oxide film to be an element isolation structure, the flattening process is a process of flattening the buried oxide film, and the n-type diffusion layer forming process is a lower part of the element isolation region. Is a process for forming an n-type diffusion layer at a position corresponding to.

Further, in the ion implantation process, the implantation energy and the resist are P in the silicon other than the groove portion.
The conditions were chosen so that the ions would not be hit.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a semiconductor memory according to the present invention. The figure briefly shows the structure of the memory cell region. In this embodiment, the purpose is to reduce the junction leakage current of the n-type diffusion layer 2 below the capacitance electrode 1.

Therefore, in the present invention, the n-type diffusion layer 2 is provided under the capacitor electrode 1, and the p-type well 3 formed by doping B is provided outside the n-type diffusion layer 2.
Are also formed below the element isolation region 5.

The present invention is characterized in that the n-type region 4 is provided below the element isolation region 5 and immediately below the p-type well 3. This n-type region 4 becomes a gettering layer,
The leak current of the memory cell can be reduced.

If the n-type region 4 is not provided, heavy metal contamination is gettered to the n-type diffusion layer 2 and the leak current increases. In this example, the n-type diffusion layer 2 of the memory cell is P
It is formed by doping. In this respect, the conventional structure has a problem that the n-type diffusion layer 2 functions as a gettering site, resulting in a large leak current of the n-type diffusion layer 2 as described above.

The gettering strength of the diffusion layer is related to the P concentration. The reason is that when the P concentration is high, the solid solubility of the heavy metal element is high. Therefore, in the present invention, the n-type region 4 is provided as a gettering region stronger than the n-type diffusion layer 2 of the memory cell.

In order to make the n-type region 4 a gettering site stronger than the n-type diffusion layer 2, there are the following methods. For example, if the n-type region 4 has the same volume as the n-type diffusion layer 2,
This is a method of making the P concentration of the n-type region 4 higher than that of the n-type diffusion layer 2.

If the P concentration in the n-type region 4 is changed to the n-type diffusion layer 2
The gettering force is approximately doubled when the density is increased by one digit. The concentration can be designed by the dose of ion implantation and the diffusion depth by heat treatment.

There is another method in which the P concentration is the same and the volume of the n-type region 4 is larger than that of the n-type diffusion layer 2. According to this method, the gettering force becomes stronger in proportion to the volume ratio. The volume can be designed by the area of the element isolation region 5 and the depth after ion implantation. Practically, it is desirable to use a combination of these two methods.

That is, the P concentration of the n-type region 4 is set higher than that of the n-type diffusion layer 2 and the volume thereof is increased. Next, a method for manufacturing the structure of the semiconductor device as shown in FIG. 1 will be described with reference to FIG.

In the method of manufacturing a semiconductor memory according to the present invention, the groove opening process, the ion implantation process, the oxide film forming process, the flattening process, and the n-type diffusion layer forming process are sequentially performed.

In FIG. 2, the STI (S
The case of using (hallow Trench Isolation) is explained. FIG. 2A is a cross-sectional view at the time when the element isolation region 5 which will be the STI portion is etched.

That is, as a groove opening process, an oxide film 12 and a nitride film 13 are laminated on a wafer 11 which is a substrate, a resist 14 is attached to the laminated film, and the substrate 11 is etched.
Open the groove to reach. The p-type well 3 has already been formed. In FIG. 2B, next, as an ion implantation process, P is ion-implanted in order to form the n-type region 4 just below the p-type well under the etched groove.

At this time, conditions for the implantation energy and the resist are selected so that P ions are not implanted in the silicon other than the groove portion. Next, as an oxide film forming process, as shown in FIG. 2C, a buried oxide film 15 to be an element isolation region by STI is formed by CVD. After that, CMP (Chemical Mechanical P
The buried oxide film 15 is planarized by the polishing process.

Then, as an n-type diffusion layer forming process, an n-type diffusion layer is formed at a portion corresponding to the lower portion of the element isolation region. FIG. 2D shows the state at the time when the n-type diffusion layer 2 is formed. In the present invention, FIG. 1 and FIG.
As shown in, the n-type region 4 for gettering is
It is formed below the element isolation region. The method of FIG. 2 has the following advantages.

That is, since the n-type region 4 is formed in the portion where the groove is formed in advance, the energy of ion implantation can be reduced. Therefore, the possibility that crystal defects will occur in the well portion immediately above the n-type region 4 is reduced. In addition, at the stage of the ion implantation process for forming the n-type region 4, no ions are hit in the region that will become the n-type diffusion layer 2, which may adversely affect the n-type diffusion layer 2 that is formed later. There is no.

[0045]

EXAMPLE The following example is an example of manufacturing a semiconductor memory using the method shown in FIG. A specific manufacturing method will be described in detail with reference to FIG. The same components as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 3A, the depth of the STI groove formed by the groove opening process is 400 nm. In order to form the n-type region 4 in this groove portion, as the ion implantation process, P ions are dosed at 2 × 10 ¹⁵ cm ⁻² ,
Injected with energy 1.5 MeV. (Fig. 3 (b)).

After the implantation, as the oxide film forming process, the resist was peeled off and buried by CVD to form the oxide film 15 (FIG. 3C). Next, as a planarization process, the embedded oxide film 15 was planarized by CMP (FIG. 3D).

Next, the nitride film 13 was removed, and B for transistor threshold value adjustment was ion-implanted prior to the n-type diffusion layer forming process (FIG. 3 ( e )). Then, the structure of the gate oxide film 16 and the gate electrode 17 was formed ( FIG.3 ( f )).

Next, the n-type diffusion layer 2 was formed, and the capacitor lower electrode was formed of P-doped polysilicon (FIG. 3).
( g )). The n-type diffusion layer 2 doses P ions 3 × 10 3.
^The implantation was performed under the conditions of ¹³ cm ^-2 and energy of 50 KeV. The junction leak characteristic was measured by pulling out the polysilicon used for the lower electrode of the capacitor and forming a PAD electrode.

However, the area of the n-type diffusion layer 2 was measured in a pattern of a large order of 1 mm ² so that it could be directly measured by a prober. The data retention characteristics were measured by making a 64 Mbits DRAM by the same method.

After forming the capacitor lower electrode , a MIS type stack type capacitor was formed. An element isolation region, n
The area ratio to the type diffusion layer 2 was set to almost 1 for both the pattern for measuring the junction leak and the DRAM for measuring the data retention characteristic.

For reference, one having no n-type region 4 in the above-described process was manufactured as a comparative example. For wafer, p / p ⁺
An epi-wafer and p-type Cz were used. p + substrate, the B concentration of the p-type Cz and p-type epitaxial layer at a B concentration 10 ^{1 9} cm about ^-3 is approximately 10 ¹⁵ cm ^-3.

The reason why the leak current of the n-type diffusion layer 2 can be reduced by manufacturing the structure shown in FIG. 1 will be described below. The cause of the leak current is a defect existing in the depletion layer at the junction of the n-type diffusion layer 2 and the p-type well. This defect is a defect in a broad sense, and among them, there are crystal defects caused by ion implantation and dry etching damage,
There are oxygen precipitates and heavy metal contamination.

Heavy metal contamination forms a deep level as a point defect even if it is in solid solution. If this cannot form a solid solution and forms a silicide, it is fatal as a semiconductor memory. In addition, defects caused by ion implantation or dry etching damage may become a problem because heavy metal contamination is caught.

According to the present invention, defects due to heavy metal contamination in the depletion layer can be reduced. Heavy metal element (Fe,
Cu, Ni, etc. diffuse considerably faster in Si than the dopants (P, As, B, etc.). Still, there are various problems in diffusing from the device region to gettering.

Among the heavy metal elements, Fe is a problem because it diffuses slowly and is difficult to getter. As a method of efficiently gettering Fe, there is a method of using a high concentration B layer as a gettering layer.

Of course, since this high concentration B layer is higher than the B concentration of the p-type well forming the np junction, it is possible to prevent gettering to the p-type well.

However, the gettering force of the n-type diffusion layer is
Stronger than the high-concentration B layer. Therefore, in the n-type diffusion layer 2 and n
Fe increases in the p-type well near the type diffusion layer 2.
As a result, the junction leak increases.

Most of the thickness of the p / p ⁺ wafer is the p ⁺ substrate, and the gettering force cannot be increased by increasing the thickness or increasing the B concentration of the p ⁺ substrate. .

In the present invention, the n-type region 4 is formed as a gettering site stronger than the n-type diffusion layer 2. As described above, Fe diffuses slowly from the viewpoint of gettering. Therefore, it is desirable that the n-type region 4 is arranged near the n-type diffusion layer 2.

In this embodiment, the junction depth between the n-type diffusion layer 2 and the p-type well 3 is about 0.2 μm, and the n-type region 4 is formed.
Is about 1.5 microns deep. Therefore, it is sufficient that Fe can diffuse by 1.3 μm.

Further, in the experiment by the inventor, it was found that the gettering force of the n-type diffusion layer 2 and the n-type region 4 is determined by the P concentration and the volume of the n-type portion. In this embodiment, the area ratio between the n-type diffusion layer 2 and the n-type region 4 is 1 as described above, but the dose amount ratio is almost 100. as a result,
The gettering force of the n-type region 4 is definitely stronger than that of the n-type diffusion layer 2.

Since it is not possible to say that the cause of the leak current is all heavy metal elements and most of them are Fe, it is difficult to quantitatively explain. Therefore, it is assumed that the gettering force has increased 100 times. That is, 10 ¹² cm
^If there is ^-3 heavy metal contamination, the concentration of heavy metal contamination in the n-type diffusion layer 2 can be about 10 ¹⁰ cm ^-3 .

With this method, the concentration in the n-type diffusion layer 2 can be reduced by two orders of magnitude compared to the amount of heavy metal contamination existing in the production line by cleaning the LSI manufacturing process.

Further, in the case of the conventional structure, since the heavy metal contamination during the diffusion which is gettered to the n-type diffusion layer 2 exists, the contamination concentration in the p-type well also becomes high.

According to the present invention, since the heavy metal contamination diffused toward the n-type diffusion layer 2 is reduced, the contamination concentration in the p-type well 3 is also reduced. For the above reasons, the amount of heavy metal contamination in the np junction depletion layer in question is reduced and the junction leak is reduced. As a result, it is possible to improve the DRAM data retention characteristic where the junction leak is dominant.

FIG. 4 (a) shows a comparison of the current-voltage characteristics of the junction leak in the junction area of 1 mm ² according to the present invention and the conventional example. As is clear from the figure, according to the present invention, the effect of reducing the junction leak is remarkable especially on the low voltage side.

FIG. 4B shows a comparison of the holding characteristics of the DRAM of the present invention and the conventional example. As you can see in the figure,
According to the present invention, it can be seen that the data retention characteristic of DRAM is improved.

In the above embodiment, both the n-type diffusion layer 2 and the n-type region 4 are formed by doping P. However, the present invention is also effective when the n-type diffusion layer 2 is formed by doping As. For P and As, the gettering of the n-type diffusion layer 2 is higher when P is doped.

Therefore, when the n-type diffusion layer 2 is formed by doping As, it is possible to more easily getter the n-type region 4 formed by doping P.

The ratio of the n-type diffusion layer 2 and the dose of the n-type region 4 is about 100 times, and the ratio of the n-type region 4 is higher. Since the absolute value of the amount of contamination in the target depletion layer is a problem, when the manufacturing line is cleaned and the total amount of contamination is reduced, the n-type region 4 is reduced even if the dose ratio is further lowered. The gettering effect of will be satisfactory.

When the amount of contamination on the manufacturing line is very small, even a dose ratio of 1 is effective. On the contrary, when the amount of contamination in the production line is large, it is better to increase the dose ratio.

In the above embodiment, the element isolation structure is S
Although it has a TI structure, the present invention is not limited to the recess LOCOS.
The structure is also effective. In the case of recess LOCOS structure,
LOCOS After etching the area to be oxidized, LOC
Before the OS oxidation, P is ion-implanted to form an n-type region.

[0074]

As described above, according to the present invention,
The gettering ability of heavy metal contamination is improved, and the np junction leak can be reduced. In addition, an excellent junction leak reduction effect can be obtained especially on the low voltage side. Furthermore, according to the invention, D
It also has the effect of improving the data retention characteristics of the RAM.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a semiconductor memory according to the present invention.

FIG. 2 is a diagram showing a step of forming an n-type region below an element isolation region by using STI for an element isolation structure.

FIG. 3 is a diagram showing a step-by-step process of manufacturing a semiconductor memory according to the present invention.

FIG. 4A is a graph showing a comparison between current-voltage characteristics of a junction leak having a junction area of 1 mm ² according to the present invention and a conventional example. (B) is a graph showing a comparison of the retention characteristics of the DRAM of the present invention and the conventional example.

[Explanation of symbols]

1 capacitance electrode 2 n-type diffusion layer 3 p-type well 4 n-type region 5 element isolation region 11 wafers 12 Oxide film 13 Nitride film 14 Resist 15 Embedded oxide film 16 Gate oxide film 17 Gate electrode

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Claims (8)

(57) [Claims] 1. A semiconductor memory in which a diffusion layer of a memory cell is an n-type and has an n-type region, wherein the n-type region is at least directly under a p-type well below an oxide film to be an element isolation region. Formed, and n
The concentration of the mold region is lower than that of the n-type diffusion layer.
The n-type region is stronger than the n-type diffusion layer.
A semiconductor memory, which is provided as a storage area. 2. A semiconductor memory in which a diffusion layer of a memory cell is n-type and has an n-type region, the n-type region being formed at least directly under a p-type well below an oxide film to be an element isolation region. The semiconductor memory according to claim 1, wherein the volume of the n-type region is not smaller than the volume of the n-type diffusion layer. 3. The semiconductor memory according to claim 2 , wherein the n-type region is provided as a gettering region stronger than the n-type diffusion layer of the memory cell. Concentration of wherein n-type region is higher than the concentration of n-type diffusion layer, and volume, as claimed in any one of claims 1 to 3 and greater than n-type diffusion layer Semiconductor memory. 5. The n-type region is formed by doping P, and the n-type diffusion layer is formed by doping P and As. 4. The semiconductor memory according to item 4. 6. B outside the n-type diffusion layer below the capacitance electrode
Doped has a p-type well formed by the p-type well is also formed under the element isolation region has an n-type region directly under the lower a and the p-type well of the isolation region ,
The n-type region has stronger gettering than the n-type diffusion layer.
A semiconductor memory, which serves as a gettering layer provided as a region and reduces a leak current of a memory cell. 7. A method of manufacturing a semiconductor memory, which comprises sequentially performing a groove opening process, an ion implantation process, an oxide film forming process, a planarizing process, and an n-type diffusion layer forming process, the groove opening process comprising: An oxide film and a nitride film are sequentially laminated on a substrate on which a p-type well is formed, a resist is applied to the laminated film, and a groove reaching the substrate is opened by etching. Ion implantation is performed under the etched groove. In order to form an n-type region directly under the p-type well, P is ion implantation processing, oxide film formation processing is formation of a buried oxide film to be an element isolation structure, and planarization processing is A method of manufacturing a semiconductor memory, which is a process of planarizing a buried oxide film, and the n-type diffusion layer forming process is a process of forming an n-type diffusion layer at a portion corresponding to a lower portion of an element isolation region. 8. In the ion implantation process, the implantation energy and the resist are selected such that P ions are not implanted in silicon other than the groove portion. Item 8. A method of manufacturing a semiconductor memory according to item 7.