JP2001007256A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent warpage of a semiconductor integrated circuit device by arranging first sealing resin for sealing a semiconductor chip and wiring at a first main surface side and at the same time, sealing a second main surface side where a plurality of leads are formed with second sealing resin. SOLUTION: After a brazing material 4 that is a liquid adhesive material of a solvent volatile type at a die attach, a semiconductor chip 5 is mounted before the brazing material 4 is cured for curing the brazing material 4, and the semiconductor chip 5 is sealed to the die attach 3. Then, the semiconductor chip 5 and a lead 1 are electrically connected via metal wiring 6, so that an electrical signal can be inputted or outputted from the outside of the semiconductor integrated circuit device to the semiconductor chip 5 via the lead 1. After that, the reverse side of the die attach 3, where no semiconductor chips 5 are mounted, is sealed by second sealing resin 8, thus preventing warpage of the semiconductor integrated circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for preventing warpage of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a semiconductor integrated circuit chip (hereinafter, referred to as a semiconductor chip) is sealed in a ceramic package having excellent heat resistance or resin-sealed with a sealing resin. Except for special markets, when comparing semiconductor integrated circuit devices that are distributed in general markets in terms of quantity, most of the semiconductor integrated circuit devices are resin-sealed with a sealing resin. This is because a semiconductor integrated circuit device can be manufactured at low cost.

Hereinafter, a conventional technique for a semiconductor integrated circuit device sealed with a sealing resin will be described with reference to FIGS. 10 and 11. FIG.

FIG. 10 is a diagram schematically showing a so-called assembly process of a process of manufacturing a semiconductor integrated circuit device sealed with a sealing resin. 10A to 10G show the transition of the assembly process of the semiconductor integrated circuit device.
Starting from the step (a), the steps proceed in the order from the step (b) to the step (g). In each of the steps (a) to (g) of FIG. 10, a top view and a cross-sectional view taken along line AA are shown.

In FIG. 10, reference numeral 5 denotes a semiconductor chip. Reference numeral 1 denotes a lead which is electrically connected to the semiconductor chip 5 and whose outer end portion serves as an external connection terminal of the semiconductor integrated circuit device. Reference numeral 6 denotes a metal wiring for electrically connecting the semiconductor chip 5 and the lead 1. 7 is a first sealing resin. Reference numeral 2 denotes a tie bar for temporarily stopping the flow of the sealing resin and temporarily holding the lead 1 before cutting. Reference numeral 3 denotes a die attach for mounting the semiconductor chip 5. Reference numeral 4 denotes a wax material for bonding the semiconductor chip 5 to the die attach 3.

Incidentally, the configuration shown in FIG.
Only one unit of a lead required for manufacturing one semiconductor integrated circuit device is shown. That is, usually, in order to increase the productivity, a plurality of the configurations shown in FIG. 10A are formed in a plate shape (frame shape). The plate-shaped lead is particularly called a lead frame. FIG. 11 illustrates a top view of the lead frame and a cross-sectional view taken along line AA.
In the following description, an assembly for mounting the semiconductor chip 5 on the die attach 3 is referred to as a die attach method.

Hereinafter, each assembly process of the semiconductor integrated circuit device by the die attach method will be described in order.

First, a die attach sinking step (b) for forming a depression in the die attach 3 is performed. This step (b)
This is a step of using a press die (not shown) to form a recess in which the semiconductor chip 5 is half inserted into the die attach 3. The press die used at this time is a press die provided exclusively for manufacturing a certain semiconductor integrated circuit device.

Next, an adhesive material disposing step (c) for disposing an adhesive material is performed on the die attach 3 on which the step (b) has been performed. The wax material 4 used in this step (c) is a liquid adhesive material for adhering the die attach 3 and the semiconductor chip 5, and is mostly a solvent-evaporating adhesive material or a rarely used one. Solder is used.

Next, the semiconductor chip 5 is inserted through the brazing material 4.
Is mounted on the die attach 3 (d). In this step (d), after the brazing material 4 is provided, the semiconductor chip 5 is mounted before the brazing material 4 is solidified. After the evaporation of the solvent, the brazing material 4 solidifies, so that the semiconductor chip 5 adheres to the die attach 3.

Next, a wiring step (e) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed. Thereby, the semiconductor chip 5 and the lead 1 are electrically connected via the metal wiring 6. Electrical signals can be input and output from the outside of the semiconductor integrated circuit device to the semiconductor chip 5 through the leads 1.

Next, a sealing step (f) of resin-sealing the semiconductor chip 5 with the first sealing resin 7 is performed so that the semiconductor integrated circuit device can be easily handled. First sealing resin 7
Is, for example, an epoxy resin. The lead frame that has been subjected to the wiring step (e) is placed in a mold (not shown) and sealed. After that, the inside of the sealed mold is filled with the first sealing resin 7, and the filled first sealing resin 7 is heated and thermally cured.

Finally, the tie bar 2 is cut, a plurality of semiconductor integrated circuit devices manufactured on a lead frame are individually cut, and the leads 1 protruding from the sealing resin are bent to connect the semiconductor integrated circuit device to the external connection. A terminal forming step (g) for forming a terminal is performed. By this step (g), the semiconductor integrated circuit device is completed.

Recently, lead frames without die attach 3 have been developed and commercialized. In this case, the semiconductor chip 5 is directly mounted on the lead 1 extending to near the center. This method is referred to as a chip-on-read method (COL method) in the following description. The COL type semiconductor integrated circuit device can have a smaller sealing shape than the die attach type semiconductor integrated circuit device because of the absence of the die attach 3.
With the advantage that.

FIG. 12 shows a COL sealed with a sealing resin.
FIG. 4 is a diagram showing an assembly process of a semiconductor integrated circuit device according to a method. In FIG. 12, reference numeral 9 denotes a film sheet for mounting the semiconductor chip 5 on the lead 1. This film sheet 9 is an adhesive material having tackiness on both sides. Other configurations are the same as the die attach method.

Hereinafter, each assembly process of the COL type semiconductor integrated circuit device will be described. First, a lead sinking step (b) is performed using a press die to form a recess in the lead 1 such that the semiconductor chip 5 is half inserted. Note that the lead sinking step (b) is a step of forming a depression in the lead 1 in the same manner as the die attach 3 of the die attach sinking step. The work of making a dent is complicated, and the jigs (press dies) used for the work are more expensive.

Next, an adhesive material disposing step (c) for disposing the film sheet 9 in the recess formed in the lead 1 is performed. The film sheet 9 used in this step (c) has adhesiveness on both sides of the film, and the lead 1 and the semiconductor chip 5 are adhered by utilizing the adhesiveness.

Next, a mounting step (d) for mounting the semiconductor chip 5 on the film sheet 9 is performed.

In the case of the die attach method, the liquid wax material 4 is used as an adhesive material. In the case of the COL method, a film sheet 9 is used. Although the wax material 4 used in the die attach method has a certain degree of viscosity, it is in a liquid state before it is solidified, so that the wax material 4 drips from the gap between the leads 1. Therefore, the brazing material 4 cannot be used in the COL system. Therefore, a film sheet 9 having an adhesive force is provided between the lead 1 and the semiconductor chip 5 on both sides of the film, and the semiconductor chip 5 is mounted on the lead 1 via the film sheet 9.

Next, similarly to the die attach method, a wiring step (e) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed.

Next, similarly to the die attach method, the first sealing resin 7 is used to facilitate the handling of the semiconductor integrated circuit.
To perform a sealing step (f) for resin sealing.

Finally, similarly to the die attach method, the tie bar 2 is cut, a plurality of semiconductor integrated circuit devices manufactured on the lead frame are individually cut, and the leads 1 projecting from the sealing resin are bent. A terminal forming step (g) of forming an external connection terminal of the semiconductor integrated circuit device is performed.

[0023]

The present semiconductor integrated circuit device is manufactured by the above-described assembly process. However, the first sealing resin 7 and the semiconductor chip 5
The physical properties, particularly the thermal expansion coefficient, are different, and the semiconductor integrated circuit device is warped. If the semiconductor integrated circuit device has a warp, when incorporating it into an electronic circuit board,
The external connection terminals of the semiconductor integrated circuit device are separated from the lands of the electronic circuit board and cannot be mounted properly.

[0024]

A semiconductor integrated circuit device according to a first aspect of the present invention includes a plurality of leads, a semiconductor chip disposed on a first main surface formed by the leads, the leads and the semiconductor. A metal wiring electrically connecting the chip, a first sealing resin disposed on the first main surface side to seal the semiconductor chip and the wiring, and a second wiring formed by the lead. A second sealing resin for sealing the main surface side.

In the semiconductor integrated circuit device according to the second invention, the first sealing resin has a larger coefficient of thermal expansion than the second sealing resin.

A semiconductor integrated circuit device according to a third aspect of the present invention is a semiconductor integrated circuit device comprising: a plurality of leads; a semiconductor chip disposed on a first main surface formed by the leads; and electrically connecting the leads and the semiconductor chip. A metal wiring to be connected; a first sealing resin disposed on the first main surface side to seal the semiconductor chip and the wiring; and a second formed by the lead.
And a second sealing resin that is disposed on the second main surface side and seals the plate-shaped member.

In a semiconductor integrated circuit device according to a fourth aspect of the present invention, the plate member has the same shape as the semiconductor chip and has the same coefficient of thermal expansion.

A semiconductor integrated circuit device according to a fifth aspect of the present invention is a semiconductor integrated circuit device comprising: a plurality of leads; a semiconductor chip disposed on a first main surface formed by the leads; and electrically connecting the leads and the semiconductor chip. A metal wiring to be connected, a first sealing resin disposed on the first main surface side to seal the semiconductor chip and the wiring, and a second main surface side formed by the lead to the second main surface. And a second sealing resin for sealing to a thickness different from that of the first main surface side.

In a semiconductor integrated circuit device according to a sixth aspect, the first sealing resin is formed thicker than the second sealing resin.

In the semiconductor integrated circuit device according to the seventh aspect, the bending stress on the first main surface side and the bending stress on the second main surface side are balanced at room temperature.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit device, a step of arranging a plate member on the second principal surface side on which a plurality of leads are formed, and a step of arranging the plate member Arranging a semiconductor chip on the first main surface side on which a plurality of leads are formed.

A method of manufacturing a semiconductor integrated circuit device according to a ninth aspect of the present invention includes a step of forming a second sealing resin on a second main surface side on which a plurality of leads are formed; Arranging a semiconductor chip on the first main surface side on which a plurality of leads are formed after the forming step.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

Embodiment 1 Using FIGS. 1 and 2,
Embodiment 1 will be described.

FIG. 1 is a view showing an assembly process of a semiconductor integrated circuit device by a die attach method, which is sealed with a sealing resin. In FIG. 1, (a) to (g) show the transition of the assembly process of the semiconductor integrated circuit device. Process
Starting from (a), the steps proceed from step (b) to step (g). In each of the steps (a) to (g) of FIG. 1, a top view and a cross-sectional view taken along line AA are shown. In FIG. 1, reference numeral 5 denotes a semiconductor chip. 1 is a semiconductor chip 5
Are electrically connected to each other, and their outer ends are leads serving as external connection terminals of the semiconductor integrated circuit device. Reference numeral 6 denotes a metal wiring for electrically connecting the semiconductor chip 5 and the lead 1. 7 is a first sealing resin. 8 is a second sealing resin. Reference numeral 2 denotes a tie bar for temporarily stopping the flow of the sealing resin and temporarily holding the lead 1 before cutting. Reference numeral 3 denotes a die attach for mounting the semiconductor chip 5. Reference numeral 4 denotes a wax material for bonding the semiconductor chip 5 to the die attach 3. Note that the configuration shown in the step (a) of FIG. 1 shows only one unit of lead required to manufacture one semiconductor integrated circuit device, and usually increases productivity. For this purpose, a plurality of them are formed in a plate shape (frame shape).
The plate-shaped lead is particularly called a lead frame.

Hereinafter, each assembly process will be described in order.
First, an adhesive material disposing step (b) of disposing an adhesive material on the die attach 3 is performed. The wax material 4 used in this step (b) is a solvent-evaporating type liquid adhesive material for adhering the die attach 3 and the semiconductor chip 5, and solidifies after the solvent evaporates.

Next, a mounting step (c) for mounting the semiconductor chip 5 on the die attach 3 is performed. After the brazing material 4 is provided, the semiconductor chip 5 is mounted before the brazing material 4 solidifies. When the brazing material 4 solidifies, the semiconductor chip 5 is fixed to the die attach 3.

Next, a wiring step (d) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed. Thereby, the semiconductor chip 5 and the lead 1 are electrically connected via the metal wiring 6. Electrical signals can be input and output from the outside of the semiconductor integrated circuit device to the semiconductor chip 5 through the leads 1.

The first embodiment is different from the prior art in that steps (e) and (f) described later are performed. Thus, it will be understood that the semiconductor integrated circuit device can prevent warpage.

Next, the back surface (hereinafter, referred to as a second main surface) of the die attach 3 on which the semiconductor chip 5 is not mounted is
Second sealing step of resin sealing using second sealing resin 8
Perform (e). The second sealing resin 8 is, for example, Kevlar epoxy resin.

The sealing step (e) will be described with reference to FIG. In FIG. 2, reference numeral 51 denotes a first mold piece. 52
Is a first sealing resin inlet provided in the first mold piece. Reference numeral 53 denotes an exhaust port provided in the first mold piece 51. 54 is a second mold piece. Reference numeral 55 denotes a second sealing resin injection port provided in the second mold piece 54. The first mold piece 51 and the second mold piece 54 constitute a set of molds.

As shown in FIG. 2B, the lead frame having undergone the wiring step (d) is placed in a mold composed of the first mold piece 51 and the second mold piece 54. The inside of the mold is closed via a tie bar 2. Thereafter, the second sealing resin 8 heated and melted was provided on the second mold piece 54 while slowly sucking out the gas inside the mold from the exhaust port 53 provided on the first mold piece 51. It is injected from the second sealing resin injection port 55. By controlling the discharge amount of the gas inside the mold exhausted from the exhaust port 53, it is possible to control the injection amount of the second sealing resin 8 injected into the mold. The inside of the mold is vertically symmetric with respect to the lead frame.

Returning to FIG. Next, a first sealing step (f) of resin-sealing the surface (hereinafter, first main surface) side of the lead 1 on which the semiconductor chip 5 is mounted with the first sealing resin 7. Is carried out. First sealing resin 7
Is, for example, an epoxy resin.

After performing the second sealing step (e), FIG.
As shown in (c), the first sealing resin 7 heated and melted while the gas inside the mold is slowly sucked out from the exhaust port 53 provided in the first mold piece 51 is removed from the first mold piece 51. The resin is injected from a first sealing resin injection port 52 provided in the piece 51. By controlling the amount of gas discharged inside the mold exhausted from the exhaust port 53, it is possible to control the amount of the first sealing resin 7 injected into the mold.

Next, after injecting the first sealing resin 7 and the second sealing resin 8, they are heated to about 150 ° C. in a state of being sealed in the mold, and are then filled with the first sealing resin 7. 7 and the second sealing resin 8 are thermally cured. As a result, the first main surface side is resin-sealed with the first sealing resin 7 and the second main surface side is resin-sealed with the second sealing resin 8. Thereafter, the lead frame is removed from the mold.

Finally, the tie bar 2 is cut, a plurality of semiconductor integrated circuit devices manufactured on a lead frame are cut individually, and the leads 1 projecting from the sealing resin are bent to connect the external connection terminals of the semiconductor integrated circuit device. A terminal forming step (g) for forming is performed.

Next, the operation will be described. Semiconductor chip 5, first sealing resin 7, and second sealing resin 8
Have different coefficients of thermal expansion.

The thermal expansion coefficient of the first sealing resin 7 is about 1.
05 × 10 ⁻⁵ [° C. ⁻¹ ]. The thermal expansion coefficient of the second sealing resin 8 is about 1.0 × 10 ⁻⁵ [° C. ⁻¹ ]. The thermal expansion coefficient of the semiconductor chip 5 is about 4.0 × 10 ⁻⁶ [° C. ⁻¹ ]. That is, the magnitude relationship between the respective thermal expansion coefficients is as follows: first sealing resin> second sealing resin >> semiconductor chip.

The first sealing resin 7 and the second sealing resin 8 are thermoset by heating to seal the semiconductor chip 5 with resin. Furthermore, these members including the semiconductor chip 5 have different thermal expansion coefficients when cooled to room temperature, and therefore have different shrinkage amounts.

On the first main surface side, a first sealing resin 7 having a large thermal expansion coefficient and a semiconductor chip 5 having a small thermal expansion coefficient are provided.
And are arranged. On one second main surface side, a second sealing resin 8 having a coefficient of thermal expansion between the former two coefficients of thermal expansion is provided. Therefore, the difference between the total amount of shrinkage on the first main surface side and the total amount of shrinkage on the second main surface side is reduced, and the balance can be substantially achieved.

Therefore, at normal temperature, the bending stress inside the semiconductor integrated circuit device is balanced, and the warpage of the semiconductor integrated circuit device can be reduced.

In the above description of the assembly process,
Although the die attach sunk is not performed, the same is true when the die attach is performed. Although two types of sealing resins having different coefficients of thermal expansion are used, the elasticity of the sealing resins may be different.

According to the first embodiment, since two types of sealing resins having different physical properties, for example, different coefficients of thermal expansion, are used as the sealing resin of the semiconductor integrated circuit device, the first main surface side and the first main surface side are different from each other. The bending stress of the semiconductor integrated circuit device can be substantially balanced between the main surface side and the second main surface side. For this reason,
The bending stress of the semiconductor integrated circuit device is balanced, and the warpage is reduced.

Embodiment 2 Embodiment 2 will be described with reference to FIG.

FIG. 3 is a view showing an assembly process of a semiconductor integrated circuit device according to the COL method. Each step in FIG.
(a)-(g) have shown the transition of an assembly process. Starting from the step (a), the steps proceed in the order from the step (b) to the step (g). In FIG. 3, reference numeral 5 denotes a semiconductor chip. Reference numeral 1 denotes a lead that is electrically connected to the semiconductor chip 5 and serves as an external connection terminal of the semiconductor integrated circuit device. 6
Is a metal wiring for electrically connecting the semiconductor chip 5 and the lead 1. 7 is a first sealing resin. 8
Is a second sealing resin. 2 prevents the first sealing resin 7 and the second sealing resin 8 from flowing, and the lead 1 before cutting.
Is a tie bar for temporarily holding the tie bar. 9 is a film sheet for mounting the semiconductor chip 5 on the lead 1. This film sheet 9 is an adhesive material having tackiness on both sides.

Hereinafter, each assembly process will be described in order.
First, an adhesive material disposing step (b) for disposing the film sheet 9 on the lead 1 is performed. The film sheet 9 is a sheet-like adhesive material for mounting the semiconductor chip 5 on the leads 1.

Next, the semiconductor chip 5 is attached to the film sheet 9.
Mounting step (c) on the lead 1 via
Is carried out. After arranging the film sheet 9 on the lead 1,
The semiconductor chip 5 is mounted on the film sheet 9, and the semiconductor chip 5 and the lead 1 are bonded.

Next, a wiring step (d) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed. The description is omitted because it is the same as in the first embodiment.

The second embodiment is different from the prior art in that steps (e) and (f) described later are performed. Thus, the COL type semiconductor integrated circuit device
It will be appreciated that bowing can be prevented.

Next, the second main surface side is connected to the second sealing resin 8.
A second sealing step (e) of resin sealing is performed using
The second sealing resin 8 is, for example, Kevlar epoxy resin. Refer to Embodiment 1 for details regarding the injection of the sealing resin.
Therefore, the description is omitted.

Next, the first main surface side is placed on the first sealing resin 7.
A first sealing step (f) of resin sealing is performed using
The first sealing resin 7 is, for example, an epoxy resin.

As in the first embodiment, the first sealing resin 7
After injecting the first sealing resin 7 and the second sealing resin 8, the lead frame is sealed in the mold and heated to about 150 ° C. Heat cured.

Finally, the tie bar 2 is cut, a plurality of semiconductor integrated circuit devices manufactured on a lead frame are individually cut, and the leads 1 projecting from the sealing resin are bent to connect the external connection terminals of the semiconductor integrated circuit device. A terminal forming step (g) for forming is performed.

Next, the operation will be described. Semiconductor chip 5, first sealing resin 7, and second sealing resin 8
Have different coefficients of thermal expansion.

The thermal expansion coefficient of the first sealing resin 7 is about 1.
05 × 10 ⁻⁵ [° C. ⁻¹ ]. The thermal expansion coefficient of the second sealing resin 8 is about 1.0 × 10 ⁻⁵ [° C. ⁻¹ ]. The thermal expansion coefficient of the semiconductor chip 5 is about 4.0 × 10 ⁻⁶ [° C. ⁻¹ ]. That is, the magnitude relationship between the respective thermal expansion coefficients is as follows: first sealing resin> second sealing resin >> semiconductor chip.

The first sealing resin 7 and the second sealing resin 8 are thermoset by heating to seal the semiconductor chip 5 with resin. Furthermore, these members including the semiconductor chip 5 have different thermal expansion coefficients when cooled to room temperature, and therefore have different shrinkage amounts.

A first sealing resin 7 having a large thermal expansion coefficient and a semiconductor chip 5 having a small thermal expansion coefficient are provided on the first main surface side.
And are arranged. On one second main surface side, a second sealing resin 8 having a coefficient of thermal expansion between the former two coefficients of thermal expansion is provided. Therefore, the difference between the total amount of shrinkage on the first main surface side and the total amount of shrinkage on the second main surface side is reduced, and the balance can be substantially achieved.

Therefore, at normal temperature, the bending stress in the semiconductor integrated circuit device is balanced, and the warpage of the semiconductor integrated circuit device can be reduced.

In the above description of the assembly process,
Although lead sinking is not performed, the same applies when lead sinking is performed. Although two types of sealing resins having different coefficients of thermal expansion are used, the elasticity of the sealing resins may be different.

According to the second embodiment, the encapsulation resin of the COL type semiconductor integrated circuit device has physical properties, for example,
Since two types of sealing resins having different thermal expansion coefficients are used, the bending stress of the semiconductor integrated circuit device can be substantially balanced between the first main surface side and the second main surface side. . Therefore, the warpage of the semiconductor integrated circuit device is reduced.

Embodiment 3 Embodiment 3 will be described with reference to FIG.

FIG. 4 is a view showing an assembly process of a semiconductor integrated circuit device according to the COL method. Each step in FIG.
(a)-(g) have shown the transition of an assembly process. Starting from the step (a), the steps proceed in the order from the step (b) to the step (g). In FIG. 4, reference numeral 5 denotes a semiconductor chip. Reference numeral 1 denotes a lead that is electrically connected to the semiconductor chip 5 and serves as an external connection terminal of the semiconductor integrated circuit device. 6
Is a metal wiring for electrically connecting the semiconductor chip 5 and the lead 1. 7 is a first sealing resin. 8
Is a second sealing resin. 2 prevents the first sealing resin 7 and the second sealing resin 8 from flowing, and the lead 1 before cutting.
Is a tie bar for temporarily holding Reference numeral 4 denotes a brazing material for bonding the semiconductor chip 5 to the leads 1.

In the third embodiment, prior to performing the adhesive material disposing step (b) for disposing the film sheet 9 in the second embodiment, the second sealing resin 8 in the second embodiment is removed. The second embodiment differs from the second embodiment in that a second sealing step (e) is performed.

First, a second sealing step (b) of resin-sealing the second main surface side with the second sealing resin 8 is performed. The step (b) of forming the second sealing resin 8 in the third embodiment is the same as the step (e) in the second embodiment, and a description thereof will be omitted.

The third embodiment is different from the second embodiment in that a liquid adhesive material is used instead of the film sheet 9 as an adhesive material for bonding the semiconductor chip 5.

Next, an adhesive material disposing step of disposing the brazing material 4
Perform (c). The bonding material providing step (c) in the third embodiment is the same as the bonding material providing step (b) in which the brazing material 4 in the first embodiment is provided.

Next, a mounting step (d) for mounting the semiconductor chip 5 on the lead 1 is performed. After the brazing material 4 is provided, the semiconductor chip 5 is mounted before the brazing material 4 solidifies. When the brazing material 4 solidifies, the semiconductor chip 5 is fixed to the lead 1.

Next, a wiring step (e) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed.

Next, a first sealing step (f) for sealing the first main surface with the first sealing resin 7 is performed.

Finally, the tie bar 2 is cut, a plurality of semiconductor integrated circuit devices manufactured on a lead frame are individually cut, and the leads 1 projecting from the sealing resin are bent to connect the external connection terminals of the semiconductor integrated circuit device. A terminal forming step (g) for forming is performed.

The operation will be described. In the COL system,
Since there was no die attach, the liquid wax material 4 was not suitable for the adhesive material, and the film sheet 9 was used. Embodiment 3
Now, a second sealing step of resin sealing with the second sealing resin 8
(b) is a mounting step of mounting the semiconductor chip 5
Perform before (c). The layer made of the second sealing resin 8 formed in the second sealing step (b) forms a kind of anti-dripping film for preventing dripping of the brazing material 4. Therefore, even when the liquid wax material 4 is used, the wax material 4 does not drop from between the leads 1, and the liquid wax material 4 can be used instead of the film sheet 9.

According to the third embodiment, on the second main surface side,
After the anti-dripping film was formed, the semiconductor chip 5 was mounted. For this reason, it is possible to use inexpensive brazing material 4 instead of the film sheet 9 as the adhesive material used to mount the semiconductor chip 5, thereby reducing the manufacturing cost of the semiconductor integrated circuit device. Can be planned.

Embodiment 4 Embodiment 4 will be described with reference to FIG.

FIG. 5 is a diagram showing a process of assembling a semiconductor integrated circuit device by the die attach method. In FIG. 5, reference numeral 5 denotes a semiconductor chip. 1 is a lead. 6 is a metal wiring. 7 is a first sealing resin. 2 is a tie bar. 3 is a die attach. 4 is a brazing material. 10 is a plate-shaped member.

Hereinafter, each assembly process will be described in order.
First, an adhesive material disposing step (b) for disposing the brazing material 4 on the die attach 3 is performed. This step (b) is the same as in the first embodiment, and a description thereof will be omitted. Next, a mounting step (c) of mounting the semiconductor chip 5 on the die attach 3 via the brazing material 4 is performed. This step (c) is the same as in the first embodiment, and a description thereof will be omitted.

Next, a wiring step (d) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed. This step (d) is the same as in the first embodiment, and a description thereof will be omitted.

Next, a plate member disposing step (e) of disposing the plate member 10 on the second main surface is performed. Embodiment 4
The point that the plate-like member arranging step (e) of arranging the plate-like member 10 on the second main surface side is different from the conventional technique. The plate member 10 is, for example, a silicon plate. Plate member 10
Are bonded by the brazing material 4.

Next, the first main surface side and the second main surface side are
A sealing step (f) of resin sealing with the sealing resin 7 is performed.
The lead frame was put into the mold shown in FIG. 2, the inside of the mold was decompressed, and the first sealing resin was melted through the first sealing resin injection port 52 and the second sealing resin injection port 55. Resin 7
Inject. Thus, both the first main surface side and the second main surface side are resin-sealed with the first sealing resin 7. Then, the first sealing resin 7 is heated to about 150 ° C. to be thermally cured.

Finally, the tie bar 2 is cut, a plurality of semiconductor integrated circuit devices manufactured on a lead frame are cut individually, and the leads 1 projecting from the sealing resin are bent to connect the external connection terminals of the semiconductor integrated circuit device. A terminal forming step (g) for forming is performed.

Next, the operation will be described. The thermal expansion coefficient of the semiconductor chip 5 is about 4.0 × 10 ⁻⁶ [° C. ⁻¹ ]. In the fourth embodiment, the thermal expansion coefficient is about 4.01 × 10
The plate member 10 of ^-6 [° C. ^-1 ] is used. Further, the shape and the arrangement position are the same as those of the semiconductor chip 5. This substantially eliminates the difference in the amount of shrinkage between the first main surface side and the second main surface side.

Therefore, since the bending stress in the semiconductor integrated circuit device is balanced, the warpage of the semiconductor integrated circuit device is reduced.

According to the fourth embodiment, since plate-like member 10 is provided on the second main surface, the bending stress of the semiconductor integrated circuit device is provided between the first main surface and the second main surface. Are substantially balanced. Therefore, the warpage of the semiconductor integrated circuit device can be reduced by using a single sealing resin.

Embodiment 5 Embodiment 5 will be described with reference to FIG. FIG. 6 is a diagram showing an assembly process of the semiconductor integrated circuit device according to the COL method. In FIG. 6, reference numeral 5 denotes a semiconductor chip. 1 is a lead.
6 is a metal wiring. 7 is a first sealing resin. 2 is a tie bar. 9 is a film sheet. 10 is a plate-shaped member.

Hereinafter, each assembly process will be described in order.
First, an adhesive material disposing step (b) for disposing the film sheet 9 on the lead 1 is performed. This step (b) is the same as in the second embodiment, and a description thereof will be omitted. Next, a mounting step (c) for mounting the semiconductor chip 5 on the lead 1 via the film sheet 9 is performed. This step (c)
Is the same as in the second embodiment, and a description thereof will be omitted.
Next, a wiring step (d) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed. This process
(d) is the same as in the second embodiment, and a description thereof will not be repeated.

Next, a plate member disposing step (e) of disposing the plate member 10 on the second main surface is performed. Embodiment 5
The point that the plate-shaped member disposing step (e) for disposing the plate-shaped member 10 is performed is different from the conventional technique.

Next, a sealing step (f) of resin-sealing the first main surface side and the second main surface side with the first sealing resin 7 is performed.

Finally, the tie bar 2 is cut, a plurality of semiconductor integrated circuit devices manufactured on a lead frame are cut individually, and the leads 1 projecting from the sealing resin are bent to connect the external connection terminals of the semiconductor integrated circuit device. A terminal forming step (g) for forming is performed.

According to the fifth embodiment, since plate-like member 10 is provided on the second main surface, the bending stress of the semiconductor integrated circuit device is different between the first main surface and the second main surface. However, this is substantially balanced, and the semiconductor integrated circuit device reduces the warpage. Therefore, the warpage of the semiconductor integrated circuit device can be reduced by using a single sealing resin.

Embodiment 6 FIG. Embodiment 6 will be described with reference to FIG. FIG. 7 is a diagram showing an assembly process of the semiconductor integrated circuit device according to the COL method. In FIG. 7, reference numeral 5 denotes a semiconductor chip. Reference numeral 1 denotes a lead that is electrically connected to the semiconductor chip 5 and serves as an external connection terminal of the semiconductor integrated circuit device. Reference numeral 6 denotes a metal wiring for electrically connecting the semiconductor chip 5 and the lead 1. 7
Is a first sealing resin. Reference numeral 2 denotes a tie bar for stopping the flow of the first sealing resin 7 and temporarily holding the lead 1 before cutting. Reference numeral 4 denotes a brazing material for bonding the semiconductor chip 5 to the leads 1. 10 is a plate-shaped member.

In the sixth embodiment, prior to performing the adhesive material disposing step (b) of disposing the film sheet 9 in the fifth embodiment, the plate member step of disposing the plate member 10 is performed. Points to be implemented and film sheet 9
The fifth embodiment is different from the fifth embodiment in that the semiconductor chip 5 is mounted by using the wax material 4 instead of the fifth embodiment.

First, a plate member disposing step (b) for disposing the plate member 10 on the second main surface is performed.

Next, an adhesive material disposing step (c) for disposing the brazing material 4 on the plate-like member 10 is performed. Next, a step of mounting the semiconductor chip 5 on the lead 1 via the brazing material 4
Perform (d). At this time, the previously arranged brazing material 4 is sandwiched between the plate member 10 and the semiconductor chip 5, and the plate member 10 and the semiconductor chip 5 are connected to the lead 1 via the brazing material 4. Adhered to. Next, a wiring step (e) for electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6 is performed. This step (e) is the same as in the fourth embodiment, and a description thereof will be omitted. Next, a sealing step of resin sealing the semiconductor chip 5 using the first sealing resin 7.
Perform (f). Since this step (f) is the same as that of the fourth embodiment, the description is omitted. Finally, the tie bar 2 is cut, and a plurality of semiconductor integrated circuit devices manufactured on a lead frame are individually cut, and the lead 1 projecting from the sealing resin is cut.
To form an external connection terminal of the semiconductor integrated circuit device to form a terminal forming step (g). This step (g) is the same as in the fourth embodiment, and a description thereof will be omitted.

Next, the operation will be described. In the COL type assembly, since the die attach 3 was not provided, the liquid wax material 4 was not suitable for the adhesive material, and the film sheet 9 was used. In the sixth embodiment, the plate-shaped member arranging step (b) for arranging the plate-shaped member 10 is performed before the adhesive material arranging step (c) for arranging the brazing material 4. This plate-like member arranging process
The plate-like member 10 arranged in (b) forms a kind of dripping prevention film for preventing dripping of the liquid brazing material 4. Therefore, even if the liquid wax material 4 is used, the wax material 4 does not drop from between the leads 1, and the wax material 4 can be used instead of the film sheet 9.

According to the sixth embodiment, on the second principal surface side,
After the anti-dripping film was formed, the semiconductor chip 5 was mounted. For this reason, inexpensive brazing material 4 can be used instead of film sheet 9 used for mounting semiconductor chip 5, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

Embodiment 7 FIG. Embodiment 7 will be described with reference to FIG.

In FIG. 8, reference numeral 5 denotes a semiconductor chip. Reference numeral 1 denotes a lead which is electrically connected to the semiconductor chip 5 and whose end serves as an external connection terminal of the semiconductor integrated circuit device. Reference numeral 6 denotes a metal wiring for electrically connecting the semiconductor chip 5 and the lead 1. 7 is a first sealing resin. Reference numeral 2 denotes a tie bar for temporarily stopping the flow of the sealing resin and temporarily holding the lead 1 before cutting. 3 is a semiconductor chip 5
This is a die attach to mount. Reference numeral 4 denotes a wax material for bonding the semiconductor chip 5 to the die attach 3.

Hereinafter, each assembly process of the semiconductor integrated circuit device according to the die attach method will be described. First, an adhesive material disposing step of disposing the brazing material 4 on the die attach 3 (b)
Is carried out. This step (b) is the same as in the first embodiment, and a description thereof will be omitted. Next, a mounting step of mounting the semiconductor chip 5 on the die attach 3 via the brazing material 4
Perform (c). This step (c) is the same as in the first embodiment, and a description thereof will be omitted. Next, a wiring step of electrically connecting the semiconductor chip 5 and the lead 1 with the metal wiring 6
Perform (d). This step (d) is the same as in the first embodiment, and a description thereof will be omitted.

Next, the semiconductor chip 5 is placed in the first sealing resin 7.
A sealing step (f) of resin sealing is performed using At this time, the mold shown in FIG. 9 is used. The inside of the mold of the first embodiment shown in FIG. 2 is vertically symmetric about the lead frame, whereas the inside of the mold used in the seventh embodiment has a vertically asymmetric thickness. It is configured to be sealed with resin. That is, the first main surface side is thickly resin-sealed, and the second main surface side is thinly resin-sealed.

Next, the tie bars 2 are cut, a plurality of semiconductor integrated circuit devices manufactured on a lead frame are individually cut, and the leads 1 projecting from the sealing resin are bent to connect the external connection terminals of the semiconductor integrated circuit device. Step (g) of molding is performed.

Next, the operation will be described. In the case where the vertically symmetrical mold described in Embodiment 1 is used and the resin is sealed with the same thickness of the sealing resin and the type of the sealing resin, the first principal surface is bent. The stress and the bending stress on the second main surface side are not balanced.

However, if the second main surface side is formed to be thinly resin-sealed, the stress is also reduced. That is,
Since the first main surface side is sealed with the first sealing resin and the second main surface side is resin-sealed thicker than the first main surface side, the first main surface side and the second main surface side are sealed. The difference in stress from the surface side can be substantially reduced.

The case where the first sealing resin 7 has a coefficient of thermal expansion smaller than that of the semiconductor chip 5 has been described. Needless to say, the second main surface may be configured to be thick. In addition to the die attach method, COL
It goes without saying that the present invention can also be applied to the system.

According to the seventh embodiment, the first main surface is sealed with the first sealing resin, and the second main surface is sealed with a thickness different from that of the first main surface. Stop, the first main surface side and the second main surface side
The bending stress of the semiconductor integrated circuit device is substantially balanced with the main surface of the semiconductor integrated circuit device, and the warpage of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an assembly process according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a sealing step according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an assembly process according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an assembly process according to a third embodiment of the present invention.

FIG. 5 is a diagram showing an assembly process according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing an assembly process according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing an assembly step according to a sixth embodiment of the present invention.

FIG. 8 is a diagram showing an assembly step according to a seventh embodiment of the present invention.

FIG. 9 is a diagram showing a sealing step according to a seventh embodiment of the present invention.

FIG. 10 is a diagram showing an assembly process of the semiconductor integrated circuit device according to the prior art of the present invention.

FIG. 11 is a diagram illustrating an example of a lead frame.

FIG. 12 is a view showing an assembly process of the semiconductor integrated circuit device according to the prior art of the present invention.

[Explanation of symbols]

1 is a lead, 2 is a tie bar, 3 is a die attach, 4 is a brazing material, 5 is a semiconductor chip, 6 is a wiring, 7 is a first sealing resin, 8 is a second sealing resin, 9 is a film sheet, 10 is a plate-shaped member.

Claims (9)

[Claims] A plurality of leads; a semiconductor chip formed on the first main surface formed by the leads; a metal wiring for electrically connecting the leads and the semiconductor chip; A first sealing resin disposed on the first main surface side for sealing the semiconductor chip and the wiring; and a second encapsulation for forming the leads and sealing the second main surface side A semiconductor integrated circuit device comprising: a resin. 2. The semiconductor integrated circuit device according to claim 1, wherein said first sealing resin has a larger thermal expansion coefficient than said second sealing resin. 3. A plurality of leads, a semiconductor chip formed on the first main surface formed by the leads, a metal wiring for electrically connecting the leads and the semiconductor chip, A first sealing resin provided on the first main surface side to seal the semiconductor chip and the wiring; and a plate-like member provided on the second main surface formed by the lead; A second sealing resin that is disposed on the second main surface side and seals the plate-shaped member. 4. The semiconductor device according to claim 1, wherein the plate-shaped member has the same shape as the semiconductor chip and has the same coefficient of thermal expansion.
The semiconductor integrated circuit device according to claim 3. 5. A plurality of leads, a semiconductor chip formed on the first main surface formed by the leads, a metal wiring for electrically connecting the leads and the semiconductor chip, A first sealing resin disposed on a first main surface side for sealing the semiconductor chip and the wiring; and a second main surface side on which the leads are formed, the first main surface side And a second sealing resin for sealing to a thickness different from that of the semiconductor integrated circuit device. 6. The method according to claim 5, wherein the first sealing resin is formed thicker than the second sealing resin.
3. The semiconductor integrated circuit device according to 1. 7. The bending stress on the first main surface side and the bending stress on the second main surface side are balanced at room temperature. 3. The semiconductor integrated circuit device according to 1. 8. A step of disposing a plate-like member on the second principal surface side on which a plurality of leads are formed; Arranging a semiconductor chip on a surface side of the semiconductor integrated circuit device. 9. A step of forming a second sealing resin on a second main surface side on which a plurality of leads are formed, and forming a plurality of leads after the step of forming a second sealing resin. Arranging a semiconductor chip on the first main surface side.