JP2001007046A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve workability by removing a resist film used as a mask in ion implantion step. SOLUTION: This semiconductor device manufacturing method includes steps of using as a mask a resist film 7 formed on an interlayer insulating film, consisting of TEOS films 4, 6, a BPSG film 5, etc., which covers a titanium silicide film 3 on a diffusion layer 2 formed on a semiconductor substrate 1, making a contact hole 8 on the substrate 1 via the insulating film, and then removing the resist film 7. In this case, the step of removing the resist film 7 comprises the ashing step of using O2 plasma, a reverse sputtering step using an argon gas, and a cleaning step of using sulfuric acid and hydrogen peroxide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for removing a resist film used as a mask in an ion implantation step.

[0002]

2. Description of the Related Art A method of manufacturing a semiconductor device according to a conventional example, in particular, a step of removing a resist film used as a mask during an ion implantation step will be described below.

First, in FIG. 5, reference numeral 51 denotes a semiconductor substrate; 52, a diffusion layer formed on the surface of the substrate 51; titanium silicide (TiSi ₂ ) on the diffusion layer 52 in order to reduce resistance; ) A film 53 is formed. Then, on the substrate 51, for example, the LP-TEOS film 54,
An interlayer insulating film composed of a BPSG film 55 and a plasma TEOS film 56 is formed, and a contact hole 58 for contacting the titanium silicide film 53 is formed in the interlayer insulating film by using a resist film 57 formed thereon as a mask. Is formed. The BPSG film 55 is interposed to improve the flatness of the interlayer insulating film.

In the state where the contact holes are formed, impurities of the same conductivity type are ion-implanted so as to reach the diffusion layer 52 in order to suppress leakage at the contact portion in the diffusion layer 52. I have.

Then, the resist film 57 used for forming the contact hole 58 is removed, and a metal wiring which contacts the diffusion layer 52 through the contact hole 58 is formed (not shown). In this step, for example, after forming a barrier metal film composed of a titanium (Ti) film and a titanium nitride (TiN) film so as to cover the entire contact hole 58, the inside of the contact hole 58 is formed through the barrier metal film. A tungsten (W) film is embedded in the tungsten plug, and an Al alloy (Al
-Si, Al-Cu, Al-Si-Cu) and the like.

[0006]

However, at the time of removing the resist film 57, the following problem has occurred.

That is, when the resist film 57 is removed, first, the resist film 57 is ashed, for example,
An ashing process using O ₂ plasma is performed. Subsequently, cleaning is performed using sulfuric acid H ₂ SO ₄ and a hydrogen peroxide solution H ₂ O ₂ . As described above, even if the work is performed by the conventionally used removal method, the resist remains 59 as shown in FIG.

In the ion implantation step performed to suppress the contact leakage of the diffusion layer 52, the surface of the resist film 57 is hardened by the temperature rise due to the ion bombardment, and the deteriorated layer (see the hatched portion shown in FIG. 5). ) Is produced, and the deteriorated layer portion significantly lowers the etching rate to increase the accumulated heat, and as a result, accelerates the thermal deterioration of the resist film 57 during the ashing process, leaving the resist residue 59. It is the cause.

When the wafer is mounted in a sputtering apparatus for forming metal wiring and a sputtering process is performed in a state where the remaining resist 59 is present, the remaining resist 59 is scattered in the apparatus and the reliability of the metal wiring is reduced. There is a problem that the cleaning performance is reduced and the cleaning work later becomes troublesome.

Further, in order to remove the resist residue 59, a mixed solution (SC1) of dilute hydrofluoric acid HF or ammonia NH ₃ and hydrogen peroxide solution H ₂ O ₂ is used for the wafer in the state of FIG. Then, the resist residue 59 can be removed.

However, when such a cleaning step is added, as shown in FIG. 7, the etching rate is higher than the other films (the LP-TEOS film 54 and the plasma TEOS film 56) constituting the interlayer insulating film. The BPSG film 55 having a high level is further etched and receded in the direction of the arrow.

When the subsequent metal wiring forming step is performed in such a state, the following problem occurs.

That is, although the illustrated description is omitted, when the barrier metal film is formed so as to cover the entire contact hole 58, the barrier metal film is uniform due to the unevenness of the side wall of the contact hole 58. It will not be formed with a thicker thickness. In some cases, the coverage of the titanium nitride film constituting the barrier metal film was deteriorated, and the underlying titanium film was even exposed. When a tungsten film is formed via a barrier metal film having a non-uniform film thickness, the titanium film and the titanium nitride film are peeled off, and abnormal deposition (so-called volcano) and metal There is a problem that a short circuit or the like occurs.

As described above, conventionally, there is no method for completely solving the above problem. Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which the step of removing a resist film used as a mask during the above-described ion implantation step is improved.

[0015]

Therefore, a method of manufacturing a semiconductor device according to the present invention comprises a method of manufacturing a semiconductor device by forming a TEOS film 4, 6 and a BPSG film 5 covering a titanium silicide film 3 on a diffusion layer 2 formed on a semiconductor substrate 1. Forming a contact hole 8 for contacting the substrate 1 via the interlayer insulating film using the resist film 7 formed on the interlayer insulating film as a mask, and then removing the resist film 7. ,
The step of removing the resist film 7 includes an ashing step using O ₂ plasma shown in FIG. 2, a reverse sputtering step using an argon gas shown in FIG. 3, and a cleaning step using sulfuric acid and hydrogen peroxide. I do.

A floating gate 25 and a control gate 2 are formed on a semiconductor substrate 21 as shown in FIG.
And the floating gate 25
And a TEOS film, a BPSG film, or the like, which covers a region having a high step portion such as a nonvolatile semiconductor memory device in which a titanium silicide film 23 is formed on a diffusion region 22 formed adjacent to a control gate 27. Forming a contact hole 29 that contacts the titanium silicide film 23 through the interlayer insulating film 28 using the resist film formed on the interlayer insulating film 28 as a mask, and then removing the resist film. The resist film removing step includes an ashing step using O ₂ plasma, a reverse sputtering step using an argon gas, and a cleaning step using sulfuric acid and a hydrogen peroxide solution.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

First, in FIG. 1, reference numeral 1 denotes a semiconductor substrate of one conductivity type, for example, a P-type, and 2 denotes an opposite conductivity type, for example, an N-type diffusion layer formed on a surface layer of the substrate 1. 2 on top of titanium silicide (Ti
An Si ₂ ) film 3 is formed. Then, on the substrate 1, for example, an interlayer insulating film composed of an LP-TEOS film 4, a BPSG film 5, and a plasma TEOS film 6 is formed, and a resist film (PR) formed thereon is formed on the interlayer insulating film.
A contact hole 8 is formed on the titanium silicide film 3 using the mask 7 as a mask. In addition, BPS
The G film 5 is interposed to improve the flatness of the interlayer insulating film.

In the state where the contact hole 8 is formed as described above, in order to suppress leakage at the contact portion in the diffusion layer 2, impurities of the same conductivity type, that is, N-type impurities, reach the diffusion layer 2. (Eg, phosphorus ions) are implanted. At this time, in the ion implantation step performed to suppress the contact leak of the diffusion layer 2, the surface of the resist film 7 is hardened by the temperature rise due to the ion bombardment, and the deteriorated layer (see the hatched portion shown in FIG. 1).
Can be. It should be noted that a P-type diffusion layer may be formed on an N-type substrate, an N-type diffusion layer may be formed on a P-type well, or a P-type diffusion layer may be formed on an N-type well.

Then, the resist film 7 used as a mask when forming the contact hole 8 is removed. This step
First, in order to ash the resist film 7, for example, O ₂ in a state where a wafer is mounted in an RIE (reactive ion etching) type plasma processing apparatus. An ashing process using plasma is performed. In this case, as shown in FIG. 2, a resist residue 9 remains on the interlayer insulating film as in the conventional case.

Subsequently, reverse sputtering using an inert gas is performed in another plasma processing apparatus. In this step, for example, argon gas (Ar) is used as an inert gas,
With the high frequency of 3.56 MHz generated, the output 20
0-500W, flow rate 20-50sccm, low pressure 20-
The sputtering process is performed under various conditions of 50 mTorr. Note that neon gas Ne other than argon gas may be used as the inert gas, or another gas may be used. Further, in order to improve the uniformity, a small amount of a gas such as N ₂ or O ₂ may be added to the argon gas as an additional gas.

In this step, as shown in FIG. 3, the remaining resist 9 is removed, and the upper corner of the contact hole 8 is also removed (see the arrow 10 in FIG. 3). This is because the plasma-converted argon gas is supplied to the contact hole 8 described above.
This is for removing the remaining resist 9 remaining on the upper portion of the contact hole and chamfering the upper corner of the contact hole 8.

Subsequently, sulfuric acid H ₂ SO ₄ and hydrogen peroxide solution H ₂
Wash with a mixture of O ₂ .

Although not shown, a metal wiring is formed to contact the diffusion layer 2 through the contact hole 8. In this step, for example, after forming a barrier metal film composed of a titanium (Ti) film and a titanium nitride (TiN) film so as to cover the entire contact hole 8,
A tungsten (W) film is buried in the contact hole 8 via the barrier metal film, and an Al alloy (Al-Si, Al-Cu, Al-Si-C) is formed on the tungsten plug.
u) and the like are formed.

As described above, according to the present invention, when ions are implanted in order to suppress the contact leakage of the diffusion layer 2, the deteriorated layer portion formed by hardening of the surface of the resist film 7 due to the temperature rise due to the ion bombardment. Can be reliably removed, and the remaining resist 9 as in the prior art is eliminated.
For this reason, when the metal wiring is formed in a later step, when the wafer is mounted in the sputtering apparatus for forming the metal wiring and the sputtering process is performed, the remaining resist 9 does not scatter in the sputtering apparatus. Wiring with good properties can be formed, and the cleaning operation inside the apparatus can be simplified.

In addition, conventionally, in order to remove the remaining resist 59, cleaning is performed by using a mixed solution (SC1) composed of dilute hydrofluoric acid HF or ammonia NH ₃ and a hydrogen peroxide solution H ₂ O ₂ , as shown in FIG. As shown in the figure, the problem of unevenness in the side wall of the interlayer insulating film and the occurrence of volcano can be solved by adopting the present invention because the cleaning step is not required by the present invention.

Further, in the present invention, since the corners above the contacts 8 are chamfered, there is also an effect that the step coverage in forming the metal wiring is improved.

Hereinafter, an embodiment in which the present invention is applied to a nonvolatile semiconductor memory device having a floating gate and a control gate will be described with reference to FIG.

In FIG. 4, for example, a P-type semiconductor substrate 2
An N-type diffusion region (a diffusion region having a deeper diffusion depth is referred to as a source region and a shallower diffusion region is referred to as a drain region) 22 is formed on the surface layer 1 of the semiconductor device 1 so as to be separated from each other.

A titanium silicide (TiSi ₂ ) film 23 is formed on one of the diffusion regions which are to be in contact with a bit line described later, that is, on the surface layer of the drain region 22 in order to reduce the resistance.

The other diffusion region, that is, the source region 2
About 100-200 ° on the substrate 21 on both sides of
1000Å20 through the insulating film 24 having a thickness of
A floating gate 25 made of a conductive polysilicon film having a thickness of 00 ° is formed. Further, on the substrate 11 between the source region 22 and the drain region 22, an insulating film 26 having a thickness of about 300 ° to 400 ° is formed.
Then, a control gate 27 made of a polysilicon film having a thickness of about 1000 to 2000 degrees and a tungsten silicide (WSix) film having a thickness of about 1000 to 2000 degrees is formed. The end of the control gate 27 on the side of the source region 22 is connected to the insulating film 2.
6 and above the floating gate 25.

The source region 22 and the control gate 27 both extend in one direction (perpendicular to the plane of the drawing). A plurality of drain regions 22 and a plurality of control gates 27 are provided on both sides of the source region 22. They are arranged along the one direction. Then, the control gate 27 functions as a word line of the nonvolatile semiconductor memory device.

Then, for example, an LP-TEOS film, a BPSG film, and a plasma T are coated so as to cover the floating gate 25 and the control gate 27 on the substrate 21.
An interlayer insulating film 28 made of an EOS film is formed. The BPSG film is interposed in order to improve the flatness of the interlayer insulating film 28.

In the nonvolatile semiconductor memory device having such a structure, a contact hole 29 for making contact with the titanium silicide film 23 is formed in the interlayer insulating film 28 using a resist film (not shown) as a mask. For the purpose of suppressing contact leak, ions of the same conductivity type, that is, N-type impurities (for example, phosphorus ions) are implanted so as to reach the drain region 22. At this time, an altered layer due to the impact at the time of ion implantation is formed on the surface of the resist film.

In the step of removing the resist film having the altered layer, the present invention is applied. As described in the first embodiment, first, the O ₂ plasma is removed in the RIE type plasma processing apparatus. (In this case, the resist remains on the interlayer insulating film as in the conventional case as shown in FIG. 2 as shown in FIG. 2), and then in another plasma processing apparatus, argon gas (Ar 4), the remaining resist is removed and the upper corner of the contact hole 29 is chamfered as shown in FIG. Then, cleaning is performed using sulfuric acid H ₂ SO ₄ and a hydrogen peroxide solution H ₂ O ₂ .

Hereinafter, a barrier metal film (not shown) made of a titanium film and a titanium nitride film is formed on the entire contact hole 29, and a tungsten plug 30 made of a tungsten (W) film is formed through the barrier metal film. By embedding and forming a metal wiring 31 thereon, a bit line of the nonvolatile semiconductor memory device is formed in contact with the drain region 22.

Also in the present embodiment, since the remaining resist as in the prior art is eliminated, when forming the metal wiring in the subsequent process, the wafer is mounted in a sputtering apparatus for forming the metal wiring and subjected to the sputtering process. At this time, since the resist residue does not scatter in the apparatus, a highly reliable wiring can be formed, and the cleaning operation in the apparatus can be further simplified.

In addition, conventionally, in order to remove the resist residue, cleaning is performed using diluted hydrofluoric acid HF or a mixed solution (SC1) composed of ammonia NH ₃ and hydrogen peroxide solution H ₂ O ₂ , as shown in FIG. As shown in the figure, the problem of unevenness in the side wall of the interlayer insulating film and the occurrence of volcano can be solved by adopting the present invention because the cleaning step is not required by the present invention.

Here, the contact hole 29 in which the metal wiring 31 is formed is formed in a high step portion of the nonvolatile semiconductor memory device in which the floating gate 25 and the control gate 27 are stacked as shown in FIG. Therefore, the contact hole 29 cannot be avoided.
When a wiring film made of aluminum etc. is formed in
The step coverage will be worse. Therefore, the above-described tungsten plug 30 is buried in the contact hole 29, and this tungsten plug 30
When the metal wiring 31 is formed thereon, the step coverage of the metal wiring 31 can be improved by applying the present invention in order to suppress abnormal deposition of the tungsten film.

In the present embodiment, an example is shown in which the present invention is applied to a so-called split gate type nonvolatile semiconductor memory device in which a control gate 27 is laminated on a part of a floating gate 25 with an insulating film 26 interposed therebetween. But
The present invention may be applied to a so-called stacked gate type nonvolatile memory device in which a control gate is stacked on the entire surface of a floating gate.

Also, when argon gas is used, the rate at which the interlayer insulating film is cut is lower than that when other O ₂ gas is used, for example, so that the cut oxide film is deposited on the bottom of the contact. Therefore, the problem that the contact diameter is reduced and the contact resistance is increased can also be reduced.

Further, before the washing step with sulfuric acid and hydrogen peroxide after the above-mentioned reverse sputtering with argon gas,
By adding an oxide film etching process, an oxide film slightly formed at the bottom of the contact can be removed, and the contact resistance can be further reduced. In this oxide film etching step, a fluorine-based gas such as CF ₄ may be supplied instead of the argon gas supplied into the plasma processing apparatus described above, and the workability is good.

[0043]

As described above, according to the present invention, the resist film used as the mask during the ion implantation step can be completely removed, and the workability can be improved.

Further, since the corners above the contact holes are chamfered, the step coverage at the time of forming the metal wiring can be improved.

Further, since the conventional cleaning process for removing the residual resist is not required, a part of the side wall of the interlayer insulating film is receded, so that the occurrence of volcano does not occur. Can be improved.

Further, if the present invention is applied to a step of forming a contact hole formed in a region having a high step portion and a step of embedding a tungsten film in a non-volatile semiconductor memory device having a floating gate and a control gate, a resist can be obtained. The remainder is eliminated, and the step of embedding the tungsten film can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 6 is a diagram for explaining a conventional problem.

FIG. 7 is a diagram for explaining a conventional problem.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 29/792 (72) Inventor Osamu Ishimaru 3000 Chiyakko, Ojiya-shi, Niigata F-term in Niigata Sanyo Electronics Co., Ltd. ) 4M104 AA01 BB25 CC01 DD08 DD12 DD16 DD19 DD21 EE12 EE15 FF22 GG16 HH13 HH20 5F001 AA01 AB03 AB08 AD16 AF25 AG10 AG12 AG17 AG29 5F033 HH08 HH09 JJ18 JJ19 JJ33 KK01 KK27 NN03 Q07 Q04 Q09 Q04 Q04 VV16 XX00 XX21 5F083 EP02 EP23 EP24 EP62 GA02 GA27 GA30 JA35 JA36 JA39 JA40 JA53 JA56 MA04 MA05 MA06 MA20 NA08 PR00 PR03 PR05 PR22 PR36

Claims (8)

[Claims] 1. A CVD oxide film on a semiconductor substrate, BPSG
Manufacturing a semiconductor device having a step of forming a contact hole in contact with the substrate via the interlayer insulating film using the resist film formed on the interlayer insulating film made of a film or the like as a mask, and then removing the resist film In the method, the step of removing the resist film includes an ashing step, a reverse sputtering step using an inert gas, and a cleaning step. 2. Using a resist film formed on an interlayer insulating film made of a CVD oxide film, a BPSG film, or the like covering a silicide film formed on a semiconductor substrate as a mask, the resist film is formed on the silicide film via the interlayer insulating film. A method for manufacturing a semiconductor device, comprising: a step of removing the resist film after forming a contact hole to be contacted; wherein the step of removing the resist film includes an ashing process, a reverse sputtering process using an inert gas, and a cleaning process. And a method of manufacturing a semiconductor device. 3. Using a resist film formed on an interlayer insulating film made of a CVD oxide film, a BPSG film, or the like, covering a silicide film formed on a semiconductor substrate as a mask, the resist film is formed on the silicide film via the interlayer insulating film. A method for manufacturing a semiconductor device, comprising: a step of removing the resist film after forming a contact hole to be contacted; wherein the step of removing the resist film includes an ashing process, a reverse sputtering process using an inert gas, and an oxide film. A method for manufacturing a semiconductor device, comprising: an etching step; and a cleaning step. 4. The method according to claim 1, wherein the reverse sputtering step using an inert gas is performed using an Ar gas or a He gas using a reactive ion etching type plasma processing apparatus. Item 4. The method for manufacturing a semiconductor device according to Item 3. 5. An interlayer insulating film made of a CVD oxide film, a BPSG film, or the like covering a region having a high step portion, such as a nonvolatile semiconductor memory device in which a floating gate and a control gate are stacked on a semiconductor substrate. Forming a contact hole on the substrate via the interlayer insulating film using the resist film formed thereon as a mask, and then removing the resist film; A method for manufacturing a semiconductor device, wherein the removing step includes an ashing step, a reverse sputtering step using an inert gas, and a cleaning step. 6. A nonvolatile semiconductor memory device comprising: a floating gate and a control gate laminated on a semiconductor substrate; and a silicide film formed on a diffusion region formed adjacent to the floating gate and the control gate. A contact that contacts the silicide film via the interlayer insulating film using a resist film formed on an interlayer insulating film made of a CVD oxide film, a BPSG film, or the like covering the region having the high step portion as described above as a mask. In the method for manufacturing a semiconductor device having a step of removing the resist film after forming the holes, the step of removing the resist film includes an ashing process, a reverse sputtering process using an inert gas, and a cleaning process. A method for manufacturing a semiconductor device, comprising: 7. A non-volatile semiconductor memory device comprising: a floating gate and a control gate laminated on a semiconductor substrate; and a silicide film formed on a diffusion region formed adjacent to the floating gate and the control gate. A contact that contacts the silicide film via the interlayer insulating film using a resist film formed on an interlayer insulating film made of a CVD oxide film, a BPSG film, or the like covering the region having the high step portion as described above as a mask. In the method for manufacturing a semiconductor device, comprising the step of removing the resist film after forming the holes, the step of removing the resist film includes an ashing process, a reverse sputtering process using an inert gas, and an oxide film etching process. And a cleaning process. 8. The reverse sputtering step using an inert gas is performed using an Ar gas or a He gas using a reactive ion etching type plasma processing apparatus. Item 8. A method for manufacturing a semiconductor device according to item 7.