JP2001005773A - Device and method for controlling storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a bus occupancy ratio and to prevent a DMA access from stopping at the break of a line. SOLUTION: A controller part 101 divides bitmap data into odd line data and even line data, switches line data obtained by the division to the memory bank of a corresponding SDRAM 107 according to the odd/even of each line and collectively fetches the bitmap data of odd and even lines by one time DMA access while synchronizing with the memory bank switching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a storage control device and method used in a print control device capable of performing resolution conversion processing.

[0002]

2. Description of the Related Art Conventionally, a memory control device has different DMA channel parameters for data of odd-numbered lines and even-numbered lines of bitmap data created in units of pages or bands, and each DMA (direct memory) has
The print data is stored in the buffer by managing the head address and word width in the access) unit, and the video conversion unit sends the serial video signals (CVDON, CVDO (N +
The resolution conversion processing has been performed by transferring 1)). The resolution conversion processing referred to here means that reproduction is performed without loss of details using an engine having a resolution lower than the resolution of the pixel pattern of the bitmap data.

FIG. 5 is an explanatory diagram for explaining an example in which bitmap data having a resolution of 2R on an SDRAM is printed out at a resolution of (4R × R). In this example, the A bank stores bitmap data of even lines, and the B bank stores bitmap data of odd lines. Then, the bitmap data is converted to the SDR
When importing from AM, access from bank A and B
Bank access is alternately repeated. That is, the bitmap data of the nth line is fetched in the access cycle of bank A, and (n +
1) The bitmap data of the line is fetched, the bitmap data of the (n + 2) th line is fetched in the access cycle of the bank A, and the bitmap data of the (n + 3) th line is fetched in the access cycle of the bank B. The bitmap data is taken in according to such a rule.

[0004] The resolution conversion unit performs data processing on the bitmap data having a resolution of 2R and prints out the data at a resolution of (4R x R).

[0005]

However, in the above-mentioned conventional example, as shown in FIG. 6, when performing the resolution conversion process, two channels of DMA are required, and individual parameters are required, so that control is not performed. There is a problem that the system becomes complicated and the occupation ratio of the DMA path of the video control unit in the system increases.

Also, at the line break, the address is set to DMA.
Since one line is always skipped for each channel, DMA access is always cut off, and there is a problem that access efficiency is poor.

Accordingly, an object of the present invention is to solve the above-mentioned problems, reduce the bus occupation rate, and ensure that DMA access is not interrupted at line breaks and that the configuration can be simplified. It is to provide an apparatus and a method.

[0008]

According to a first aspect of the present invention, there is provided a dividing means for dividing bitmap data into odd-numbered line data and even-numbered line data, and dividing the line data obtained by the dividing means into odd-numbered line data and odd-numbered line data. Storage means for switching and storing in a corresponding memory bank according to an even number;
In synchronization with the memory bank switching by the storage means, 1
DMA access means for fetching bitmap data of odd and even lines in a single DMA access.

In the first aspect, the DMA access means can perform access in burst units.

In the present invention, the DMA access means can divide a burst unit into two and assign the highest address as a bank address.

According to the first aspect of the present invention, it is possible to provide a load means for reloading the offset address of the bank corresponding to the even line when the bank address is switched.

According to a fifth aspect of the present invention, there is provided a dividing step of dividing bitmap data into odd-numbered line data and even-numbered line data, and the line data obtained by the division is switched and stored in a corresponding memory bank according to the odd-even number of each line. A storage step and a DMA access step in which bitmap data of odd-numbered and even-numbered lines are batch-fetched by one DMA access in synchronization with memory bank switching in the storage step.

In the fifth aspect, in the DMA access step, the access can be performed in burst units.

In the sixth aspect, in the DMA access step, the burst unit can be divided into two, and the highest address can be assigned as a bank address.

According to a fifth aspect of the present invention, a load step of reloading the offset address of the bank corresponding to the even-numbered line when the bank address is switched can be provided.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
An embodiment will be described. This is an example of a printing system. As shown in FIG. 1, the printing system includes a controller unit 101, a host computer 102, and an engine unit 103.

The controller 101 processes commands and data from the host computer 102 and forms image information recorded on recording paper as bitmap data in a memory. Host computer 102
Is a print data supply source for the controller unit 101. The engine unit 103 receives the
It prints VDQ Data on recording paper.

The controller unit 101 has a CPU (central
processing unit (104) and ROM (read only memor)
y) 105 and RAM (random access memory) 106
, An SDRAM 107, an I / F (interface) control unit 108, a DMA controller 109, and a video control unit 110 are mutually connected via a system bus 112. A resolution conversion processing unit 111 is connected to the video control unit 110.

The CPU 104 controls each section of the controller section 101. The ROM 105 stores programs for managing the operation of the controller unit 101 and font data. The RAM 106 temporarily saves the stack of the program and stores control results, and is mainly used for work. The SDRAM 107 has two banks, and stores image information generated by processing recording data from the host computer 102 as bitmap data. The I / F control unit 108 captures recording data from the host computer 102 based on a protocol and outputs the data to the RAM 106. DMA controller 109 is CPU 10
4 and a plurality of DMA units (not shown)
5, when there is a request for access to a memory such as the RAM 106 and the SDRAM 107, the system bus 112
Arbitration, memory access timing, data paths, and the like. The video control unit 110 is SD
The bitmap data stored in the RAM 107 is converted from parallel to serial at a predetermined timing,
Resolution conversion processing unit 1 for the data of the line required as ta
11 is output. The resolution conversion processing unit 111 receives the VDO of the line from the video control unit 110
Data is fetched, the data having a resolution of 2R is converted into (4R × R) data at a predetermined timing, and output to the engine unit 103. System bus 11
Numeral 2 is for transferring address and data information to each section.

FIG. 2 is a flowchart showing an example of the control program stored in the ROM 105 of FIG. When the recording data is transferred from the host computer 102, the recording data is temporarily stored in the RAM 106 through the I / F control unit 108, and the recording data is transferred to the CPU 104.
And a plurality of DMA units (not shown) (S101). At this time, an output mode code indicating “in what format” the VDO Data is desired to be printed out on the recording paper is identified from the recording data. Whether the code is in the Real output mode (print output of 2R data with 2R resolution as it is) or the resolution conversion output mode (print of 2R data with (4R × R) resolution) is output. A determination is made (S102). Then, the storage method of the bitmap data formed in SDRAM 107 is changed according to the determination result.

That is, if it is determined that the output mode is the resolution conversion output mode, the bit map data is stored by switching the bank between the odd line and the even line (S103), and the video controller 110 transfers the bit map data to the SDRAM 107 by DMA. (S104).

FIG. 4 is an explanatory diagram for explaining an example in which bitmap data having a resolution of 2R on the SDRAM 107 is printed out at a resolution of (4R × R). In this example, A
The bank stores the bitmap data of the even line, and the bank B stores the bitmap data of the odd line. When the bitmap data is taken in from the SDRAM 107, the bitmap data of the nth line of the A bank and the (n +
1) The bitmap data of the two lines of the bitmap data of the line are fetched in a lump by switching the banks, and then the bitmap data of the (n + 2) th line of the A bank and the (n + 3) th line of the B bank. The two lines of bitmap data of the bitmap data are fetched collectively by switching the banks, and thereafter, by such a rule, fetched collectively by switching the banks every two lines.

The DMA from the video control unit 110
When the request is accepted, the DMA controller 109 divides the burst unit into two, that is, (when the access unit to the SDRAM 107 by the DMA controller 109 is eight bursts), and divides it into four bursts, and the highest address, that is, (0 → 4) → 8 → C → 10
→ 14 → 18 → 1C) A4 is SDRAM
107 is assigned to the bank address (BA) (S10
5). Then, four words are fetched from each bank, and the video control unit 110 outputs data of four words of the line (QA in FIG. 3G) and data of four words of the next line (FIG. 3G).
(QB) of (g) is the OBU of the video control unit 110, respectively.
F and EBUF (see FIG. 3 for specific timing).

When one DMA request by the video control unit 110 is completed, the DMA controller 109
Adds the DMA address for each bank, and the added value becomes half of the normal burst unit (here, 20 → 10 × 2 (h)) (S10
6).

Then, the data is stored in the O
At the time when the data is quantitatively stored in the BUF and the EBUF, the video control unit 110 converts the data of the line and the next line into parallel / serial data and outputs the data to the resolution conversion processing unit 111 (CVDON and CVDO (N + 1)) (S
107).

Further, in this embodiment, if the offset addresses (A0) of the odd and even lines are matched, a circuit can be realized only by changing only the bank address BA. Since there is no need to load addresses, the configuration can be simplified.

<Second Embodiment> In the first embodiment, with respect to each bank of the SDRAM 107, the offset address for storing the bit map data of each of the odd line and the even line is shared, and only the bank address BA is used. Was switched to simplify the circuit.

On the other hand, in the present embodiment, the SDR
Various cases are conceivable due to the configuration of the controller unit 101, such as the capacity of the AM 107 and the processing method of the bitmap data in band units.
When fetching data from the RAM 107, the offset address of the bank B is reloaded when the bank address BA is switched (indicated by ★ in FIG. 3), so that the same effect as in the first embodiment is obtained. Can be played.

[0030]

As described above, according to the present invention,
With the above-described configuration, the bus occupation rate related to the DMA access of the video control is reduced, and the address is continuous for each bank even at the line break, so that the DMA access is not interrupted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a control program stored in a ROM 105 of FIG.

FIG. 3 is a timing chart showing an example of the timing of each signal of the controller unit 101 in FIG. 1;

FIG. 4 is a diagram showing an example of a memory map of the SDRAM 107.

FIG. 5 is a diagram showing an example of a memory map on an SDRAM in a conventional storage control device.

FIG. 6 is a timing chart showing an example of the timing of each signal of a conventional memory control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Controller part 102 Host computer 103 Engine part 104 CPU 105 ROM 106 RAM 107 SDRAM 108 I / F control part 109 DMA controller 110 Video control part 111 Resolution conversion processing part 112 System bus

Claims (8)

[Claims] 1. Dividing means for dividing bitmap data into odd-numbered line data and even-numbered line data, and storage for switching and storing the line data obtained by the dividing means into a corresponding memory bank according to the odd-even number of each line. Means in synchronization with memory bank switching by said storage means.
A storage control device comprising: a DMA access unit that fetches bitmap data of odd and even lines in a single DMA access. 2. The storage controller according to claim 1, wherein said DMA access means performs access in burst units. 3. The storage control device according to claim 2, wherein said DMA access means divides a burst unit into two and assigns the highest address as a bank address. 4. The storage control device according to claim 1, further comprising a load unit that reloads an offset address of a bank corresponding to an even-numbered line when a bank address is switched. 5. A dividing step of dividing the bitmap data into odd line data and even line data, and a storing step of switching and storing the line data obtained by the division into a corresponding memory bank according to the odd or even number of each line. A DMA access step of fetching bitmap data of odd-numbered and even-numbered lines in a single DMA access in synchronization with memory bank switching in the storage step. 6. The storage control method according to claim 5, wherein said DMA access step performs access in burst units. 7. The storage control method according to claim 6, wherein said DMA access step divides a burst unit into two and assigns the highest address as a bank address. 8. The storage control method according to claim 5, further comprising a load step of reloading an offset address of a bank corresponding to an even line when the bank address is switched.