JP2001004695A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method dispensing with the manufacture of a burn-in board in performing a burn-in test. SOLUTION: The manufacturing method of this semiconductor device has a process for preparing a mounting board 1 equipped with signal-supplying wires for supplying semiconductor chips 3 with signals for performing a burn-in test and having ball grids 9 formed on one principal plane and electrically connected to the semiconductor chips 3, a process for CSP-mounting the semiconductor chips 3 on the other principal plane of the mounting board 1, a process for inserting the mounting board 1 into a thermostatic oven to perform burn-in test, and a process for cutting off portions of the mounting board 1 situated between the semiconductor chips 3. This eliminates the need for manufacturing a burn-in board in performing a burn-in test.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device which does not require a burn-in board when performing a burn-in test and a method of manufacturing the same.

[0002]

2. Description of the Related Art An example of a conventional method for manufacturing a semiconductor device will be described.

First, after a large number of semiconductor elements are formed on a semiconductor wafer by a photolithography process or the like, the semiconductor elements are individually separated and cut from the semiconductor wafer by dicing to form chips. Next, a semiconductor device (semiconductor package) is formed by connecting leads to the semiconductor element and performing resin molding.

After that, a burn-in test is performed on the semiconductor device. That is, a burn-in board to which a number of sockets are attached is prepared, the semiconductor device is stored in the socket, and the burn-in board is inserted into a thermostat. Next, the semiconductor device is kept at a constant temperature by raising the temperature in the constant temperature bath to a predetermined temperature, a power supply voltage rated or higher than the rated value is applied to the semiconductor device, and a signal close to the actual operation is applied to the input circuit of the semiconductor device. The screening is performed while applying a voltage.

[0005]

In the above-described conventional method for manufacturing a semiconductor device, it is necessary to manufacture a burn-in board for each type of semiconductor device. That is, since the socket attached to the burn-in board can only support a predetermined semiconductor device, and a different model requires a different socket, a burn-in board must be prepared for each model. . Therefore, this has been an obstacle to the cost reduction of the burn-in test.

In particular, a CSP (Chip Sized Package) which is a package miniaturized to a size close to a chip size.
Since it is difficult to manufacture a burn-in board when performing a burn-in test, the manufacturing cost of this burn-in board is further increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device which does not require a burn-in board when performing a burn-in test, and a method of manufacturing the same. is there.

[0008]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a substrate, a plurality of semiconductor chips mounted on a CSP on one main surface of the substrate,
And a terminal formed on the other main surface of the substrate and electrically connected to the semiconductor chip.
A signal supply line for supplying a signal for performing a burn-in test to the semiconductor chip is provided.

A method of manufacturing a semiconductor device according to the present invention includes a signal supply wiring for supplying a signal for performing a burn-in test to a semiconductor chip to be described later, and a terminal electrically connected to the semiconductor chip to be described later on one main surface. Preparing a substrate on which is formed, CSP mounting a semiconductor chip on the other main surface of the substrate, performing a burn-in test by inserting the substrate into a constant temperature bath, Cutting the substrates located between each other.

In the method of manufacturing a semiconductor device, a semiconductor chip is CSP-mounted on the other main surface of the substrate, and a burn-in test is performed by inserting the substrate into a constant temperature bath. The burn-in test can be easily performed without any problem. Therefore, there is no need to prepare a burn-in board when performing a burn-in test.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG.
FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. FIG. 2 is a configuration diagram showing a signal supply wiring on the mounting board shown in FIG. FIG. 3 is a diagram showing a boundary scan circuit built in the semiconductor chip shown in FIG.

As shown in FIGS. 1A and 1B, a semiconductor chip 3 has bumps 5 electrically connected to its internal circuit.
And a plurality of semiconductor chips 3 are CSP-mounted on the mounting substrate 1 via the bumps 5. The space between the lower surface of the semiconductor chip 3 and the upper surface of the mounting substrate 1 is sealed with a resin 7. A plurality of ball grids 9 are formed below the mounting substrate 1, and the ball grids 9 are electrically connected to the bumps 5 by connection means (not shown).

As shown in FIG. 2, a common power supply line 11 for supplying power to the semiconductor chip 3 is formed on the mounting substrate 1. Further, a common signal line 12 for controlling a test mode is formed on the mounting substrate 1, and the signal line 12 is electrically connected to the semiconductor chip 3. Further, the common SI wiring 13 and the SCK wiring 14 are formed on the mounting substrate 1, and the SI wiring 13 and the SCK wiring 1 are formed.
4 are electrically connected to the semiconductor chip 3.

As shown in FIG. 3, the semiconductor chip 3 incorporates a boundary scan circuit in a test mode. The boundary scan circuit includes a shift register 2
1, a NOR circuit 22, MUXes 23 and 24, and buffers 25 to 29.

Next, a method of manufacturing the semiconductor device will be described.

First, a common power supply wiring 11, signal wiring 12, SI wiring 13 and SCK wiring 14 shown in FIG. 2 are formed on one main surface of the mounting substrate 1, and a diagram is formed on the other main surface of the mounting substrate 1. The ball grid 9 shown in FIG.

Thereafter, a semiconductor chip 3 having a boundary scan circuit shown in FIG. 3 is prepared, and the semiconductor chip 3 is mounted on one main surface of the mounting substrate 1 by CSP.
That is, the resin 7 is placed on the pads (not shown) of the mounting substrate 1.
Is applied, the pads and the bumps 5 of the semiconductor chip 3 are aligned, and then the semiconductor chip 3 is mounted on the mounting substrate 1. In this way, the plurality of semiconductor chips 3 are mounted on the mounting board 1 having a relatively large area.

Next, a mounting defect of the CSP mounting is inspected.
The mounting failure is determined based on whether the contact between the bump 5 of the semiconductor chip 3 and the pad of the mounting board 1 is good.

That is, a high-level test mode signal is input to the boundary scan circuit, a high-level signal is output from the semiconductor chip 3, and a high-level potential is confirmed by the ball grid 9. Is determined.

Next, a dynamic burn-in test is performed on the mounting substrate 1 on which a plurality of semiconductor chips 3 as shown in FIG.

That is, the mounting substrate 1 is inserted into a constant temperature bath heated to a predetermined temperature, the mounting substrate 1 is kept at a constant temperature, and a power supply voltage rated for or exceeding the semiconductor chip 3 is supplied to the power supply wiring 11. And input a signal from the SI wiring 13 to the boundary scan circuit of the semiconductor chip 3. Thus, the circuit is operated and screening is performed. The screening is to remove a product having a latent defect by a test based on a failure mechanism in order to obtain a product quality and a reliability level.

Thereafter, individual CSPs are formed by dicing the mounting substrate 1 shown in FIG. That is, the CSP is formed by cutting a portion of the mounting substrate 1 located between the semiconductor chips 3 and separating the semiconductor chip 3 into individual semiconductor chips 3 mounted on the mounting substrate 1.

According to the above embodiment, a plurality of semiconductor chips 3 are mounted on the mounting substrate 1 by CSP, and a burn-in test is performed by inserting the mounting substrate 1 into a constant temperature bath. There is no need to create a dedicated burn-in board as in the method. Thus, the burn-in test can be easily performed, and the cost of the burn-in test can be reduced.

In this embodiment, a high-level test mode signal is input to the boundary scan circuit, a high-level signal is output from the semiconductor chip 3, and a high-level potential is confirmed by the ball grid 9. The mounting failure (contact failure) of the semiconductor chip 3 can be easily determined. Also, by alternately transferring data from the serial input and measuring the power supply current, it is possible to reject a short-circuit failure of an adjacent pad.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
In this embodiment, nine semiconductor chips are mounted on the mounting board 1 by CSP. However, the number of semiconductor chips mounted on one mounting board can be variously changed. CSP mounting is also possible.

[0027]

As described above, according to the present invention, a burn-in test is performed by mounting a semiconductor chip by CSP on the other main surface of a substrate and inserting the substrate into a thermostat. Therefore, it is possible to provide a semiconductor device that does not require a burn-in board when performing a burn-in test, and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1A is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a plan view of FIG.
FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.

FIG. 2 is a configuration diagram showing a signal supply wiring on the mounting board shown in FIG. 1;

FIG. 3 is a diagram showing a boundary scan circuit built in the semiconductor chip shown in FIG. 2;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 mounting board 3 semiconductor chip 5 bump 7 resin 9 ball grid 11 power supply wiring 12 signal wiring 13 SI wiring 14 SCK wiring 21 shift register 22 NOR circuit 23, 24 M
UX 25-29 buffer

Claims (2)

[Claims] A substrate; a plurality of semiconductor chips mounted on one main surface of the substrate by CSP; and terminals formed on the other main surface of the substrate and electrically connected to the semiconductor chip. And a signal supply line for supplying a signal for performing a burn-in test to the semiconductor chip. 2. A substrate having a signal supply wiring for supplying a signal for performing a burn-in test to a semiconductor chip to be described later and having, on one main surface, a terminal electrically connected to the semiconductor chip to be described later is prepared. A step of performing CSP mounting of a semiconductor chip on the other main surface of the substrate; a step of performing a burn-in test by inserting the substrate into a constant temperature bath; and cutting a substrate located between the semiconductor chips. A method for manufacturing a semiconductor device, comprising: