JP2000504187A - 信号のオフセット電圧を低減させる方法および回路装置 - Google Patents
信号のオフセット電圧を低減させる方法および回路装置Info
- Publication number
- JP2000504187A JP2000504187A JP9528194A JP52819497A JP2000504187A JP 2000504187 A JP2000504187 A JP 2000504187A JP 9528194 A JP9528194 A JP 9528194A JP 52819497 A JP52819497 A JP 52819497A JP 2000504187 A JP2000504187 A JP 2000504187A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- voltage
- circuit device
- offset voltage
- separating means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Circuits Of Receivers In General (AREA)
- Transceivers (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.信号内に生ずる直流電圧が信号線内の直流電圧の分離手段(C1)によっ て分離される際の前記信号のオフセット電圧を低減し、かつ前記オフセット電圧 を低減するために前記分離手段の出力(P2)に第2の信号(Vref ,S2)が 接続される方法において、前記第2の信号(S2)が前記分離手段の前に存在す る第1の信号(S1)に基づいて形成されることを特徴とする方法。 2.前記直流電圧の分離手段(C1)の前に存在する前記第1の信号(S1) がハイパスフィルタにかけられ、前記第2の信号(S2)が前記ハイパスフィル タにかけられた信号(S3)に基づいて形成されることを特徴とする請求項1に 記載の方法。 3.前記ハイパスフィルタにかける際に、前記信号線よりも高い下限周波数を 用いることを特徴とする請求項2に記載の方法。 4.前記第2の信号(S2)は、定電圧(Vref )が前記ハイパスフィルタに かけられた信号(S3)に加算されるような方法で形成されることを特徴とする 請求項2または3に記載の方法。 5.前記第2の信号(S2)が前記分離手段の出力(P2)に所定時間だけ接 続されることを特徴とする請求項1から4のいずれか一項に記載の方法。 6.信号線内に信号の直流電圧成分を分離するための分離手段(C1)と、第 2の信号(Vref ,S2)を前記分離手段(C1)の出力(P2)に接続するた めの手段(3)とを備える場合に信号のオフセット電圧を低減する回路装置にお いて前記分離手段(C1)の前に存在する第1の信号(S1)に基づいて前記第 2の信号(S2)を形成するための手段(4,5)を備えることを特徴とする回 路装置。 7.前記第2の信号(S2)を形成する手段は、前記第1の信号(S1)にフ ィルタをかけるハイパスフィルタ(4)を備えることを特徴とする請求項6に記 載の回路装置。 8.前記ハイパスフィルタ(4)の下限周波数が、信号線のインピーダンスと ともに前記分離手段(C1)によって形成される信号線の下限周波数よりも高い ことを特徴とする請求項7に記載の回路装置。 9.前記第2の信号(S2)を形成する手段は、基準電圧(Vref )を前記 第1の信号(S1)から導出した信号(S3)に加算するための加算器(5)を 備えることを特徴とする請求項6から8のいずれか一項に記載の回路装置。 10.前記第2の信号(S2)を接続するための前記手段(3)は、演算増幅 器(17,18)と、その出力に接続された制御可能な半導体スイッチ(15, 16)とを備えることを特徴とする請求項6から9のいずれか一項に記載の回路 装置。 11.前記第2の信号(S2)を接続するための前記手段(3)は、その出力 を高インピーダンス状態に制御可能である演算増幅器(l7a,l8a)を備え ることを特徴とする請求項9に記載の回路装置。 12.制御パルス(DCN)を形成し、これを前記第2の信号(S2)を前記 分離手段の出力(P2)に所定時間だけ接続するための手段(3)へと送るため の手段を備えることを特徴とする請求項7から11のいずれか一項に記載の回路 装置。 13.請求項1から6のいずれか一項に記載の方法、または請求項7から12 のいずれか一項に記載の回路装置の、ベースバンド信号のオフセット電圧を低減 するための直接変換受信器への利用。 14.請求項1から6のいずれか一項に記載の方法、または請求 項7から12のいずれか一項に記載の回路装置の、移動局の受信器への利用。 15.請求項1から6のいずれか一項に記載の方法、または請求項7から12 のいずれか一項に記載の回路装置の、ディジタル時分割移動通信システムへの利 用。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI960578A FI112131B (fi) | 1996-02-08 | 1996-02-08 | Menetelmä ja piirijärjestely signaalin erojännitteen pienentämiseksi |
FI960578 | 1996-02-08 | ||
PCT/FI1997/000072 WO1997029551A1 (en) | 1996-02-08 | 1997-02-06 | Method and circuit arrangement for reducing offset voltage of a signal |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000504187A true JP2000504187A (ja) | 2000-04-04 |
JP3866290B2 JP3866290B2 (ja) | 2007-01-10 |
Family
ID=8545363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52819497A Expired - Fee Related JP3866290B2 (ja) | 1996-02-08 | 1997-02-06 | 信号のオフセット電圧を低減させる方法および回路装置 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6144243A (ja) |
EP (1) | EP0875096B1 (ja) |
JP (1) | JP3866290B2 (ja) |
CN (1) | CN1175583C (ja) |
AU (1) | AU1604797A (ja) |
DE (1) | DE69733000T2 (ja) |
FI (1) | FI112131B (ja) |
WO (1) | WO1997029551A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2366460A (en) * | 2000-08-24 | 2002-03-06 | Nokia Mobile Phones Ltd | DC compensation for a direct conversion radio receiver |
GB2371931B (en) * | 2001-02-06 | 2004-10-20 | Nokia Mobile Phones Ltd | Processing received signals |
DE10131676A1 (de) * | 2001-06-29 | 2003-01-16 | Infineon Technologies Ag | Empfängeranordnung mit Wechselstrom-Kopplung |
KR100403814B1 (ko) * | 2001-08-13 | 2003-10-30 | 삼성전자주식회사 | 멀티칩 모듈을 이용하여 디.씨 옵셋을 감소시킨 다이렉트컨버젼 수신기 |
US6784751B2 (en) | 2001-09-18 | 2004-08-31 | Nokia Corporation | Method and apparatus providing resampling function in a modulus prescaler of a frequency source |
EP1306978B1 (fr) * | 2001-10-26 | 2005-05-25 | STMicroelectronics N.V. | Récepteur à conversion directe pour un système de communication utilisant une modulation à enveloppe non constante |
GB0130849D0 (en) * | 2001-12-22 | 2002-02-06 | Weatherford Lamb | Bore liner |
JP3805258B2 (ja) | 2002-01-29 | 2006-08-02 | 松下電器産業株式会社 | ダイレクトコンバージョン受信機 |
US6759881B2 (en) | 2002-03-22 | 2004-07-06 | Rambus Inc. | System with phase jumping locked loop circuit |
US6952123B2 (en) * | 2002-03-22 | 2005-10-04 | Rambus Inc. | System with dual rail regulated locked loop |
US7139542B2 (en) * | 2003-03-03 | 2006-11-21 | Nokia Corporation | Method and apparatus for compensating DC level in an adaptive radio receiver |
GB2402008B (en) * | 2003-04-30 | 2006-09-06 | Synad Technologies Ltd | Method and apparatus for DC offset control |
DE102004009038B4 (de) * | 2004-02-23 | 2005-12-29 | Zentrum Mikroelektronik Dresden Ag | Verfahren und Anordnung zur Reduktion eines dynamischen Offsets bei der Verarbeitung unsymmetrischer Signalfolgen |
WO2005086362A1 (ja) * | 2004-03-08 | 2005-09-15 | Matsushita Electric Industrial Co., Ltd. | 受信回路と、それを用いた受信装置および送受信装置 |
US8036622B2 (en) * | 2005-09-28 | 2011-10-11 | Qualcomm, Incorporated | DC offset cancellation circuit for a receiver |
GB0803710D0 (en) * | 2008-02-28 | 2008-04-09 | Nokia Corp | DC compensation |
CN105893992A (zh) * | 2016-05-31 | 2016-08-24 | 京东方科技集团股份有限公司 | 指纹识别结构和方法、显示装置 |
CN111970585B (zh) * | 2020-07-08 | 2022-07-15 | 武汉光迅科技股份有限公司 | 一种信号解调方法、装置、计算机存储介质及设备 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4514685A (en) * | 1981-07-27 | 1985-04-30 | Electric Power Research Institute, Inc. | Integrating circuit for use with Hall effect sensors having offset compensation means |
GB2175473A (en) * | 1985-05-17 | 1986-11-26 | Philips Electronic Associated | D.c. block capacitor circuit |
JPS62180603A (ja) * | 1986-02-03 | 1987-08-07 | Nec Corp | Scf用オフセツト補償回路 |
US4829594A (en) * | 1986-09-23 | 1989-05-09 | Motorola, Inc. | Adaptive correction of DC error transients |
GB2210744B (en) * | 1987-10-05 | 1992-01-29 | Marconi Instruments Ltd | Offset voltage nulling circuit |
US5212826A (en) * | 1990-12-20 | 1993-05-18 | Motorola, Inc. | Apparatus and method of dc offset correction for a receiver |
US5289059A (en) * | 1992-06-05 | 1994-02-22 | Nokia Mobile Phones, Ltd. | Switched capacitor decimator |
EP0594894B1 (en) * | 1992-10-28 | 1999-03-31 | Alcatel | DC offset correction for direct-conversion TDMA receiver |
US5748681A (en) * | 1995-10-27 | 1998-05-05 | Lucent Technologies Inc | Offset correction for a homodyne radio |
DE19628257C1 (de) * | 1996-07-12 | 1997-12-11 | Siemens Ag | Schaltungsanordnung zur Offset-Kompensation |
-
1996
- 1996-02-08 FI FI960578A patent/FI112131B/fi not_active IP Right Cessation
-
1997
- 1997-02-06 WO PCT/FI1997/000072 patent/WO1997029551A1/en active IP Right Grant
- 1997-02-06 JP JP52819497A patent/JP3866290B2/ja not_active Expired - Fee Related
- 1997-02-06 EP EP97902386A patent/EP0875096B1/en not_active Expired - Lifetime
- 1997-02-06 DE DE69733000T patent/DE69733000T2/de not_active Expired - Lifetime
- 1997-02-06 US US09/117,751 patent/US6144243A/en not_active Expired - Lifetime
- 1997-02-06 AU AU16047/97A patent/AU1604797A/en not_active Abandoned
- 1997-02-06 CN CNB971936064A patent/CN1175583C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP3866290B2 (ja) | 2007-01-10 |
FI960578A (fi) | 1997-08-09 |
EP0875096A1 (en) | 1998-11-04 |
CN1175583C (zh) | 2004-11-10 |
FI112131B (fi) | 2003-10-31 |
FI960578A0 (fi) | 1996-02-08 |
EP0875096B1 (en) | 2005-04-13 |
DE69733000D1 (de) | 2005-05-19 |
WO1997029551A1 (en) | 1997-08-14 |
AU1604797A (en) | 1997-08-28 |
US6144243A (en) | 2000-11-07 |
DE69733000T2 (de) | 2006-03-02 |
CN1215511A (zh) | 1999-04-28 |
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