JP2000349244A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method by which on resistance can be reduced, when sufficient positive voltage is applied to a gate, in a semiconductor device having a plurality of transistors with different threshold voltages. SOLUTION: In this semiconductor device provided with a first field effect transistor EFET and a second field effect transistor DFET having a threshold voltage lower than that of the first EFET, the first and second field effect transistors are provided with a low resistance region 11 which is formed at least in a first high resistance layer 4c under a gate electrode 9 and which contains impurities reverse in carrier and conductive type, and the first high resistance layer on the lower part of a gate of the first field effect transistor is formed thinner than that on the lower part of a gate of the second field effect transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a heterojunction field effect transistor applied to a microwave communication device and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, a mobile communication device such as a portable telephone has a microwave integrated circuit (MMIC; Monolithic Micro) having high-speed operation and low noise characteristics.
waveIC) has become indispensable. Recently, MMIC
, An RF switch I with a built-in digital control circuit
Low noise amplifier (LNA) with C or DC switch, etc.
Products with added value by incorporating circuits other than conventional functions have appeared on the market. In particular, switch ICs with a built-in logic circuit can be made smaller by reducing the number of external terminals, so that switch ICs are becoming mainstream.

In order to realize a switch IC having such a function in a monolithic manner, it is essential to form two transistors having different threshold voltages on the same chip. That is, a depletion type field effect transistor (hereinafter referred to as D) used in a conventional switch IC circuit.
FET. ) Together with an enhancement type field effect transistor (hereinafter, EFE) used in a logic circuit.
Let it be T. ) Must be formed on the same chip.

At present, a heterojunction field effect transistor (HFE), which is becoming mainstream as an MMIC device, is used.
T; Hetero Junction Field E
FIG. 4 is a cross-sectional view of an example of an IC in which an EFET and a DFET are mixedly mounted using an FFET as a basic element. As shown in FIG. 4, no impurity is added to the semi-insulating GaAs substrate 1 (und).
(Operated) A buffer layer 2 made of GaAs, a channel layer 3 made of GaAs to which impurities are not added, and a barrier layer 4 made of AlGaAs are sequentially stacked by epitaxial growth.

The barrier layer 4 is made of Al to which no impurity is added.
It has a structure in which three layers of a spacer layer 4a made of GaAs, an electron supply layer 4b made of AlGaAs doped with n-type impurities, and a gate contact layer 4c made of AlGaAs doped with no impurities are stacked. On the barrier layer 4, a source electrode 6 and a drain electrode 7 are formed via a cap layer 5. The cap layer 5 is made of, for example, GaAs containing a high concentration of n-type impurities. The barrier layer 4 or the cap layer 5 is covered with an insulating film 8, and the insulating film 8 has connection holes 8a, 8
b, 8c are formed.

A gate electrode 9 is formed on the barrier layer 4 between the source electrode 6 and the drain electrode 7. In many cases, the surface of the gate contact layer 4c immediately below the gate electrode 9 is partially etched to be thin (recess structure).
As the gate contact layer 4c in the recess portion is thinner, the threshold voltage of the transistor has a larger value on the positive (+) side. Therefore, it is possible to adjust the threshold voltage to an arbitrary value by controlling the thickness of the gate contact layer 4c.

As shown in FIG. 4, element isolation between an EFET and a DFET, between other elements (not shown), and a resistance portion is performed by mesa etching the epitaxial layer on the GaAs substrate 1. This etching is performed until at least a part of the buffer layer 2 is removed.

The field effect transistor (FE) having the above structure
In T), the threshold voltage is determined depending on the thickness of the gate contact layer 4c immediately below the gate electrode 9. Therefore, in order to make the threshold voltages of the two FETs different from each other, the thicknesses of the gate contact layers 4c in the recessed portions of these FETs may be made different from each other. EFE
When forming T, the threshold voltage is set to a positive value (0 V or more) by making the gate contact layer 4c in the recessed portion thinner than the lower portion of the gate of the DFET.

[0009]

However, in the semiconductor device having the conventional structure described above, the EFET and the DFET
In either case, the contact of the gate electrode becomes a Schottky junction. In the case of a Schottky junction, since a built-in voltage is lower than that of a pn junction, a sufficient positive voltage cannot be applied to the gate, and a problem occurs that a parasitic resistance component remains in a channel layer immediately below the gate. Therefore, in the DFET, the on-resistance, which is an important device parameter, cannot be sufficiently reduced. Also, when a logic circuit is formed by using a Schottky junction for the gate contact of the EFET, a sufficient logic amplitude cannot be obtained and a circuit design margin is reduced.

The present invention has been made in view of the above problems, and accordingly, the present invention relates to a semiconductor device having a plurality of transistors having different threshold voltages on the same substrate, wherein a sufficient positive voltage is applied to the gate. It is an object of the present invention to provide a semiconductor device that can apply ON voltage and reduce on-resistance. The present invention also provides a method for manufacturing a semiconductor device in which a plurality of transistors having different threshold voltages from each other and capable of applying a sufficient positive voltage to a gate can be formed over the same substrate in a simple process. The purpose is to do.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention comprises a first field-effect transistor on a substrate and a first field-effect transistor having a lower threshold voltage than the first field-effect transistor. And a second field-effect transistor, wherein the first field-effect transistor and the second field-effect transistor each include a carrier transit layer formed on the substrate and a carrier transit layer formed on the carrier transit layer. A carrier supply layer formed and containing a first conductivity type impurity having the same conductivity type as the carrier; a first high resistance layer formed on the carrier supply layer; A source electrode and a drain electrode formed at a predetermined interval; a gate electrode formed on the first high-resistance layer between the source electrode and the drain electrode; At least a low resistance region containing a second conductivity type impurity whose conductivity type is opposite to the first conductivity type, which is formed in a part of the first high resistance layer including at least the lower portion of the gate electrode. The first high-resistance layer below the gate electrode of the first field-effect transistor includes the first high-resistance layer below the gate electrode of the second field-effect transistor.
Characterized by being formed thinner than the high resistance layer.

The semiconductor device of the present invention is preferably characterized in that the carrier transit layer is made of a semiconductor to which no impurities are added. The semiconductor device of the present invention is preferably characterized in that the carrier supply layer is made of a semiconductor having a wider band gap than the semiconductor constituting the carrier transit layer. The semiconductor device of the present invention is preferably characterized in that the first high-resistance layer has a wider band gap than the semiconductor constituting the carrier transit layer, and is made of a semiconductor to which no impurity is added. I do.

The semiconductor device of the present invention preferably has a wider band gap between the carrier transit layer and the carrier supply layer than a semiconductor constituting the carrier transit layer, and is doped with impurities. A second high-resistance layer made of a semiconductor is formed. The semiconductor device of the present invention is preferably characterized in that a buffer layer made of a semiconductor to which no impurity is added is formed between the substrate and the carrier transit layer. In the semiconductor device of the present invention, preferably, the source electrode and the drain electrode have a narrower band gap than a semiconductor forming the first high-resistance layer, and include a cap layer containing a first conductivity type impurity. Are formed on the first high resistance layer through the respective layers.

The semiconductor device according to the present invention is preferably characterized in that the first field-effect transistor is an enhancement-type field-effect transistor. The semiconductor device of the present invention is preferably characterized in that the second field-effect transistor is a depletion-type field-effect transistor.

The semiconductor device according to the present invention is preferably characterized in that a trench for element isolation is provided between the first field-effect transistor and the second field-effect transistor. The semiconductor device of the present invention is preferably characterized in that a high resistance region for element isolation is provided between the first field effect transistor and the second field effect transistor.

The semiconductor device according to the present invention is preferably characterized in that the carrier is an electron. The semiconductor device of the present invention is preferably characterized in that the substrate is made of a group III-V compound semiconductor. The semiconductor device of the present invention
Preferably, the substrate is a GaAs substrate. The semiconductor device of the present invention is preferably characterized in that the carrier supply layer contains silicon as the first conductivity type impurity. The semiconductor device of the present invention is preferably characterized in that the low resistance region contains zinc as the second conductivity type impurity.

Thus, an arbitrary threshold voltage can be independently set for a plurality of transistors formed on the same substrate and having different threshold voltages. According to the semiconductor device of the present invention, a recess is formed in a barrier layer at a gate contact portion, and a low-resistance region having a conductivity type opposite to that of a channel is formed below a gate electrode. By controlling the depth of the recess and the depth of impurity diffusion in the low-resistance region independently of each transistor, the threshold voltage of each transistor can be controlled with high precision.

Further, according to the semiconductor device of the present invention, since the gate portion is a pn junction, a larger positive voltage can be applied to the gate electrode than in the case of the Schottky junction. Therefore, it is possible for the EFET constituting the logic circuit to have a sufficient logic amplitude larger than that of the HFET using the Schottky junction. As a result, a margin for circuit design can be increased.
Similarly, a pn junction is formed at the gate of the DFET, and a sufficiently large positive voltage can be applied to the gate electrode. Therefore, the parasitic resistance component generated in the channel immediately below the gate can be reduced, and the ON state can be reduced. Resistance can be reduced.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a first field-effect transistor on a substrate; Forming a carrier transit layer in the first and second field effect transistor forming regions on the substrate; and forming a carrier transit layer on the carrier transit layer. Forming a carrier supply layer containing a first conductivity type impurity having the same conductivity type as the carrier; forming a high resistance layer on the carrier supply layer; and forming the first field effect transistor forming region Forming a recess by making a part of the high-resistance layer thinner than the high-resistance layer in the second field-effect transistor forming region; and forming the first field-effect transistor. The recess of Njisuta formation region,
And forming a low-resistance region by allowing a part of the high-resistance layer in the second field-effect transistor formation region to contain a second conductivity type impurity whose conductivity type is opposite to the first conductivity type; Forming a source electrode and a drain electrode on the high-resistance layer so as to face each other in the low-resistance region; and forming a gate electrode on the low-resistance region.

In the method for manufacturing a semiconductor device according to the present invention, preferably, the step of forming the recess is a step of selectively etching the high-resistance layer. In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of forming the low resistance region is a step of diffusing the second conductivity type impurity in a gas phase. In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of forming the carrier traveling layer, the carrier supply layer, and the high resistance layer includes:
Each of the processes is characterized by forming a semiconductor layer by epitaxial growth. In the method of manufacturing a semiconductor device according to the present invention, preferably, the carrier transit layer, the carrier supply layer, and the high resistance layer between the first field effect transistor and the second field effect transistor are removed. And forming a device isolation region.

According to the method of manufacturing a semiconductor device of the present invention,
A low-resistance region for reducing gate resistance can be formed in a plurality of transistors having different threshold voltages in the same step. A recess is formed under the gate of the transistor for relatively increasing the threshold voltage before forming the low-resistance region. Thus, a plurality of transistors whose threshold voltages are independently controlled can be formed on the same chip by a simple process.

[0022]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of the semiconductor device of the present embodiment. An EFET and a DFET are formed on a GaAs substrate 1 separated by an element isolation region I. Since the EFET and the DFET shown in FIG. 1 have a common structure except for the contact part of the gate electrode, the EFET and the DF
Each part of the ET is denoted by a common symbol.

As shown in FIG. 1, in each transistor, a channel layer 3 and a barrier layer 4 are sequentially laminated on a substrate 1 via a buffer layer 2. The barrier layer 4 has a three-layer structure in which a spacer layer 4a, an electron supply layer 4b, and a gate contact layer 4c are sequentially stacked from the substrate 1 side. A source electrode 6 and a drain electrode 7 are formed above the barrier layer 4 of each transistor via two cap layers 5 respectively. Further, an insulating film 8 is formed so as to cover the barrier layer 4 or the cap layer 5.
The source electrode 6 and the drain electrode 7 are formed in connection holes 8a and 8b formed in the insulating film 8, respectively.

A gate electrode 9 is formed between the source electrode 6 and the drain electrode 7. EFET gate electrode 9
The lower gate contact layer 4c has a recess 10 formed on the surface, and the gate contact layer 4c is partially thinned. A p-type low-resistance region 11 is formed below the gate electrodes 9 of the EFET and the DFET. In the above-described semiconductor device, the channel layer 3 serves as a current path between the source electrode 6 and the drain electrode 7.

Hereinafter, each layer constituting the semiconductor device of this embodiment will be described in detail. For example, the substrate 1 contains almost no impurities and has a resistivity of 10 ⁶ to 10 ^8.
A substrate made of semi-insulating GaAs single crystal of about Ω · cm is used. The GaAs substrate 1 is a bulk crystal grown at a GaAs melting point (1238 ° C.) and contains many lattice defects such as point defects and dislocations. Therefore, if the active epitaxial layer is grown directly on the substrate 1, the epitaxial layer close to the substrate 1 in the initial stage of growth does not become a high-quality crystal.

The buffer layer 2 is made of, for example, undoped GaAs and has a thickness of, for example, about 3 to 5 μm by epitaxial growth. If there is no buffer layer 2, for example, the source - or hysteresis is observed in the plot of the drain current (I-V characteristic) with respect to the drain voltage, a problem transconductance G _m is decreased in a low current region occurs. To prevent this, a buffer layer 2 is provided between the substrate 1 and the active epitaxial layer.

As a material of the channel layer 3, a semiconductor having a band gap narrower than that of the semiconductor forming the barrier layer 4, for example, GaAs to which impurities are not added is used. Electrons are supplied to the channel layer 3 from the electron supply layer 4b of the barrier layer 4, and the supplied electrons are accumulated. The channel layer 3 has a thickness of about 10 to 15 nm and a number of atomic layers of 20 to 15 nm.
It is formed as extremely thin as about 30 layers. Therefore, there is no degree of freedom of electron transfer in the direction perpendicular to the heterojunction plane, and the property of a two-dimensional electron gas (2DEG) is exhibited. Since the channel layer 3 contains almost no impurities and the electrons and donor ions are spatially separated, electrons traveling in the channel are not scattered by the donor ions. Therefore, the channel layer 3 becomes an electron transit layer in which electrons move at a high speed.

The barrier layer 4 is made of III-V group compound semiconductor such as Al _x Ga _1-x As mixed crystal, in the case of using the Al _x Ga _1-x As as the barrier layer 4 is usually, Al
Is 0.2 to 0.3. The spacer layer 4a in contact with the channel layer 3 is a high-resistance layer to which no impurity is added, and has a thickness of, for example, about 2 nm. The spacer layer 4a is provided for the purpose of preventing the potential of a high-concentration impurity contained in the electron supply layer 4b from infiltrating the channel layer 3 and causing scattering of electrons.

The electron supply layer 4b contains, for example, silicon as an n-type impurity at 1.0 × 10 ^{12 to} 2.0 × 10 ¹² atoms.
s / cm ^{2 is} added, and the thickness of the electron supply layer 4b is, for example, about 4 nm. The gate contact layer 4c is a high resistance layer to which no impurity is added, and has a thickness of, for example, 100
nm. Between the electron supply layer 4b and the gate electrode 9, by the gate contact layer 4c having a band gap wider than the semiconductor constituting the channel layer 3 is formed, the transconductance G _m and gate
The linearity of the source-to-source capacitance C _gs with respect to the gate voltage V _g is improved, and the power addition efficiency is increased.

On the gate contact layers 4c of the EFET and the DFET, two cap layers 5 are formed at appropriate intervals. The cap layer 5 is made of, for example, silicon as an n-type impurity at 4 × 10 ¹⁸ atoms /
GaAs containing about ³ cm ³ and a thickness of 50 to 1
It is about 00 nm. The connection resistance is generated by forming the gate contact layer 4c, which is a high resistance layer, on the electron supply layer 4b. However, the formation of the cap layer 5 reduces the connection resistance.

The insulating film 8 formed on the gate contact layer 4c or the upper layer of the cap layer 5 and the element isolation region I is made of, for example, a silicon nitride film, and has a thickness of, for example, 30.
It is about 0 nm. Source electrode 6 and drain electrode 7
Is gold (Au) − sequentially laminated on the upper layer of the cap layer 5.
Germanium (Ge) alloy, nickel (Ni) and A
are alloyed with each other to form an ohmic junction with the cap layer 5.

A p-type low-resistance region 11 is formed on the surface of the recess 10 below the gate electrode 9 for the EFET, and below the gate electrode 9 for the DFET. p
The low-resistance region 11 is formed of, for example, zinc (Z
n) in an amount of about 1.0 × 10 ¹⁹ atoms / cm ³ . If the diffusion depths of the p-type low-resistance regions 11 of the EFET and the DFET are the same, these p-type low-resistance regions 11 can be formed by the same process. EFET and DF
When the impurity diffusion depth of the p-type low-resistance region 11 of the ET is the same, the etching depth of the recess 10 of the EFET is adjusted to obtain a desired threshold voltage.

As described above, according to the semiconductor device of this embodiment, the diffusion depth of the p-type low resistance region 11 and the recess 1
By controlling the thickness of the zero-portion gate contact layer 4c, an arbitrary threshold voltage can be set independently for the EFET and the DFET. Further, according to the semiconductor device of the present embodiment, since the gate portion is a pn junction, a larger positive voltage can be applied to the gate electrode than in the case of the Schottky junction. Therefore, it is possible for the EFET constituting the logic circuit to have a sufficient logic amplitude larger than that of the HFET using the Schottky junction. As a result, a margin for circuit design can be increased. Similarly, a pn junction is formed at the gate of the DFET, and a sufficiently large positive voltage can be applied to the gate electrode. Therefore, the parasitic resistance component generated in the channel immediately below the gate can be reduced, and the ON state can be reduced. Resistance can be reduced.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 2A, a buffer layer 2 is formed on a substrate 1 made of, for example, semi-insulating GaAs as a buffer layer 2 without adding impurities.
The s layer is grown epitaxially. The GaAs layer is formed by, for example, vapor phase epitaxial growth. GaAs
In order to make s vapor-phase epitaxial growth, a chloride method using AsCl ₃ as a supply source of As, and AsH ₃ /
There is a hydride method using PH _3, usually carried out by a hydride method. Typically, the buffer layer is epitaxially grown at the same time as the active layer above. By forming the buffer layer 2, it is possible to improve the crystallinity of the operation epitaxial layer formed thereon. The thickness of the buffer layer 2 is, for example, 3 to 5 μm.

The channel layer 3 is epitaxially grown on the buffer layer 2. As the channel layer 3, a semiconductor having a band gap narrower than that of the semiconductor forming the barrier layer 4, for example, a layer made of GaAs to which impurities are not added is formed extremely thin, for example, to a thickness of about 10 nm. The channel layer 3 can be suitably formed by molecular beam epitaxial growth in addition to the vapor phase epitaxial growth similar to the buffer layer 2. The molecular beam epitaxial growth method has a lower semiconductor layer deposition rate than other epitaxial growth methods. For example, when growing GaAs on a GaAs substrate, the growth rate is 0.1 to 2 μm.
/ H. Therefore, although the molecular beam epitaxy is disadvantageous for forming a thick semiconductor layer, it is suitable for forming a film while controlling the crystallinity at an atomic size level like an operating epitaxial layer of an HFET.

As a barrier layer 4 above the channel layer 3, for example, a spacer layer 4a made of an AlGaAs layer containing no impurity, an electron supply layer 4b made of an AlGaAs layer containing an n-type impurity, and an AlG
The gate contact layer 4c made of an aAs layer is sequentially epitaxially grown. Al formed as barrier layer 4
_{In the x} Ga _{1 -x} As mixed crystal, the Al composition ratio x is 0.2
０．３0.3. The thickness of each layer of the laminated film is, for example, 2 nm for the spacer layer 4a, 4 nm for the electron supply layer 4b, and 100 nm for the gate contact layer 4c.

The electron supply layer 4b contains, for example, silicon (Si) as an n-type impurity in an amount of 1.0 × 10 ^{12 to} 2.0 × 10 ^12.
Atomics / cm ^{2 is} added, and Si is introduced at the stage of epitaxial growth. If Si is diffused after forming the AlGaAs layer, a heat treatment at a temperature higher than the crystal growth temperature (500 to 600 ° C.) of the operation epitaxial layer is required, and the crystal structure of the thin epitaxial layer is damaged. Si is frequently used as an n-type impurity for the AlGaAs layer, but in addition to Si, sulfur (S) and selenium (S
e), tin (Sn) and the like can also be used.

Each layer constituting the barrier layer 4 can be formed by a method such as vapor phase epitaxial growth or molecular beam epitaxial growth. To grow an AlGaAs layer by vapor phase epitaxial growth, Al is converted to Al (C
H ₃ ) ₃ and Al (C ₂ H ₅ ) ₃ are supplied in the vapor phase as an organic metal (organic metal vapor phase epitaxy). An n-type Ga layer serving as a cap layer 5 is formed on the gate contact layer 4c.
The As layer 5 'is epitaxially grown to a thickness of, for example, about 50 to 100 nm. The n-type GaAs layer 5 ′ contains, for example, Si as an n-type impurity.

After that, the active epitaxial layer other than the transistor formation region is removed by mesa etching to form an element isolation region I. This mesa etching is performed to a depth at which at least a part of the buffer layer 2 is removed. The groove for element isolation may have a depth reaching the substrate 1. Alternatively, instead of performing the mesa etching, O ⁺ or B ⁺ may be ion-implanted to form a high-resistance region to be used as an element isolation region. When ion implantation is performed to form an element isolation region, annealing is not required, and does not affect the crystal structure of the epitaxial layer.

Next, as shown in FIG. 2B, the n-type GaAs layer 5 'is selectively removed by etching using a resist as a mask, and a cap layer is formed in a region where the source electrode 6 and the drain electrode 7 are formed. 5 is formed. This etching exposes the barrier layer 4 in the gate electrode formation region. Subsequently, the barrier layer 4 or the cap layer 5 and the trench of the element isolation region I are covered, for example, by chemical vapor deposition (CVD).
A silicon nitride film is deposited on the insulating film 8 to form an insulating film 8.

Next, as shown in FIG.
The insulating film 8 in the gate electrode formation region is selectively removed by etching to form a connection hole 8c. Subsequently, FIG.
As shown in FIG. 2A, etching is performed using the insulating film 8 as a mask to selectively remove the gate contact layer 4c in the gate electrode formation region of the EFET. Thereby, the recess 10 is formed. This etching depth depends on the E
It is set appropriately according to the threshold voltage of the FET. Next, as shown in FIG. 3B, etching is performed using the resist 12 as a mask to selectively remove the insulating film 8 in the gate electrode formation region of the DFET. Thereby, DFET
A connection hole 8c is formed in the portion. Then, resist 12
Is removed.

Next, as shown in FIG.
and a p-type impurity such as Z
n is vapor-phase diffused at about 600 ° C. Thereby, EF
A p-type low resistance region 11 is formed on the surface (portion of the recess 10) of the gate contact layer 4c of the ET and the surface of the gate contact layer 4c of the DFET, respectively. In the gas phase diffusion of zinc, for example, diethyl zinc (DEZ; Zn (C ₂ H ₅ ) ₂ ) or dimethyl zinc (DMZ; Zn (CH ₃ ) ₂ ) which is a liquid organic metal and arsine (AsH)
_Use gas containing ₃ ). Diethyl zinc or dimethyl zinc is an organic metal that is liquid at room temperature, and is generally used as a zinc gas phase diffusion source for compound semiconductors. This zinc compound becomes a gaseous state when bubbling high-purity hydrogen as a carrier gas, and is introduced into the furnace tube.

Arsine is obtained by adding arsenic having a high vapor pressure to the barrier layer 4.
Is supplied for the purpose of preventing the compound semiconductor from evaporating from the surface and changing the composition of the compound semiconductor. The vapor phase diffusion of zinc can be performed at a temperature approximately equal to the crystal growth temperature (500 to 600 ° C.) of the active epitaxial layer, and prevents the crystal structure of the active epitaxial layer, particularly crystal damage at the heterojunction interface. Is done.

Next, the p-type low resistance region 1 at the bottom of the connection hole 8c
A metal layer to be the gate electrode 9 is formed so as to be in contact with 1. For example, titanium (Ti), platinum (Pt), and Au are stacked in a thickness of 30 nm / 50 nm / 120 nm, respectively, by an electron beam evaporation method or the like. A resist having a gate electrode pattern is formed on the metal laminated film. Using the resist as a mask, the metal laminated film is processed by, for example, ion milling using argon gas to form a gate electrode 9.

Subsequently, as shown in FIG.
The insulating film 8 in the formation region and the formation region of the drain electrode 7 is selectively etched, and the connection holes 8a and 8b are respectively formed by EF.
Formed on ET and DFET. For example, an Au—Ge alloy and Ni are sequentially deposited on the connection holes 8a and 8b, and then the deposited metal layer is patterned. Then, for example, 4
A heat treatment at about 00 ° C. is performed to form an alloy to form a source electrode and a drain electrode. When the electrode metal is alloyed by heat treatment, ohmic properties are improved. Through the above steps, the semiconductor device shown in FIG. 1 is obtained.

According to the method of manufacturing a semiconductor device of the present embodiment, it becomes possible to form a p-type low-resistance region in an EFET and a DFET having different threshold voltages in the same step. Therefore, a plurality of transistors whose threshold voltages are independently controlled can be formed on the same chip by a simple process.

Embodiments of the semiconductor device and the method of manufacturing the same according to the present invention are not limited to the above description. For example, HF
The heterojunction formed in the ET is replaced with the above GaAs / Al
Instead of GaAs, InGaAs / AlInAs can be used. Further, the thickness of each layer constituting the operation epitaxial layer can be appropriately changed according to the design of the semiconductor device. In addition, various changes can be made without departing from the gist of the present invention.

[0048]

According to the semiconductor device of the present invention, in a semiconductor device having a plurality of transistors having different threshold voltages on the same substrate, a sufficient positive voltage is applied to the gate,
The on-resistance can be reduced. According to the method for manufacturing a semiconductor device of the present invention, it is possible to form a plurality of transistors having different threshold voltages on the same substrate and capable of applying a sufficient positive voltage to a gate in a simple process. Become.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating substrate (GaAs substrate), 2 ... Buffer layer, 3 ... Channel layer, 4 ... Barrier layer, 4a ... Spacer layer, 4b ... Electron supply layer, 4c ... Gate contact layer, 5
... cap layer, 5 '... n-type GaAs layer, 6 ... source electrode, 7 ... drain electrode, 8 ... insulating film, 8a, 8b, 8c
... Connection hole, 9 gate electrode, 10 recess, 11 p-type low-resistance region, 12 resist.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/338 29/812

Claims (21)

[Claims] A first field-effect transistor on a substrate;
A semiconductor device comprising: a second field-effect transistor having a threshold voltage lower than that of the first field-effect transistor, wherein the first field-effect transistor and the second field-effect transistor are each provided on the substrate A carrier supply layer formed on the carrier travel layer, the carrier supply layer containing a first conductivity type impurity having the same conductivity type as the carrier, and a first carrier supply layer formed on the carrier supply layer. A high-resistance layer, a source electrode and a drain electrode formed at predetermined intervals on the first high-resistance layer, and on the first high-resistance layer between the source electrode and the drain electrode. A second conductive layer formed on a part of the first high-resistance layer including at least the lower part of the gate electrode, the second conductive layer having a conductivity type opposite to the first conductivity type. A low-resistance region containing an impurity, wherein the first high-resistance layer below the gate electrode of the first field-effect transistor includes a first high-resistance layer below the gate electrode of the second field-effect transistor. Semiconductor device formed thinner than the high-resistance layer. 2. The semiconductor device according to claim 1, wherein said carrier transit layer is made of a semiconductor to which no impurity is added. 3. The semiconductor device according to claim 2, wherein said carrier supply layer is made of a semiconductor having a wider band gap than a semiconductor constituting said carrier transit layer. 4. The first high resistance layer has a wider band gap than a semiconductor constituting the carrier transit layer,
4. The semiconductor device according to claim 3, comprising a semiconductor to which no impurities are added. 5. A second high resistance layer made of a semiconductor which has a wider band gap between the carrier transit layer and the carrier supply layer than a semiconductor constituting the carrier transit layer and has no impurity added thereto. 4. The semiconductor device according to claim 3, wherein a layer is formed. 6. The semiconductor device according to claim 1, wherein a buffer layer made of a semiconductor to which no impurity is added is formed between the substrate and the carrier transit layer. 7. The source electrode and the drain electrode each have a narrower band gap than a semiconductor forming the first high-resistance layer, and each of the source electrode and the drain electrode have a first conductive type impurity via a cap layer. The semiconductor device according to claim 4, wherein the semiconductor device is formed on the first high resistance layer. 8. The semiconductor device according to claim 1, wherein said first field effect transistor is an enhancement type field effect transistor. 9. The field effect transistor according to claim 8, wherein said second field effect transistor is a depletion type field effect transistor.
13. The semiconductor device according to claim 1. 10. The semiconductor device according to claim 1, further comprising an element isolation groove between said first field effect transistor and said second field effect transistor. 11. The semiconductor device according to claim 1, further comprising a high resistance region for element isolation between said first field effect transistor and said second field effect transistor. 12. The semiconductor device according to claim 1, wherein said carriers are electrons. 13. The semiconductor device according to claim 1, wherein said substrate is made of a group III-V compound semiconductor. 14. The substrate according to claim 1, wherein said substrate is a GaAs substrate.
4. The semiconductor device according to 3. 15. The semiconductor device according to claim 13, wherein said carrier supply layer contains silicon as said first conductivity type impurity. 16. The semiconductor device according to claim 13, wherein said low resistance region contains zinc as said second conductivity type impurity. 17. A method for manufacturing a semiconductor device, comprising: forming a first field-effect transistor and a second field-effect transistor having a lower threshold voltage than the first field-effect transistor on a substrate, Forming a carrier transit layer in the first and second field effect transistor formation regions on the substrate; and a carrier containing a first conductivity type impurity having the same conductivity type as the carrier on the carrier transit layer. Forming a supply layer; forming a high-resistance layer on the carrier supply layer; forming a part of the high-resistance layer in the first field-effect transistor formation region into a second field-effect transistor; Forming a recess by making the region thinner than the high-resistance layer; and forming the recess in the first field-effect transistor formation region and the second field-effect transistor. Forming a low-resistance region by making a part of the high-resistance layer in the transistor formation region contain a second conductivity-type impurity whose conductivity type is opposite to the first conductivity type; and forming a source on the high-resistance layer. A method for manufacturing a semiconductor device, comprising: forming an electrode and a drain electrode so as to face each other in the low-resistance region; and forming a gate electrode on the low-resistance region. 18. The method according to claim 17, wherein the step of forming the recess is a step of selectively etching the high-resistance layer. 19. The method according to claim 1, wherein the step of forming the low resistance region is a step of diffusing the second conductivity type impurity in a gas phase.
8. The method for manufacturing a semiconductor device according to item 7. 20. The method of manufacturing a semiconductor device according to claim 17, wherein the step of forming the carrier traveling layer, the carrier supply layer, and the high resistance layer is a step of forming a semiconductor layer by epitaxial growth. 21. removing the carrier transit layer, the carrier supply layer and the high resistance layer between the first field effect transistor and the second field effect transistor;
The method for manufacturing a semiconductor device according to claim 17, further comprising a step of forming an element isolation region.