JP2000347422A - Fine pattern forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a fine pattern forming method that can efficiently form a fine integrated resist pattern on a semiconductor substrate through a silylation process and can effectively regenerate and use the substrate without damaging the substrate if a defective pattern is produced in a production process. SOLUTION: When a resist pattern is formed on a substrate 801 with a resist layer 901, the resist layer 901 is formed on an inorganic or organic film underlayer 802 and the resist pattern is formed through a silylation process. If the resulting resist pattern is judged to be a reject in a quality inspecting step, the underlayer on the substrate with an SiOx layer, a silylated layer and a resist layer is removed and a fine resist pattern is formed again on the regenerated substrate by the above method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fine pattern formed on a semiconductor substrate or the like, and more particularly, to manufacturing a finely integrated semiconductor device by using a silylation process. The present invention relates to a method for forming a fine pattern that can efficiently form a pattern and that can effectively reproduce and use a substrate when it is determined that the quality is poor in a manufacturing process.

[0002]

2. Description of the Related Art Conventionally, in a manufacturing process of a semiconductor integrated circuit, a photolithography technique has been used when a design circuit is transferred to a substrate. Exposure sources used in the photolithography process in semiconductor manufacturing in recent years include:
Mercury lamp g-line (wavelength: 463 nm), i-line (wavelength:
365 nm) is often used, and a KrF excimer laser (wavelength: 248) is used to obtain higher resolution.
nm) or ArF excimer laser (wavelength: 193n)
Use of an exposure apparatus that uses m) as a light source is being studied. As described above, light exposure is used up to a minimum line width of 0.5 μm, but recently, an exposure method with a minimum line width of 0.1 μm or less, which allows a finer pattern to be formed by a focused ion beam, has also been proposed. .

[0003] The minimum dimension of a pattern which can be exposed and transferred by these semiconductor elements can be appropriately used usually depending on the wavelength of the above-mentioned exposure type. Further, when performing exposure transfer, a defocus margin is required due to a step of the substrate, aberration of a lens of the exposure apparatus, etc., but when the pattern is miniaturized to about the exposure wavelength, the defocus amount is an allowable defocus amount for pattern formation. The depth of focus decreases sharply. Furthermore,
When the pattern is miniaturized, the contrast of the pattern optical image decreases, and the exposure margin, which is a margin for the exposure amount (effective exposure amount including the reflected light from the underlying substrate), decreases.

As described above, the miniaturization of semiconductor integrated circuits is in a direction of further progress, and recently, there is a general tendency to use an exposure source having a shorter wavelength in particular. However, to introduce a new exposure device with a short exposure wavelength,
It requires a large investment in its equipment and development. In addition, in the short wavelength region below the ArF excimer, devices and materials such as an exposure light source, a glass material and a resist used for an exposure apparatus are currently in a development stage, and a material having performance that can withstand production has not been obtained. Is the actual situation.

Therefore, it is increasingly important for companies to form a pattern having a wavelength equal to or shorter than the exposure wavelength while securing the depth of focus by using a current exposure apparatus in some way, as described above, due to cost reduction and the like. It is also an issue. Under these circumstances, as a solution to these problems, conventionally, a silylation process for resolving only the surface layer of the resist layer has been proposed, for example, as shown in FIGS.
A silylation process using a positive resist shown in (d) is a typical example of a solution to these problems.

That is, in FIG. 1A, a resist is applied on a substrate (or a film to be processed). Then, FIG.
As shown in (b), a circuit pattern (or a resist pattern) is exposed and transferred onto a resist layer via a pattern mask. The exposed portion of the resist is crosslinked by a photoreaction. Next, as shown in FIG. 1 (c), when the substrate surface is exposed to a silylating agent vapor, a silylated layer is selectively formed only on unexposed portions which are non-crosslinked pattern portions. Then, as shown in FIG. 1 (d), O ₂
When anisotropic etching (dry development) is performed with plasma, the surface of the silylated layer formed in FIG. 1C is used as a SiOx mask to form a positive resist pattern.

As described above, by passing the resist layer through the silylation process, only the unsilylated resist surface layer can be resolved, and a fine pattern can be formed. In addition, since a resist having a high light absorptance can be appropriately used, reflected light from a substrate serving as a base can be suppressed, a standing wave effect is reduced, and pattern dimensional accuracy is improved. .

[0008]

As already mentioned above,
A silylation process has been proposed as a method for forming a fine circuit pattern on a semiconductor substrate, but has various problems as described below, and has not been practically used yet. That is, in these manufacturing processes, conventionally, usually, a post-processing step of stripping the resist after processing the base film, or a resist such as a step of stripping the resist due to a defect caused by exposure and regenerating the substrate. Peeling is required. In particular, through the silylation process, there is a tendency that resist stripping during this regeneration step becomes extremely difficult.

That is, when forming a resist pattern through a silylation process, (1) first, residues are generated in a place where there is essentially no pattern in dry development. This occurs, as shown in FIG. 1 (e), when the silylating agent penetrates into a site which is not originally silylated, and a thin silylated layer is formed on the resist surface. Therefore, as shown in FIG. 1 (f), in dry development by oxygen etching, the silylated layer on the resist surface is made of SiOx.
When the silylated layer is thin, it is partially sputtered, and when the exposed resist portion is etched and removed, the remaining SiOx falls on the substrate to become a residue. (2) In order to prevent the residue in the dry development of (1), there is a method of removing an excess silylated layer on the surface by etching with a fluorine-based gas before oxygen etching (usually a break). -Called through). However, when the break-through is insufficient, the silylation is excessive, or the exposure dose is insufficient and the crosslinking reaction is insufficient, the residue tends to be similarly generated. (3) Further, in the exposure, if the exposure amount is inappropriate or the focus shifts, the pattern collapses at the time of dry development as shown in FIG. 1 (g). These are excessive oxygen etching at the time of dry development,
The resist under the SiOx-silylation layer is etched from the lateral direction, and the pattern falls or the SiOx-
The silylated layer falls onto the substrate and the SiOx-silylated layer adheres directly to the substrate. When the thus generated residue or the SiOx-silylated layer on the pattern layer directly adheres to the substrate,
These removals are conventionally known, for example, an amine-based stripping solution, diluted hydrofluoric acid, sulfuric acid-aqueous peroxide solution, ashing containing a fluorine-based gas, brushing or the like may be used alone or in combination. It makes removal extremely difficult.

For example, when dissolving the surface layer of the substrate to which the residue and the like adhere, it is usually necessary to dissolve the surface layer by 20 nm or more. For example, although it has been proposed to dissolve and remove the surface layer by about several nm, it is difficult to completely lift off the SiOx residue as described above, and as a result, any of the conventional removal methods is used. ,
It is extremely difficult to avoid damage to the substrate, and as a result, it is difficult to regenerate a reusable substrate.

Accordingly, an object of the present invention is to provide a method of forming a resist pattern efficiently by using a silylation process in manufacturing a finely integrated semiconductor device. It is an object of the present invention to provide a method for forming a fine pattern (or a resist pattern) using a silylation process that can surely and effectively reproduce a substrate or the like even when it is determined that the quality is poor in a quality inspection process. .

[0012]

Means for Solving the Problems In view of the above problems, the present inventor has conducted intensive studies. As a result, a resist layer was formed on a substrate by using a silylation process to form a fine pattern of an integrated semiconductor circuit. By applying a base layer such as an organic film without directly forming a film on the substrate, usually, even if a defective product that can occur in the quality inspection process occurs, without damaging the substrate by a conventionally known processing method, The inventor has found that the entire underlayer can be removed and the substrate is surely regenerated, thereby completing the present invention.

That is, according to the present invention, when a resist pattern is formed on a resist layer provided on a film to be processed or a substrate, the resist layer is formed on a base layer of an inorganic film or an organic film, Also, the present invention provides a method for forming a fine pattern, wherein the resist pattern is formed through a silylation process.

Further, according to the present invention, when a fine pattern is formed in this way, a predetermined quality value is not satisfied in a defect inspection such as a line width measurement of a pattern, a measurement of overlay accuracy, or the like. When it is confirmed that such a residue or the like is generated, the resist can be surely and effectively peeled off, and the substrate or the like can be reused to form a resist pattern again.

That is, the present invention provides a method for forming a resist pattern on a film or a substrate to which a resist layer is applied, wherein the resist layer is formed on an underlayer of an inorganic film or an organic film; When the resist pattern is formed through a silylation process, and the obtained pattern is determined
On the processed film having the Ox layer, the silylation layer and the resist layer or on each of the inorganic film base layers or the organic film base layers on the substrate, and on the processed film or the substrate subjected to the regeneration treatment, again, A method of forming a fine pattern is provided, wherein the resist pattern is formed based on the method.

Thus, according to the present invention, referring to FIGS. 2A to 2G and FIGS. 3A to 3F, the inorganic film 802 or the inorganic film 802 shown in FIG. An organic film 802 or the like shown in FIG. 3A is an inorganic film or an organic film as a base layer in the present invention. To form a resist layer on this underlayer, in the former, a film is formed directly on this underlayer, but in the latter, a silylated layer (see layer 802a in FIG. 3 (b)), which is entirely silylated, is used. A resist layer is formed on the organic film base layer. As a result, FIG.
As shown in FIG. 3 (c) and FIG. 3 (d), a fine resist pattern is formed on the resist layer through a silylation process, and even if these patterns are determined to be defective, the substrate is damaged. Instead, the entire underlayer can be removed by a conventionally known method, and a reusable substrate can be regenerated as shown in FIGS. 2 (f) and 3 (f).

[0017]

As described above, according to the present invention, as described above, a fine semiconductor circuit pattern can be formed on a resist layer through a silylation process on a substrate or the like. In this case, the substrate or the like is surely reproduced, and a resist pattern is formed on the reproduced substrate again in the same manner.

Hereinafter, an embodiment of a method for forming a fine resist pattern of a semiconductor circuit on a substrate according to the present invention will be described with reference to FIGS.

In the present invention, for forming a resist layer on a substrate by, for example, a spin coating method, conventionally known positive and negative type resist materials can be appropriately used. From the viewpoint of forming a pattern, a positive type, for example, a polyphenol-based resist is preferably used.

In the present invention, as the inorganic film of the underlayer, conventionally known materials such as a silica oxide film, a polysilicon film, a tungsten-silicon film, a silicon nitride film, a phosphorus silicate glass film (PSG) and Boron phosphorus silicate glass film and the like,
In the present invention, these may be used alone or in combination of two or more, depending on the purpose of use. Ease of film formation such as sputtering, or peeling by etching, etc.
From the viewpoint of ease of removal, more preferably, a silica oxide film, a silicon nitride film, a phosphor silica glass film (PSG)
Etc. are preferably used.

In the present invention, the thickness of the inorganic film as a base layer is preferably 20 nm or more and 100 nm or less. If this film thickness is less than 20 nm, for example, as shown in FIG. 2C, when removing the residue 1002 made of SiOx on the pattern surface, it penetrates the underlayer 802 of the inorganic film to form the film to be processed. Alternatively, the substrate may be damaged. Further, the residue easily adheres to the substrate or the like, and is difficult to remove by lift-off. On the other hand, if it exceeds 100 nm, it causes a conversion difference when etching the film to be processed or the substrate. In addition, it takes time to dissolve and remove the underlayer 802, which undesirably increases the processing cost.

Therefore, according to the present invention, by providing the underlayer of the inorganic film as described above, when removing the residue as described above, the entire underlayer can be removed, which has been apt to occur conventionally. The substrate can be regenerated without damaging the substrate.

Thus, the substrate is coated with the inorganic film 802 as a base layer, and a resist as shown in FIG. 2B is applied thereon to form a resist layer 901. A fine pattern is formed. As a result, as described above, the resist layer is not formed directly on the substrate as in the related art, but the removal at the time of pattern failure is performed on the underlying layer, so that the underlying substrate is damaged. The fact that the risk of occurrence is significantly reduced also corresponds to the fact of the embodiment described later.

Further, in the present invention, as described above, instead of the above-mentioned inorganic film, an organic film 802 can be appropriately formed on the substrate 801 as a base layer as shown in FIG. Therefore, in the present invention, for example, it is preferable to apply a novolak-based resist as an organic film 802 on a polysilicon film formed first on a substrate. In addition, if necessary,
Baking is preferably performed at a temperature of about 200 ° C.

Next, as shown in FIG. 3B, the entire surface of the underlayer of the organic film 802 is exposed to a silylating agent vapor to silylate the entire surface of the underlayer. 802a. That is, a substitution reaction between the phenolic hydroxyl group in the novolak resist and the silylating agent is performed on the entire surface of the organic film surface layer of the novolak resist, and the silylated layer 80 is formed.
2a. Therefore, in the present invention, the organic film is not particularly limited, but preferably has an —OH group from the viewpoint of silylation.

On the organic film of the underlayer thus formed, as in the above-mentioned underlayer of the inorganic film, as shown in FIG.
A resist is applied as shown in FIG.
01 is formed, and a fine pattern is similarly formed on the resist layer.

In the present invention, the thickness of such a silylated layer is preferably not less than 10 nm and not more than 30 nm. When the thickness of the silylated layer is 10
If it is less than nm, it will penetrate by sputtering or the like, and therefore, it is preferable to have a thickness around 30 nm as an upper limit.

Therefore, as a silylating agent used in the present invention, an aminosilane or an aminosiloxane-based silicon compound is generally used. These may be of oligomeric nature. Above all, when forming a positive structure, for example, aminosiloxane does not react with a carboxylic acid generated by exposure during treatment of a resist exposed through a mask, and reacts with its anhydride in an unexposed area. react. When forming a positive structure,
The non-polar, aprotic silylation solution is preferably used as a solution type of a silylation agent with an organic solvent. Examples of this type of solvent include anisole, dibutyl ether and / or diethylene glycol dimethyl ether. When a negative-type structure is formed, the organic protic silylation solution is preferably used as a solution type of a silylating agent using an aqueous organic solvent. Examples of this type of solvent include water, ethanol and / or isopropanol.

In order to form a predetermined fine pattern on the resist layer formed as described above, a method usually used is used [for example, steps (b), (c) and (d) shown in FIG. As shown in FIG. 2C or FIG. 3D, after exposure through a predetermined pattern mask, the silylated layer 1004-thin film SiOx
Each of the fine resist patterns 1001 shown in FIG. 2C or the fine resist patterns 1101 shown in FIG.

Further, when a fine pattern is formed in this way, a predetermined quality value is not satisfied by a defect inspection such as a line width measurement of a pattern and a superposition accuracy measurement. For example, when it is confirmed that a residue 1002 shown in FIG. 2C or a resist pattern which falls down and adheres to the substrate surface as shown in FIG. In, surely,
Moreover, in order to effectively remove the resist and regenerate the substrate, as shown in FIG. 2 (f) and FIG. 3 (f), the inorganic or organic film underlying layer on the substrate is removed to regenerate the substrate. A predetermined fine pattern is formed in the same manner by using the same manufacturing process again.

That is, at the time when the resist pattern 1001 shown in FIG. 2C is formed, for example, when a residue 1002 is formed on the inorganic film base layer as a pattern formation defect, first, a fluorine-based gas is contained. SiOx layer 10 by plasma etching or diluted hydrofluoric acid
05 is removed (see FIG. 2D). Next, the bulk resist pattern 1001 is removed with a conventional resist stripper (see FIG. 2E). Alternatively, the resist of the above-described resist pattern 1001 and the SiOx layer 1005 and the silylated layer 1004 thereon can be stripped at a time with an amine stripper. Next, the inorganic film 802 of the underlayer according to the present invention provided on the substrate is dissolved,
Remove. At this time, the residue 1002 is removed by lift-off, and the substrate is regenerated.

Further, if necessary, as shown in FIG. 2 (g), as a separate implementation of the above-mentioned reproducing method, when an undercoating film which is an inorganic film is provided on the substrate in advance. In particular, the residue can be lifted off by dissolving not the inorganic film base layer of the present invention as described above but the surface layer of the film to be processed.

When the underlayer is an organic film, as shown in FIG. 3B, the underlayer organic film 80 is etched by oxygen plasma in dry development.
2 (see FIG. 3C), as described above, the entire surface of the exposed organic film 802 other than the resist pattern is silylated, and the surface layer is
x, so that this etching
No damage to the substrate occurs, since progress is prevented in the layers.

Next, as shown in FIG. 3D, even if the SiOx layer 1104 and the silylation layer 1101 on the entire surface are removed by plasma etching containing a fluorine-based gas, dilute hydrofluoric acid, etc. Fig. 3 (e)
Since the organic film 802 is provided as shown in FIG. Therefore, by using the conventional resist stripping solution, as shown in FIG.
It is clearly understood that the wafer can be reliably regenerated even in the silylation process, unlike the conventional method.

In the present invention, the silylated layer and SiOx, including the residue, can be completely removed because the same situation as the above (1) is created by laying an organic film below. In the present invention, at the time of dry development or SiOx /
Even if the SiOx residue adheres to the organic film when the silylated layer is removed, the residue is removed together with the organic film later, so that the residue can be finally eliminated. In the present invention, SiOx /
Since a large amount of a fluorine-based treating agent can be used when removing the silylated layer, most of the SiOx / silylated layer can be removed at that time. This is because even if a large amount of the fluorine-based treating agent is used, the underlying substrate is covered with the organic film inert to the fluorine-based treating agent, so that the underlying substrate is not damaged.

[0036] In carrying out such a reproduction process effectively, it is known from the prior art, for example, against oxidation film such as SiO _{2, CF 4, CF 4 -H 2} , CHF 3, C 4
Plasma etch comprising a fluorine-based gas such as F ₈ (dry etching) or hydrofluoric acid, dilute hydrofluoric acid or HF-NH
Wet etching using ₃ F, etc., for the nitride film such as _{Si 3 N 4, CF 4,} CF 4 -H 2 -N 2 wet etching by dry etching or hot phosphoric acid by, CF for polysilicon _4, CCl ₄ dry etching or hydrofluoric acid by - can name a process performed by combining the washing treatment with hydrogen peroxide solution, or the like - nitrate -I ₂ wet etch and sulfuric acid, such as containing glacial acetic acid.
It is also effective to combine wet etching with an amine-based stripping solution, dilute hydrofluoric acid, and cleaning treatment with a sulfuric acid-hydrogen peroxide solution.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to FIGS. 4 to 7, but the present invention is not limited to these embodiments.

(Embodiment 1) As shown in FIG. 4A, a device isolation 150 (not shown) is formed on a silicon substrate 1501.
After the formation step 2, the gate oxide film 1503 is
m thick, and then a polysilicon film 1 is formed by a CVD method.
504 is formed to a thickness of 150 nm, and a tungsten / silicon film (W-Si film) is
A 50-nm-thick underlayer of a phosphosilicate glass film (PSG film) was formed by a CVD method. Next, as shown in FIG. 4B, a polyvinylphenol-based resist 1601 is coated on this inorganic film base layer by 500 times.
After spin-coating at a thickness of 100
Bake for 2 seconds. Next, as shown in FIG.
A gate pattern having a designed gate length of 130 nm on the mask 1701 was exposed and transferred onto a substrate using an ArF excimer laser as an exposure light source and a reduction rate 縮小 projection exposure apparatus having an exposure wavelength of 193 nm. The exposed portion of the resist is a photo-crosslinked cross-linked portion 1702 [see FIG. 4 (c)].
Becomes Next, as shown in FIG.
At 80 ° C, 80 torr dimethylsilyldi
methylamine (DMSDMA) vapor 1801
By exposing the substrate surface to the inside for 60 seconds, the portion of the gate pattern, which is the portion of the resist surface where photocrosslinking has not occurred, is silylated, and a silylated layer 1802 having a thickness of 50 nm is formed. Next, as shown in FIG. 5E, the resist was subjected to anisotropic etching under the following conditions using a TCP plasma etching apparatus. 1st.step _{Gas: CHF 4 -0 2 / 50sccm-} 15sccm / 5mtTorr TCP Power: 250W, Biased Power: 15W, time: 20sec 2nd.step _{Gas: 0 2 -SO 2 / 80sccm-} 5sccm / 5mtTorr TCP Power: 250W, Biased Power: 40W, Time: 55sec At this time, in the surface of the silylated layer of the resist pattern,
When silicon and oxygen are combined, the SiOx mask 1901 becomes 1
The resist was formed at a thickness of 0 nm, and the resist in the exposed area other than the mask was etched to form a gate pattern.

At this point, the line width of the pattern, the overlay accuracy, and the defect inspection are performed. At this time, if the measured value exceeds the allowable value, the resist is removed and the substrate is regenerated. At this time, a residue 1902 may be generated on the PSG film. Therefore, the SiOx layer is removed using a TCP plasma etching apparatus. The etching conditions were as follows. _{Gas: CHF 4 -0 2 / 20sccm-} 70sccm / 7mtTorr TCP Power: 250W, Biased Power: 15W, Time: 15 sec Next, sulfate - when the spin cleaning for 5 minutes the substrate with hydrogen peroxide solution, the resist was removed. Here, FIG.
As shown in (f), a residue may still remain on the PSG film. Therefore, the PSG film is dissolved and removed by spin cleaning with 1% DHF for 240 seconds, and the residue is removed by lift-off. Now, FIG.
As shown in (g), the entire inorganic film of the underlayer is removed,
Regeneration of the substrate is completed.

Next, in the same process as described above, FIG.
As shown in (h), a resist gate pattern 220 is formed.
Form one. Here, line width measurement, overlay accuracy measurement, and defect inspection of the pattern are performed, and if there is no problem, the process proceeds to the next step.

First, as shown in FIG.
Etching the PSG film using the pattern as a mask. this
CHF for etching_Three / CF_Four Gas is used. Next
Then, as shown in FIG. 5 (j), the W-Si film is
To CF for etching_Four / Cl_Two Use gas.
At this time, the SiOx on the resist and part of the silylation layer
Etched and removed. In addition, the polysilicon film is
Switch. This etching includes HBr / Cl _Two Moth
Using At this time, the silylated layer on the resist layer, or
Part of the resist is etched away. Then
When post-treated with a sulfuric acid-hydrogen peroxide solution, it is shown in FIG.
As shown in FIG.
It is formed. Note that here, the source and drain
The description of the process is omitted. The PSG film on the gate electrode is
It is etched at the same time when etching the interlayer film
There is no need to remove it.

(Embodiment 2) As shown in FIG. 6A, an element isolation 2702 and a gate electrode 2703 are formed on a silicon substrate 2701, and the oxide film 2 is formed by CVD.
After 704 was formed to a thickness of 1 μm and planarized by CMP, an SiN film 2705 was formed to a thickness of 50 nm by a CVD method, a polyvinyl phenol-based resist 2706 was spin-coated to a thickness of 500 nm, and the substrate was baked at 100 ° C. for 60 seconds. In addition,
Here, the description of the source and drain forming steps is omitted. Next, in the same manner as in Example 1, as shown in FIG. 6B, a hole pattern 2801 was formed by using a silylation process. The upper layer of the resist has a silylated layer 2
802 and a SiOx layer 2803 are further formed.
Here, if there is a determination of a resist pattern defect, the resist is peeled off and the substrate is regenerated. First, FIG. 6C shows an amine-based stripping solution heated to 85 ° C., from which the resist, the silylated layer, and SiOx have been removed by spin cleaning. At this time, as shown in FIG.
Ox residue 2901 may be generated. Therefore,
The substrate is immersed in and washed with hot phosphoric acid heated to 180 ° C. for 15 minutes to completely remove the SiN film. At this time, the residue S
The iOx is lifted off and removed, and the substrate is regenerated as shown in FIG.

Next, a 50 nm thick SiN film as an inorganic film as a base layer is formed by the CVD method, and a hole pattern is formed in the same manner as shown in FIG. 6B.
(E). Then, using the resist as a mask, SiN
Then, the oxide film was etched to form holes as shown in FIG. CF ₄ for etching the SiN
/ H ₂ gas, and CHF ₃ /
CF ₄ gas was used. At this time, the SiOx and the silylated layer are simultaneously etched. Next, as shown in FIG. 6 (g), the resist is etched using a gas of CHF ₃ / O ₂ (1: 3), and excess SiN is removed using a gas of CF ₄ / H _2. A fine pattern in which holes are formed in the interlayer film shown in FIG.

(Embodiment 3) As shown in FIG. 7A, an element isolation 3402 and a gate electrode 3403 are formed on a silicon substrate 3401, and an oxide film 340 is formed by a CVD method.
4 was formed to a thickness of 1 μm and flattened by CMP. Then, a polyvinylphenol-based resist 3405 was spin-coated at a thickness of 500 nm, and then baked as in Example 2. Note that a source and drain forming step is performed in the same manner as in the second embodiment. Next, in the same manner as in Example 1, a hole pattern was formed using a silylation process, as shown in FIG.
And a silylated layer, SiO 2 on the resist upper layer.
An x layer is formed. Here, if there is a determination of a resist pattern defect, the resist is peeled off and the substrate is regenerated. First, FIG. 7C shows an amine-based stripping solution heated to 85 ° C., from which the resist, the silylated layer and SiOx have been removed by spin cleaning. At this time, as shown in FIG. 7C, a residue of SiOx may be generated on SiN. Next, spin cleaning is performed with 1% DHF for 120 seconds to dissolve the oxide film by about 50 nm and remove the residue by lift-off. Thus, the substrate can be regenerated as shown in FIG. Next, using this regenerated substrate, a hole pattern was formed in the same manner as in Example 2, and the same etching was performed to form a fine pattern in which holes were formed in the interlayer film shown in FIG. Was.
In addition, in Example 2, CF ₄ / H ₂ gas was used,
Re-patterning was performed in exactly the same manner as in Example 2 except that post-treatment was performed using a sulfuric acid-hydrogen peroxide solution instead of removing excess SiN.

(Embodiment 4) As shown in FIG. 8A, an element isolation 1402, a gate oxide film 1403 having a thickness of 4 nm, and a polysilicon film 1404 having a thickness of 150 nm are formed on a silicon substrate 1401 by CVD. A novolak-based resist 1405 having a thickness of 100 nm was further spin-coated as an organic film base layer, and hard-baked at 200 ° C. for 30 minutes. Next, as shown in FIG. 8B, the organic film underlayer 1405 is subjected to 30 Torr DMSDMA vapor 1801 at a temperature of 100 ° C.
Exposure for 2 seconds to replace the phenolic hydroxyl group on the surface of the novolak resist with a silyl group, the entire surface of the silylated layer 1802
And The thickness of the silylated layer thus formed is about 2
0 nm. Next, a 500 nm-thick polyvinylphenol-based resist 1601 was spin-coated on this underlayer, and baked at 100 ° C. for 60 seconds.
(C). Next, as shown in FIG. 8D, an ArF excimer laser and a gate pattern having a designed gate length of 130 nm on the mask 1701 are used as an exposure light source.
The substrate was exposed and transferred to a substrate using a 1/4 projection exposure apparatus having a reduction ratio of 193 nm. The exposed portion of the resist becomes a photocrosslinked portion 1702 (see FIG. 8D). Next, as shown in FIG.
Then, the substrate surface is exposed to DMSDMA vapor 1801 at 80 Torr for 60 seconds to silylate the gate pattern, which is the portion of the resist surface where photocrosslinking has not occurred, to form a 50 nm thick silylated layer 1802. Next, as shown in FIG. 8F, the resist is anisotropically etched using a TCP plasma etching apparatus under the same conditions as in the first embodiment. At this time, on the surface of the silylated layer of the resist pattern, silicon and oxygen are bonded to form SiO2.
An x mask 1901 is formed to a thickness of 10 nm, and a resist in an exposed portion other than the mask is etched to form a gate pattern. When the etching reaches the lower resist, the surface of the silylated layer on the lower resist becomes SiOx1902, and the etching stops.

At this point, the line width of the pattern is measured, the overlay accuracy is measured, and the defect is inspected. At this time, if the measured value exceeds the allowable value, the resist is removed and the substrate is regenerated. Therefore, the SiOx layer is removed under the following conditions using a TCP plasma etching apparatus. The etching conditions are as follows. _{Gas: CHF 4 -0 2 / 50sccm-} 15sccm / 5mtTorr TCP Power: 250W, Biased Power: 15W, Time: 30 sec SiOx layer and silylated layer removes both patterns upper and lower resist. Further, at this time, there is no problem even if the straightness 2001 occurs on the surface of the lower resist. Next, when the substrate is spin-washed with a sulfuric acid-hydrogen peroxide solution for 5 minutes, as shown in FIG. 9H, the resist is completely removed, and the regeneration of the substrate is completed. The residue 2001 is lifted off and removed by the spin cleaning. Then
As shown in FIG. 9I, a resist gate pattern is formed by the same process as described above. At this time, the line width of the pattern is measured, the overlay accuracy is measured, and the defect is inspected. If there is no problem, the operation proceeds to the next operation. First, as shown in FIG. 9 (j), using a TCP plasma etching apparatus,
The iOx layer is completely removed. The etching conditions are as follows. _{Gas: CHF 4 -0 2 / 50sccm-} 15sccm / 5mtTorr TCP Power: 250W, Biased Power: 15W, Time: 10 sec SiOx layer removes both patterns upper and lower resist layer. Next, as shown in FIG.
The lower resist is anisotropically etched using a P plasma etching apparatus. The etching conditions are as follows. _{Gas: CHF 4 -0 2 -SO 2 /} 20sccm-80sccm-5sccm / 5mtT
orr TCP Power: 250 W, Biased Power: 40 W, Time: 20 sec At this time, the resist is etched by about 100 nm in the upper layer of the pattern. Furthermore, by using the ECR plasma etching apparatus, as shown in FIG. _{9 (l), Cl 2 -O} 2 plasma using the resist pattern as a first stage in the mask, using HBr-O ₂ plasma as the second stage poly Etch silicon and gate oxide films. At this time, the substrate temperature is 2
0 ° C, pressure O. 5pa, C1 ₂ flow 15 sccm, O ₂ flow rate 5 sccm, HBr flow 95 sccm, Biased RF power is 25W. Next, when post-treatment is performed with a sulfuric acid-hydrogen peroxide solution, a polysilicon gate pattern 2601 having a gate length of 130 nm is formed as shown in FIG.
Note that the description of the source and drain forming steps is omitted here.

(Embodiment 5) In Embodiment 4, in the regeneration step,
Fluorine-based plasma was used for removing the SiOx layer and the silylated layer, and a sulfuric acid-hydrogen peroxide solution was used for removing the bulk resist. Here, instead of this, the SiOx, the silylated layer and the bulk resist are removed at once by spin cleaning with an amine-based stripping solution heated to 85 ° C. for 10 minutes. In this case, SiOx partially dissolves, but there is also one that is removed by a lift-off effect.

(Embodiment 6) In this embodiment, a hard-baked novolak-based resist as a lower layer is formed to a thickness of 0.35 μm.
0.07 μm of polyvinylphenol-based resist in upper layer
The silylation process is performed after thick coating. Thereby, regardless of the size of the pattern, the upper layer resist can be uniformly silylated to a thickness of 0.07 μm.
The line width control of the pattern can be improved. Here, as shown in the present invention, the lower layer novolak-based resist is entirely silylated, and then the upper layer polyvinylphenol-based resist is applied. By doing so, not only the line width control of the pattern is improved, but also the reproduction of the substrate becomes possible.

[0049]

According to the present invention, in order to form a fine resist pattern for a semiconductor device having a highly integrated circuit on a substrate through a silylation process, the resist layer is formed of an inorganic film or an organic film. By forming a film on the underlayer, even if the obtained resist pattern is determined to be unacceptable in the quality inspection step, the inorganic pattern on the substrate having the SiOx layer, the silylated layer, the resist layer, and residues related thereto, etc. It is possible to remove each film base layer or each organic film base layer.

In the substrate thus removed, even if the underlying layer applied on the substrate is formed by using various etching, stripping / dissolving solutions known in the art as the removing process, the underlying layer can be used as a protective layer. As a result, the substrate is not damaged unlike the related art. Thus, the obtained substrate is surely reproduced, and is recovered and reused as a substrate on which a fine pattern can be formed again in the same manner.

As a result, the reproduction can be performed reliably and effectively, so that the number of substrates to be discarded is reduced. In particular, the yield of integrated semiconductor circuit elements with advanced fine integration is improved, and the manufacturing cost is reduced. It is possible to provide a method for forming a fine pattern which can be reduced.

[Brief description of the drawings]

FIG. 1 shows a resist on a substrate through a silylation process.
It is a conceptual process drawing which produces a defective pattern in the manufacturing process which forms a pattern.

FIG. 2 is a conceptual diagram illustrating a manufacturing process of forming a resist pattern on a substrate through a silylation process according to the present invention and a conceptual process of regenerating the substrate.

FIG. 3 is a conceptual diagram showing a manufacturing process for forming a resist pattern on a substrate through a silylation process according to the present invention and a conceptual process for regenerating the substrate.

FIG. 4 is a conceptual process diagram showing formation of a fine resist pattern, substrate regeneration and re-pattern formation according to an embodiment of the present invention.

FIG. 5 is a conceptual process diagram (continued) shown in FIG.

FIG. 6 is a conceptual process diagram showing formation of a fine resist pattern, substrate regeneration and re-patterning according to another embodiment of the present invention.

FIG. 7 is a conceptual process diagram showing the formation of a fine resist pattern, the regeneration of a substrate, and the re-patterning of another embodiment of the present invention.

FIG. 8 is a conceptual process diagram showing formation of a fine resist pattern, substrate regeneration and re-patterning according to another embodiment of the present invention.

FIG. 9 is a conceptual process diagram (continued) shown in FIG. 8;

[Explanation of symbols]

801 -------- Substrate, 802 -------- Underlayer (inorganic film or organic film), 901, 1001, 1101, 1601, 2201, 2706, 3405 ----
---- Resist layer (resist pattern), 1002, 1902, 20
01, 2901, 3601 -------- Residue, 802a, 1004, 1104, 1802, 19
03, 2802, 3502 -------- Silylation layer, 1005, 1105, 1901, 2
803, 3503 -------- SiOx layer, 1401, 1501, 2701, 3401
-------- Silicon substrate, 1402, 1502, 2702, 3402 --------
Isolator, 1403, 1503 -------- Gate oxide film, 1404, 1
504 -------- Polysilicon film, 1405 -------- Organic film underlayer, 1505 -------- W-Si film, 1506 -------- P
SG film (underlayer), 1701 -------- Mask, 1702 -----
--- Cross section of resist, 1801 -------- Vapor silylation agent, 2
703, 3403 -------- Gate electrode, 2704 -------- Oxide film, 2705 -------- SiN film, 2801, 3501 -------- Hole ·pattern.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/30 574

Claims (11)

[Claims] When forming a resist pattern on a resist layer provided on a film to be processed or a substrate, the resist layer is formed on an underlayer of an inorganic film or an organic film, and the resist A method for forming a fine pattern, wherein the pattern is performed through a silylation process. 2. The method according to claim 1, wherein the resist layer is a phenolic resist. 3. The inorganic film of the underlayer is at least one selected from the group consisting of a silica oxide film, a polysilicon film, a tungsten-silicon film, a silicon nitride film, and a phosphosilicate glass film (PSG). The method for forming a fine pattern according to claim 1. 4. The method according to claim 1, wherein the organic film of the underlayer is a novolak-based resist formed on a polysilicon film and is baked. 5. The fine particle according to claim 4, wherein the entire surface layer of the organic film of the novolak resist is silylated by substituting a phenolic hydroxyl group of the novolak resist with a silylating agent. The method of forming the pattern. 6. The method according to claim 5, wherein the thickness of the silylated layer formed on the surface layer of the organic film is not less than 10 nm and not more than 30 nm. 7. The method according to claim 1, wherein, in order to form a predetermined fine pattern on the resist layer, a silylated layer is formed in the pattern portion after exposure through a mask of the pattern. Method of forming a fine pattern. 8. A method for forming a resist pattern on a film to be processed or a substrate provided with a resist layer, wherein the resist layer is formed on a base layer of an inorganic film, and the resist pattern is silylated. When the obtained pattern formed through the process is determined to be rejected in the quality inspection step, the inorganic film base layer on the film to be processed having the SiOx layer, the silylated layer and the resist layer or on the substrate And forming the resist pattern on the processed film or substrate subjected to the regeneration process again based on the method. 9. A method for forming a resist pattern on a film to be processed or a substrate on which a resist layer has been applied, wherein the resist layer is formed on an underlayer of an organic film, and the resist pattern is silyl. When the obtained pattern is determined to be unacceptable in the quality inspection step, and the obtained pattern is determined to be unacceptable in the quality control process, the processed film having the SiOx layer, the silylation layer and the resist layer or the organic film base layer on the substrate And forming the resist pattern on the processed film or substrate subjected to the regeneration process again based on the method. 10. The method according to claim 8, wherein the regeneration processing is performed by a combination of plasma etching containing a fluorine-based gas, wet etching with diluted hydrofluoric acid, and cleaning with a sulfuric acid-hydrogen peroxide solution. 3. The method for forming a fine pattern according to 1. 11. The fine particle according to claim 8, wherein the regeneration treatment is performed by combining wet etching with an amine-based stripping solution, dilute hydrofluoric acid, and cleaning treatment with a sulfuric acid-hydrogen peroxide solution. The method of forming the pattern.