JP2000341100A - Poly phase clock signal generating circuit, phase shift clock signal generating circuit and multiple clock signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit that generates a poly phase clock signal where jitter and a phase error due to a noise are small. SOLUTION: The poly phase clock signal generating circuit is provided with a delay circuit A/D converter that has a plurality of delay elements, receives a reference clock by a delay element at a front stage and varies a delay time of each of a plurality of the delay elements with a control signal, a phase comparator 1 that compares a phase of the reference clock signal with a phase of an output signal of the delay element at the final stage of the delay circuit 3 and provides an output of a phase error signal, and a delay control circuit 2 that generates a control signal on the basis of the phase error signal, and outputs of a plurality of the delay elements of the delay circuit 3a are outputted as poly phase clock signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-phase clock signal generating circuit for generating a multi-phase clock phase-synchronized with a reference clock signal based on the reference clock signal. And a multiplied clock signal generating circuit for generating a multiplied clock signal in phase with the reference clock based on the reference clock signal.

[0002]

2. Description of the Related Art Conventional multiphase clock signal generation circuits, phase shift clock signal generation circuits, and multiplied clock signal generation circuits have included an oscillation circuit such as a VCO (Voltage Controlled Oscillator).

[0003]

However, the VCO
Oscillation circuits such as these have had problems such as an increase in jitter due to the influence of power supply noise and substrate noise, a variation in phase difference, and a problem of not operating at a low voltage. Therefore, the multi-phase clock signal generated by the conventional multi-phase clock signal generation circuit,
A phase-shifted clock signal generated by a conventional phase-shifted clock signal generation circuit and a multiplied clock signal generated by a conventional multiplied clock signal generation circuit have jitter and phase errors due to noise, and when a low voltage is applied. Could not be obtained.

An object of the present invention is to provide a multi-phase clock signal generation circuit, a phase shift clock signal generation circuit, and a multiplied clock signal generation circuit which are not easily affected by noise and operate even at a low voltage.

[0005]

A multi-phase clock signal generating circuit according to the present invention has a plurality of delay elements, a reference clock is input by a delay element at the forefront stage, and each of the plurality of delay elements has a delay time. A delay circuit that changes according to the control signal,
A phase comparator that compares a phase of the reference clock signal with a phase of an output signal of a delay element at a final stage of the delay circuit and outputs a phase error signal; and generates the control signal based on the phase error signal. A delay control circuit that outputs the outputs of the plurality of delay elements of the delay circuit as a multi-phase clock signal.

A phase-shifted clock signal generating circuit according to the present invention comprises the above-described multi-phase clock signal generating circuit and a phase-shifting clock signal for selecting one of the multi-phase clock signals according to a selection signal and outputting the selected signal as a phase-shifted clock signal. And a selector.

A multiplied clock signal generating circuit according to the present invention includes the above-described multi-phase clock signal generating circuit and a multiplying circuit that generates a multiplied clock signal based on the multi-phase clock signal.

A multiplied clock signal generating circuit according to the present invention is characterized in that in the above multiplied clock signal generating circuit, the multiplying circuit includes a product-sum circuit.

In the method for generating a multi-phase clock signal according to the present invention, a reference clock is input to a delay circuit having a plurality of delay elements, and a phase of the reference clock signal and an output signal of a delay element at the last stage of the delay circuit. Generating a phase error signal by comparing the phase of the plurality of delay elements with each other, generating a control signal based on the phase error signal, and controlling a delay time of the plurality of delay elements of the delay circuit by the control signal. And outputting the outputs of the plurality of delay elements of the delay circuit as a multiphase clock signal.

A method for generating a phase-shifted clock signal according to the present invention comprises the steps of:
Selecting one of the multi-phase clock signals according to a selection signal and outputting the selected signal as a phase-shifted clock signal.

A method of generating a multiplied clock signal according to the present invention includes the steps of generating a multi-phase clock signal described above;
Generating a multiplied clock signal based on the multi-phase clock signal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] As shown in FIG. 1, a phase shift clock signal generating circuit according to a first embodiment of the present invention includes a phase comparator 1, a delay control circuit 2, a delay circuit 3, and a phase selector. It comprises a circuit 4. Among them, the phase comparator 1, the delay control circuit 2, and the delay circuit 3 constitute a multi-phase clock signal generation circuit.

The phase comparator 1 has a function of inputting the output 12 of the delay circuit 3 and the reference clock 11, detecting the phase difference between the output 12 of the delay circuit 3 and the reference clock 11, and outputting a phase error signal. . The delay control circuit 2 outputs the phase error signal 1
3 to generate a delay control signal 14. The delay control circuit 2 is composed of, for example, a charge pump. Each of the delay control signals 14 has the same control voltage or control current.

The delay circuit 3 has a plurality of delay elements, and the delay times of the respective delay elements vary according to the delay control signal 14, but are equal to each other. The reference clock signal 11 is the delay circuit 1
3, the delayed reference clock signal is output as a multiphase clock signal 15 from each tap extracted from each delay element.

With the above configuration, the delay circuit output signal 12
Locks in phase to the reference clock signal 11, and each of the multi-phase clock signals 15
The signal is shifted by only the phase. Here, N is the number of delay elements of the delay circuit 3, and 1 <n ≦ N.

The phase selector circuit 4 selects one of the multi-phase output signals 15 of the delay circuit 3 in accordance with the designation by the selection signal 16, and generates a phase-shifted clock signal 17 having a desired phase from the reference clock signal 11. Output.

Next, the operation of the embodiment of the present invention will be described with reference to the operation flowchart of FIG.

(Step 1) The phase comparator 1 detects a phase error between the output signal 12 of the delay circuit 3 and the reference clock signal 11.

(Step 2) Next, the delay circuit 3 outputs a delay control signal 14 for controlling the delay time of the delay circuit 3 so as to reduce the phase error based on the phase error detection result.

(Step 3) Next, the delay circuit 3 adjusts the delay time of each delay element constituting the delay circuit 3 according to the delay control signal 14. However, the delay time of each delay element is the same as each other.

(Step 4) Next, the delay circuit 3 outputs a multi-phase clock signal from each tap.

(Step 5) Next, the phase selector 4
The multi-phase selection signal indicated by the selection signal 16 is selected, and a phase-shifted clock signal 17 having a phase difference indicated by the selection signal 16 with respect to the reference clock signal 11 is output.

[Second Embodiment] A second embodiment of the present invention is a multiplied clock signal generation circuit including the multiphase clock signal generation circuit of the first embodiment.

The multiplied clock signal generating circuit according to the present embodiment includes a multiplying circuit 5 in addition to the same phase comparator 11, delay control circuit 2, and delay circuit 3 as in the first embodiment. The description of the phase comparator 11, the delay control circuit 2, and the delay circuit 3 is omitted.

The multiplying circuit 5 has a multiplied clock signal 18 obtained by multiplying the reference clock signal 11 from the multiphase clock signal 15.
Generate

FIG. 4 shows an embodiment of the multiplying circuit 5, in which the phase is 1
The multiplied clock signal of 4 times is generated by the multi-phase output signal shifted by / 8. The multiplying circuit 5 is a product-sum circuit including four 2-input AND circuits 41, 42, 43, and 44 and an OR circuit 45 that inputs the outputs of these circuits. One input of each AND circuit has a phase of m · 2π / 8 (m
= 0, 2, 4, 6), and the other input has a phase of (m + 1) · 2π / 8 (m = 0, 2,
A signal obtained by inverting the signal shifted by (4, 6) is input.

FIG. 5 is a timing chart of the frequency multiplier shown in FIG.

[0028]

As described above, according to the present invention, a multi-phase clock signal can be generated without oscillating the signal, so that the jitter and phase error of the multi-phase clock signal due to noise and the fluctuation thereof are reduced. A polyphase clock signal can be generated even with a voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a phase-shifted clock signal generation circuit including a multi-phase clock signal generation circuit according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart illustrating an operation of the phase-shifted clock signal generation circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a multiplied clock signal generation circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an embodiment of a multiplication circuit 5 when a multiplication number is 4.

FIG. 5 is a timing chart for explaining the operation of the frequency multiplier shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Delay control circuit 3 Delay circuit 4 Phase selector 5 Multiplier circuit

Claims (7)

[Claims] A delay circuit having a plurality of delay elements, wherein a reference clock is input by a delay element at a first stage, and a delay time of each of the plurality of delay elements is changed by a control signal; A phase comparator that compares a phase with a phase of an output signal of a delay element at a final stage of the delay circuit and outputs a phase error signal; and a delay control circuit that generates the control signal based on the phase error signal. A multi-phase clock signal generation circuit, comprising: outputting the outputs of a plurality of delay elements of the delay circuit as a multi-phase clock signal. 2. The multi-phase clock signal generation circuit according to claim 1, further comprising: a phase-shift selector that selects one of the multi-phase clock signals according to a selection signal and outputs the selected signal as a phase-shift clock signal. A phase-shifted clock signal generating circuit. 3. A multiplied clock signal generation circuit, comprising: the multiphase clock signal generation circuit according to claim 1; and a multiplication circuit that generates a multiplied clock signal based on the multiphase clock signal. 4. The multiplied clock signal generating circuit according to claim 3, wherein said multiplying circuit includes a product-sum circuit. 5. A step of inputting a reference clock to a delay circuit having a plurality of delay elements, and comparing a phase of the reference clock signal with a phase of an output signal of a delay element at the last stage of the delay circuit to determine a phase error. Generating a signal; generating a control signal based on the phase error signal; controlling a delay time of the plurality of delay elements of the delay circuit by the control signal; Outputting the output of the delay element as a multi-phase clock signal. 6. The method according to claim 5, further comprising: selecting one of the multi-phase clock signals according to a selection signal and outputting the selected signal as a phase-shifted clock signal. A method for generating a phase-shifted clock signal. 7. A multiplied clock signal generation method, comprising: all steps of the multiphase clock signal generation method according to claim 5, and a step of generating a multiplied clock signal based on the multiphase clock signal. .