JP2000340622A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be analyzed for failures by applying the laser potential probing method, even when the area of a diffusion layer is narrowed to 0.5 μm or smaller or a metal silicide layer covering the diffusion layer hinders potential monitoring. SOLUTION: In a semiconductor device, a plurality of transistors, each having a gate electrode, source regions 4 and 6, and drain regions 5 and 7 are formed via insulating and separating regions and metallic wiring is formed in the upper layers of the transistors. At measuring of the potentials at prescribed regions of the transistors by measuring the intensity of the reflected light of laser light projected upon the regions from the rear surfaces of the substrates of the transistors, rectangular potential monitoring regions 11 and 12 which can receive the laser light and have, for example, 0.5 μm by 0.5 μm regions or larger are partly formed in the source or drain regions and electrically connected to the source areas, drain regions, or gate electrode which become the objects of potential measurement and the potentials at the regions are measured from the intensity of the reflected light of the laser light projected upon the potential monitoring regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a potential monitor region in a semiconductor substrate.

[0002]

2. Description of the Related Art As a method of failure analysis of a semiconductor device,
An electron beam tester method of detecting an abnormal signal path by probing a metal wiring with an electron beam and monitoring its potential is effective. However, with the electron beam tester method, with the increase in the scale of semiconductor devices,
As the number of multilayer wirings increases, it becomes difficult to monitor the potential of the lower wirings buried in the upper wirings.

As a method of analyzing a failure of a semiconductor device having a multilayer wiring, a laser potential probing method utilizing the Franz-Keldesch effect by infrared light transmitted through a semiconductor substrate is disclosed in Japanese Patent Application Laid-Open No. H10-111347. It is described in. According to this method, it is possible to monitor the potential of an arbitrary diffusion layer from the back surface of the silicon substrate without being hindered by wiring.

[0004]

However, as the performance of the semiconductor device becomes higher and the transistor becomes finer, the size of each diffusion layer region becomes smaller and the distance between adjacent diffusion layer regions becomes smaller. The laser potential probing method using infrared light having a long wavelength causes the following problems due to the shortening.

A first problem is that, in a semiconductor device having a miniaturized transistor, sufficient potential monitor sensitivity cannot be obtained, and the distance between the centers of two adjacent diffusion regions is reduced by the laser beam. When the diameter is reduced to about half, the potential of the two diffusion layers cannot be monitored separately.

The reason is that the size of the diffusion region to be monitored becomes smaller than the beam diameter of the laser to be probed, and the amount of light effectively used as a potential monitor is reduced. This is because, if a pixel enters an adjacent diffusion region other than the diffusion region to be monitored, the potential of the adjacent diffusion region becomes noise, and the potential monitoring sensitivity is further reduced.

That is, assuming that the wavelength of light is λ and the numerical aperture of the lens for condensing the light is NA, the diffraction effect of light causes
The laser beam diameter cannot be reduced to less than about 0.8 × λ ÷ NA. For example, in the case of a silicon substrate, the wavelength of light that can be transmitted through the substrate, which can be applied to the laser potential probing method, is 1.12 μm or more. It is difficult to narrow the beam. Therefore, when the diffusion region is formed with a width of 1 μm or less, the amount of light effective for the potential monitor is reduced.

In the laser potential probing method utilizing the Franz-Keldesch effect, since a change in the amount of light on the order of ppm is measured, a decrease in the amount of light is a serious problem, and it is difficult to monitor a diffusion layer having a width of 0.5 μm or less. Becomes Further, when the diffusion region becomes 0.5 μm or less, the distance between the centers of the adjacent diffusion regions comes close to 1 μm or less, and it is further difficult to completely separate the adjacent diffusion regions and perform the potential monitoring. It will be difficult.

The second problem is that even if the plane size of the diffusion layer is large enough to prevent the potential monitor from being hindered, the semiconductor is constituted by a transistor whose surface is covered with metal silicide. In the device, it is sometimes difficult to perform a failure analysis to which the laser potential probing method is applied.

The reason is that the interface morphology is degraded due to the silicide reaction between silicon as the diffusion layer and the metal as the electrode, and the laser light is irregularly reflected and the intensity of the detected reflected light is reduced. It is to prevent.

That is, the laser light incident from the back surface of the semiconductor substrate is intensity-modulated at the pn junction formed at the bottom of the diffusion layer by the Franz-Keldysh effect, reflected at the metal silicide interface on the surface of the diffusion layer, and intensity-modulated again. While passing through the pn junction, and comes out from the back surface of the substrate. When monitoring the potential of the diffusion layer by measuring the intensity of the reflected light, the irregular reflection at the metal silicide interface
A large noise can be caused by a change in the amount of light on the order of ppm. Therefore, when the diffusion layer is covered with the metal silicide, a decrease in sensitivity due to miniaturization is promoted, and it becomes difficult to monitor the potential.

The present invention has been made in view of the above problems, and a main object of the present invention is to provide a diffusion layer having a region of 0.5 μm.
To provide a semiconductor device capable of performing a failure analysis by applying a laser potential probing method even when the size is reduced to m or less or a metal silicide layer covering a diffusion layer hinders potential monitoring. It is in.

[0013]

According to a first aspect of the present invention, there is provided a transistor having a source region and a drain region separated by a gate electrode on one surface of a semiconductor substrate. A plurality of metal wirings are formed via an insulating isolation region and connected to each of the source region and the drain region on an upper layer of the transistor, and reflected light of laser light emitted from the other surface of the semiconductor substrate In the semiconductor device in which the potential of a predetermined region of the transistor is measured by measuring intensity, a potential monitor region having a predetermined area in which a part thereof can receive the laser light is provided in the source region or the drain region. The source region, the drain region, or the gate electrode which is formed and is a potential measurement target other than the potential monitor region is the potential monitor. It is connected to region and electrically, in which the potential of the subject to area of potential monitoring the from the reflected light intensity of the irradiated laser beam in the region potential measurement is measured.

According to a second aspect of the present invention, in a second aspect, a plurality of transistors having a source region and a drain region separated by a gate electrode are formed on one side surface of a semiconductor substrate via an insulating separation region. A metal wiring connected to each of the source region and the drain region is provided, and by measuring the reflected light intensity of the laser light emitted from the other surface of the semiconductor substrate,
In a semiconductor device in which the potential of a predetermined region of the transistor is measured, a plurality of source regions and drain regions adjacent to each other via the gate electrode or the insulating separation region are interconnected by the metal wiring, and the laser light is emitted. A potential monitor region having a predetermined area capable of receiving light and having the same potential is formed, and the transistor outside the potential monitor region, wherein a source region, a drain region, or a gate electrode to be measured for potential is electrically connected to the potential monitor region. The potential of the region to be subjected to the potential measurement is measured from the reflected light intensity of the laser light applied to the potential monitoring region.

According to a third aspect of the present invention, in a third aspect, a plurality of transistors each having a source region and a drain region separated by a gate electrode are formed on one surface of a semiconductor substrate via an insulating separation region. A metal wiring connected to each of the source region and the drain region is provided in an upper layer, and by measuring a reflected light intensity of a laser beam irradiated from the other surface of the semiconductor substrate, a predetermined amount of the transistor is measured. In a semiconductor device in which a potential of a region is measured, a potential monitor region having a diffusion region of a predetermined area capable of receiving the laser light is formed in a region other than the gate electrode, the source region, or the drain region, In the outside transistor, the source region, the drain region or the gate electrode to be measured for the potential is the Position connected monitor region and electrically, in which the potential of the subject to area of potential monitoring the from the reflected light intensity of the irradiated laser beam in the region potential measurement is measured.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the semiconductor device according to the present invention, a transistor having a gate electrode, a source region (4, 6 in FIG. 1) and a drain region (5, 7 in FIG. 1). Is formed in a plurality of layers via an insulating isolation region, a metal wiring is formed on the upper layer of the transistor, the reflected light intensity of the laser light irradiated from the back surface of the substrate, the predetermined area of the transistor In measuring the potential of the substrate, a potential monitor region (11, 12 in FIG. 1) is formed in the source region or the drain region. A source region, a drain region, or a gate electrode to be subjected to potential measurement is electrically connected to the potential monitor region, and the reflected light intensity of the laser light applied to the potential monitor region We are measuring the potential of a region of interest of the potential measurement.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

Embodiment 1 First, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view for explaining a configuration of a semiconductor device according to a first embodiment of the present invention, and FIG.
3 is a cross-sectional view taken along the line aa ', and FIG. 3 is a cross-sectional view taken along the line bb'. FIGS. 4 and 5 are diagrams for schematically explaining a method of performing a potential monitor measurement using the semiconductor device of the present embodiment.

First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIGS. In the semiconductor device of this embodiment, a p-type well diffusion layer 2 (not shown in FIG. 1) and an n-type well diffusion layer 3 are formed on the surface of a p-type silicon substrate 1 (not shown in FIG. 1). In the n-type well diffusion layer 3, a p-type source region 6, a p-type drain region 7, and an n-type well contact region 9 for supplying a potential to the n-type well diffusion layer 3 are formed. ing. In the p-type well diffusion layer 2, the n-type source region 4, n
A p-type substrate contact region 10 for supplying a potential to the drain region 5 and the p-type well diffusion layer 2 is formed. Further, a gate electrode 8 is formed between each source and drain region via a gate oxide film. Adjacent sources and drains are separated by a gate electrode 8, and adjacent sources are separated by an insulating oxide film region.

Although the source and drain regions 4, 5, 6, and 7 are all formed with a minimum dimension of 0.5 μm or less, the n-type source region 4 and the p-type source region 6 are partially expanded.
For example, an n-type potential monitor region 11 and a p-type potential monitor region 12 each having a size of, for example, 0.5 μm square or more are formed. In the present embodiment, only the source regions arranged on both sides of the n-type well contact region 9 or the p-type well contact region 10 are replaced with the n-type well contact region 9 or the p-type well contact region 10, respectively. Since it is extended so as to surround it, there is no need to change the pitch of the transistors, and the potential monitor area is secured without deteriorating the degree of integration.

The operation of the above-described semiconductor device of this embodiment will be described. A pn junction is formed at the interface between the n-type potential monitor region 11 and the p-type well diffusion layer 2 and at the interface between the p-type potential monitor region 12 and the n-type well diffusion layer 3. Normally, the highest power supply potential is supplied to the n-type well diffusion layer 3 via the n-type well contact region 9 and the lowest power supply potential is supplied to the p-type well diffusion layer 2 via the p-type well contact region 10. , N-type potential monitor area 1
1 or the voltage applied to each pn junction changes according to the potential of the p-type potential monitor region 12.

A change in the voltage causes a change in the absorptivity of light due to the Franz-Keldesch effect, so that the infrared laser beam transmitted through the silicon is applied from the back surface of the p-type silicon substrate 1 to the potential monitor regions 11 and 12. When irradiated,
A change in light intensity occurs at the time of transmission through the pn junction. Therefore, the potential of the potential monitoring regions 11 and 12 can be determined by monitoring the intensity of the infrared light reflected and returned by the silicide electrode 13a covering the potential monitoring regions 11 and 12.

At this time, due to the diffraction effect of light, even if infrared light having the shortest wavelength that can be transmitted through silicon is used, 1 μm
Since it is difficult to focus the beam below, the laser is also irradiated to the diffusion layer outside the measurement target in a normal semiconductor device.
Since the area of 0.5 μm square or more is ensured, it is possible to prevent the laser from being irradiated to the adjacent diffusion layer beyond the insulating oxide film area separating the diffusion layer or the gate electrode.

Therefore, the potential of each potential monitor layer can be detected independently without being affected by the potential of the diffusion layer adjacent to the potential monitor region. If a region of 1 μm square or more is secured as the potential monitor region, it is possible to more effectively irradiate the potential monitor region with laser light, and thus the detection accuracy of the Franz-Keldesch effect is improved. Can be.

Since the morphology of the interface between the diffusion layer and the silicide electrode 13 is deteriorated due to the silicide reaction, irregular reflection easily occurs when the laser beam is reflected, and it becomes difficult to detect the Franz-Keldesch effect. There are cases. Although this interface morphology is improved by suppressing the silicide reaction, a problem arises in that suppressing the silicide reaction increases the contact resistance at the source or the drain of the transistor.

However, in this embodiment, since the source and drain regions of the transistor and the potential monitor region are clearly distinguished, it is possible to selectively suppress the silicide reaction of only the silicide electrode 13a in the potential monitor region.
It is possible that silicide is not formed. Since only the potential is supplied to the potential monitoring region and a steady current does not flow, even if the connection resistance increases only in the potential monitoring region portion by such a configuration, the potential monitoring should be performed without impairing the transistor characteristics. Is possible.

However, the increase in the connection resistance in the potential monitor region increases the resistance load during charging and discharging of the potential monitor region. Further, since the potential monitor region of the present embodiment has a relatively large area compared to the diffusion region of the miniaturized transistor, the potential monitor region has a large capacity load. Therefore, as shown in FIG.
When connected to the potential monitoring area, a heavy load is generated on each circuit, and the circuit operation speed may be limited.

In such a case, as shown in FIG. 5, by connecting to a potential monitor area via a buffer circuit,
The problem of limiting the circuit operation speed can be avoided. The buffer circuit may not be able to follow the normal operation speed of the circuit blocks 1 and 2 due to the load of the potential monitor area. However, since the potential of the potential monitor area is not used as an input to another circuit block, It does not limit the operating speed of the entire semiconductor device. That is, the potential monitoring can be performed by lowering the operation speed and allowing the buffer circuit to follow only at the time of failure analysis.

Therefore, as shown in FIG. 4 or FIG.
In the signal path transmitted in the order of the point, the circuit block 1, the point B, the circuit block 2 and the point C, the circuit block 1 monitors the potentials at the points A and B, thereby reducing the potential at the points B and C. Circuit block 2 by monitoring
However, it can be confirmed whether or not each is operating normally.

As described above, according to the semiconductor device of this embodiment, since the area of 0.5 μm square or more is secured as the potential monitor area, it is necessary to prevent the laser from being irradiated to the adjacent diffusion layer. The potential of each potential monitor layer can be detected independently without being affected by the potential of the adjacent diffusion layer, which can be prevented. Further, since the source and drain regions of the transistor and the potential monitor region are clearly distinguished, it is possible to selectively suppress the silicide reaction of only the silicide electrode 13a in the potential monitor region or not to form silicide. , It is possible to avoid the influence of morphological deterioration.

Embodiment 2 Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a plan view for explaining the configuration of the semiconductor device according to the second embodiment of the present invention, and FIG.
5 is a cross-sectional view taken along line cc ′ of FIG.

Referring to FIG. 6, the semiconductor device according to the second embodiment will be described. As in the first embodiment, a p-type well diffusion layer 2 and a p-type well diffusion layer 2 are formed on the surface of a p-type silicon substrate 1. An n-type well diffusion layer 3 is formed. In the n-type well diffusion layer 3, a p-type source region 6, a p-type drain region 7, and an n-type well contact region 9 are formed. Has an n-type source region 4, an n-drain region 5, and a p-type well contact region 10. Further, a gate electrode 8 is formed between each source and drain region via a gate oxide film, an adjacent source and drain are separated by a gate electrode 8, and an adjacent source is separated by an insulating oxide film region. I have.

The semiconductor device of this embodiment differs from the first embodiment in that the source and drain regions 4, 5, 6, 7
Are formed with a minimum dimension of 0.5 μm or less,
An n-potential monitor region 11, which becomes 0.5 μm square or more by combining a plurality of adjacent source and drain regions,
Alternatively, a p-type potential monitor region 12 is formed.

That is, the source in each potential monitor area,
As shown in FIG. 7, the drain regions are electrically interconnected by metal wirings 16 and are configured to be supplied with the same potential. With such a configuration, an arbitrary transistor region can be used as a potential monitor region by wiring connection, so that it is not necessary to set the potential monitor region in advance, and the potential monitor region is lower than in the first embodiment. There is an advantage that the number and arrangement of monitor areas can be freely changed by wiring design.

However, when the above-described technique for improving the silicide interface morphology is applied, it is necessary to set a potential monitor region in advance, and the degree of freedom in design is not greatly improved. Therefore, this embodiment is particularly effective for a semiconductor device manufactured by a manufacturing method in which the silicide interface morphology does not hinder the potential monitor.

Third Embodiment Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a plan view for explaining the configuration of the semiconductor device according to the third embodiment of the present invention, and FIGS. 9 and 10 are cross-sectional views taken along line dd 'of FIG.

Referring to FIG. 8, the semiconductor device according to the third embodiment will be described. As in the first embodiment, the p-type silicon substrate 1 has the p-type source region 6 and the p-type
A type drain region 7, an n-type well contact region 9, an n-type source region 4, an n-drain region 5, and a p-type well contact region 10 are formed. Also, each source,
A gate electrode 8 is provided between the drain regions via a gate oxide film.
Are formed, the adjacent source and drain are separated by a gate electrode 8, and the adjacent sources are separated by an insulating oxide film region.

In the semiconductor device of this embodiment, a part of the region where the transistor of the first or second embodiment shown in FIG. 1 or FIG. Potential monitor area 11 or p-type potential monitor area 1
2 is replaced with the formation region 2.

In the case of the first embodiment, the potential monitor region is formed by extending the source region of the transistor.
To monitor a source other than the source potential of the expanded transistor, it is necessary to supply a potential at a portion to be monitored to the potential monitor region by wiring, and the transistor cannot be used as an element. That is, in order to monitor the potential at any one place, it is necessary to sacrifice one transistor. Also, in the case of the second embodiment, since a region of one transistor is used as a potential monitor region while one potential is monitored, it is necessary to sacrifice one transistor.

On the other hand, the potential monitor region of the third embodiment shown in FIG. 8 is configured such that two potential monitor regions are formed in one transistor region.
If the number of potential monitors is the same, there is an advantage that the reduction in transistor integration can be suppressed to half.

The technique of suppressing the deterioration of the interface morphology by selectively suppressing the silicide reaction of the silicide electrode 13a in the potential monitor region, which was possible in the potential monitor region of the first embodiment, is described in the present embodiment. The present invention can be applied to the potential monitoring region of the example. In the case of the potential monitor region shown in FIG. 1, since there is a portion sharing the diffusion layer with the source region of the transistor, the influence on the transistor characteristics is inevitable, and the manufacturing conditions cannot be set completely independently. However, since the potential monitor region of FIG. 8 is formed completely separately from the transistor region, there is an advantage that the potential monitor region can be formed under optimized manufacturing conditions as the potential monitor region.

Fourth Embodiment Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a cross-sectional view for explaining the configuration of the semiconductor device according to the fourth embodiment of the present invention, and is a cross-sectional view taken along the line dd 'of FIG. 8, similarly to FIG.

The layout of the source or drain region, the potential monitor region and the like of the semiconductor device according to the fourth embodiment is the same as that of the third embodiment described above, but the fourth embodiment shown in FIG. Most of the potential monitoring region 11 is not covered with the silicide electrode 13a, but is covered with the metal wiring layer 16 via the insulating film.

In the potential monitor region 11, the potential of the desired source region 4 to be monitored is applied via the metal wiring 16 to the silicide electrode 13 provided at the end of the potential monitor region 11.
a. The region of the potential monitor region 11 which is not covered with the silicide electrode 13a is formed by securing a region having a plane dimension of 0.5 μm square or more.

When monitoring the potential of the potential monitor region 11 by the laser potential probing method, the laser beam irradiated from the back surface of the silicon substrate 1 is formed by the p-type well diffusion layer and the n-type potential monitor layer. After passing through the interlayer film and reaching the metal wiring layer 16 through the pn junction, the light is reflected and returns to the back surface of the silicon substrate 1.
That is, the metal wiring 16 functions as a reflector for laser light, and has an advantage that irregular reflection of laser light can be prevented with respect to a silicide electrode whose morphology is degraded by a silicide reaction.

[0046]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that failure analysis can be performed by applying the laser potential probing method even in a semiconductor device in which the diffusion layer region is formed of a miniaturized transistor smaller than the laser beam diameter. It is to become.

The reason is that a diffusion layer having a sufficiently large size with respect to the beam diameter of the laser to be probed is formed as a potential monitoring region, and the region is electrically connected to a portion where the potential is to be monitored. This is because a potential at a desired location can be monitored.

The second effect is that failure analysis using the laser potential probing method can be performed even in a semiconductor device composed of a transistor whose diffusion layer surface is covered with metal silicide having poor interface morphology. That's what it means.

The reason is that the diffusion layer formed separately from the diffusion region of the transistor is used as a potential monitoring region, so that silicidation of the surface of the diffusion layer in the potential monitoring region can be suppressed. This is because the laser light is reflected by the metal wiring and the potential can be monitored.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the structure of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view taken along the line aa 'of FIG.

FIG. 3 is a view for explaining the structure of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view taken along the line bb 'of FIG.

FIG. 4 is a circuit block diagram for explaining an operation of the semiconductor device according to the first example of the present invention.

FIG. 5 is a circuit block diagram for explaining an operation of the semiconductor device according to the first example of the present invention.

FIG. 6 is a plan view for explaining a structure of a semiconductor device according to a second example of the present invention.

FIG. 7 is a view for explaining the structure of a semiconductor device according to a second embodiment of the present invention, and is a cross-sectional view taken along the line cc 'in FIG.

FIG. 8 is a plan view illustrating the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 9 is a view for explaining the structure of the semiconductor device according to the third embodiment of the present invention, and is a cross-sectional view taken along line dd ′ of FIG.

FIG. 10 is a diagram for explaining the structure of a semiconductor device according to a fourth embodiment of the present invention, and is a cross-sectional view taken along line dd ′ of FIG.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate 2 p-type well diffusion layer 3 n-type well diffusion layer 4 n-type source region 5 n-type drain region 6 p-type source region 7 p-type drain region 8 gate electrode 9 n-type well contact region 10 p-type substrate Contact region 11 N-type potential monitor region 12 P-type potential monitor region 13 Silicide electrode 13a Silicide electrode (potential monitor region) 14 Silicon oxide film 15 Metal plug 16 Metal wiring 17 Insulation isolation region

Claims (7)

[Claims] A plurality of transistors each having a source region and a drain region separated by a gate electrode are formed on one surface of a semiconductor substrate via an insulating separation region, and the source and drain regions are formed above the transistor. In a semiconductor device, a metal wiring connected to each of the semiconductor substrates is provided, and a potential of a predetermined region of the transistor is measured by measuring a reflected light intensity of a laser beam emitted from another surface of the semiconductor substrate. A potential monitor region having a predetermined area that can partially receive the laser light is formed in the source region or the drain region, and a source region, a drain region, or a gate other than the potential monitor region to be subjected to potential measurement. An electrode is electrically connected to the potential monitor area, and reflects the laser light applied to the potential monitor area. A semiconductor device, wherein a potential of a region to be measured for the potential is measured from light intensity. 2. A plurality of transistors each having a source region and a drain region separated by a gate electrode are formed on one side surface of a semiconductor substrate via an insulating separation region, and the source and drain regions are formed above the transistor. In a semiconductor device, a metal wiring connected to each of the semiconductor substrates is provided, and a potential of a predetermined region of the transistor is measured by measuring a reflected light intensity of a laser beam emitted from another surface of the semiconductor substrate. A plurality of source and drain regions adjacent to each other via the gate electrode or the insulating isolation region are interconnected by the metal wiring to form a potential monitor region having a predetermined area capable of receiving the laser beam and having the same potential; The transistor outside the potential monitor region, wherein the source region and the drain A region or a gate electrode is electrically connected to the potential monitor region, and a potential of the region to be measured for the potential is measured from a reflected light intensity of a laser beam applied to the potential monitor region, Semiconductor device. 3. A plurality of transistors having a source region and a drain region separated by a gate electrode are formed on one side surface of a semiconductor substrate via an insulating separation region, and the source and drain regions are formed above the transistor. In a semiconductor device, a metal wiring connected to each of the semiconductor substrates is provided, and a potential of a predetermined region of the transistor is measured by measuring a reflected light intensity of a laser beam emitted from another surface of the semiconductor substrate. Forming a potential monitor region having a diffusion region having a predetermined area capable of receiving the laser light in a region other than the gate electrode, the source region, or the drain region; The source region, the drain region or the gate electrode of the target is electrically connected to the potential monitor region, A semiconductor device, wherein a potential of a region to be measured for the potential is measured from a reflected light intensity of a laser beam applied to the potential monitoring region. 4. A metal silicide layer is formed on surfaces of the source region, the drain region, and the potential monitor region, and the metal silicide layer of the potential monitor region is smaller than the metal silicide layer of the source region or the drain region. 4. The semiconductor device according to claim 1, wherein the laser light is reflected by the metal silicide layer in the potential monitoring region. 5. 5. A metal silicide layer is not formed on the surface of the potential monitor region, and the potential monitor region is covered with the metal wiring when viewed from the direction of incidence of the laser light, and the laser light is 4. The semiconductor device according to claim 3, wherein the light is reflected by the wiring. 6. A buffer circuit or an inverter circuit is constituted by a part of the transistor, an output of the buffer circuit or the inverter circuit is connected to the potential monitor area, and an input of the buffer circuit or the inverter circuit is connected to a potential measuring point. The semiconductor device according to claim 1, wherein the semiconductor device is connected to any one of a source region, a drain region, and a gate electrode of the transistor. 7. The semiconductor device according to claim 1, wherein a predetermined area capable of receiving the laser beam is larger than 0.5 μm square.