JP2000260842A - Test element group for detecting short circuiting between wirings, its manufacturing method, and method for detecting the short circuiting between wirings - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely detect the there is a risk of short circuiting between wiring, in a semiconductor integrated circuit. SOLUTION: A test element group consists of a plurality of parallel lower- layer wiring 12 formed a the upper portion of a substrate, where a semiconductor integrated circuit is formed, an interlayer insulating film 13 for covering the area between the lower layer wiring and an upper portion, and comb-shaped upper-layer wiring 14 and 15 which is formed on the interlayer insulating film 13, while opposing each other independently. An interval G of the lower-layer wiring 12 is formed, while being changed. Although the test element group is made to generate etching remainder at the upper-layer wirings 14 and 15 due to the level difference caused by the lower-layer wiring 12 for indicating the presence or absence of the short-circuiting between wiring, the state of a plurality of types of level differences to the upper-layer wiring 14 and 15 for setting the worst state can be set by changing the interval G of the lower- layer wiring 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test element group (hereinafter simply referred to as "short-circuit") for detecting a short circuit between wirings formed on a wafer substrate or the like together with a semiconductor integrated circuit and used for detecting a short circuit between wirings in the semiconductor integrated circuit. , A test element group), a method of manufacturing a test element group for detecting a short between wires, and a method of detecting a short between wires.

[0002]

2. Description of the Related Art FIG. 2 is a configuration diagram showing a conventional test element group. The test element group includes a plurality of lower wirings 2 formed on a substrate 1 together with a semiconductor integrated circuit (not shown). An interlayer insulating film 1a is deposited on a substrate 1, and a lower wiring 2 is formed on the interlayer insulating film 1a. Each lower wiring 2 is independent of a semiconductor integrated circuit (not shown) on the substrate 1 and is arranged in parallel with the same width and at equal intervals. The space between and above the lower wirings 2 is covered with an interlayer insulating film 3. On the interlayer insulating film 3, two systems of comb-shaped upper wirings 4 and 5 are formed. The plurality of comb teeth in the comb-shaped upper wiring 4 are formed so as to be orthogonal to the lower wiring 2. A plurality of comb teeth of the comb-shaped upper wiring 5 are also formed so as to be orthogonal to the lower wiring 2. The comb teeth of the upper wiring 4 and the comb teeth of the upper wiring 5 are arranged alternately. The upper wirings 4 and 5 are formed by the same manufacturing process as the wiring pattern to be inspected of the semiconductor integrated circuit.
7 is connected.

This test element group is formed on the substrate 1 in order to detect a short circuit between wirings in the same layer in a semiconductor integrated circuit. The lower wiring 2 causes a step in the upper wirings 4 and 5. Structure. The reason for adopting the structure in which the steps are formed is to deteriorate the state of the upper wirings 4 and 5 and to cause an etching defect in those parts. At the portions corresponding to the gaps between the lower wirings 2 of the upper wirings 4 and 5, the etching becomes incomplete,
The wiring member remains in a filament shape, and the comb teeth of the upper wiring 4 and the comb teeth of the upper wiring 5 are connected by the remaining wiring member. Since the upper wirings 4 and 5 and the wiring pattern to be inspected in the semiconductor integrated circuit are formed in the same process, the conduction state is detected by conducting a continuity test between the upper wirings 4 and 5 to detect the semiconductor. It is possible to detect whether or not there is a risk that a short circuit between wirings has occurred in the integrated circuit.

[0004]

However, the conventional test element group has the following problems. The level difference between the upper wiring 4 and the upper wiring 5 is determined by the arrangement of the lower wiring 2. However, since the width and the interval of the lower wiring 2 are constant, the worst state is not necessarily set to the upper wirings 4 and 5. Even when a short circuit occurs between wirings in the semiconductor integrated circuit, the upper wiring 4,
The continuity test of No. 5 may not be able to detect it, and there was a problem in reliability.

[0005]

Means for Solving the Problems To solve the above problems, a first invention of the present invention has the following configuration in a test element group. That is, a plurality of lower wirings which are formed independently of the semiconductor integrated circuit on the substrate on which the semiconductor integrated circuit is formed, are oriented in a predetermined direction, are arranged in parallel with each other at different intervals, and And an inter-layer insulating film deposited so as to cover the upper part of the lower wiring, and formed on the inter-layer insulating film to form a comb, and a plurality of comb teeth in the comb shape face in a direction orthogonal to the plurality of lower wirings. The first upper wiring and the plurality of comb teeth of the comb formed in a comb shape formed on the interlayer insulating film are oriented in a direction perpendicular to the lower wiring and are defined as the first upper wiring. And second upper layer wirings arranged alternately. By adopting such a configuration, the interval between the lower wirings changes, so that a plurality of types of steps can be generated due to the lower wirings, and the first upper wiring and the second upper wiring tend to cause etching failure, You can set the worst situation.

In the second invention, in the test element group, a plurality of lower wirings are formed with different line widths. By adopting such a configuration,
Since the line width of the lower-layer wiring changes, a plurality of types of states of the steps caused by the lower-layer wiring can be provided, and the first upper-layer wiring and the second upper-layer wiring are liable to cause etching failure, and the worst state can be set. .

In the third invention, in the test element group, the plurality of lower-layer wirings are formed with different line widths and arranged at different intervals. By adopting such a configuration, the width and the interval of the lower wiring are changed, so that a plurality of types of steps can be generated due to the lower wiring, and the first upper wiring and the second upper wiring are likely to cause etching failure. And the worst conditions can be set.

According to a fourth aspect of the present invention, in the method of manufacturing a test element group for manufacturing the test element group according to the first, second or third aspect, the following manufacturing method is employed. That is, a plurality of lower wirings are arranged and formed independently of the semiconductor integrated circuit on the substrate on which the semiconductor integrated circuit is formed, and the lower wirings are filled so as to fill the lower wirings and cover the upper parts of the lower wirings. The first upper wiring and the second upper wiring are formed on the interlayer insulating film by the same process as that for depositing the insulating film and manufacturing the wiring pattern to be inspected in the semiconductor integrated circuit. Since the manufacturing method is configured in this manner, the first upper layer wiring and the second upper layer wiring are formed in the same process as the wiring pattern to be inspected, so that the manufacturing conditions of the wiring pattern of the semiconductor integrated circuit fluctuate. This also appears in the state of the first upper layer wiring and the second upper layer wiring, and in a plurality of steps caused by the lower layer wiring, an etching failure occurs according to the state of the first and second upper layer wirings. .

According to a fifth aspect of the present invention, in the method for detecting a short circuit between wires, the test element group according to the first, second or third invention is formed on a substrate, and the first upper layer wire and the second
By conducting a continuity test with the upper wiring, the presence or absence of a short circuit between wirings of the wiring pattern to be inspected in the semiconductor integrated circuit is detected. By employing such a method, when a short circuit occurs between wirings in a wiring pattern to be inspected in a semiconductor integrated circuit, an etching failure occurs at any of a plurality of types of steps. Therefore, by conducting a continuity test between the first and second upper-layer wirings, it is possible to estimate a state of occurrence of a short circuit between the wirings.

[0010]

Embodiment Figure 1 [OF THE PREFERRED EMBODIMENTS OF THE INVENTION A first is a configuration diagram of a test element group of a first embodiment of the present invention. The test element group is a circuit provided on the upper portion of the substrate 10 for determining whether or not a short circuit between wirings in a semiconductor integrated circuit (not shown) has occurred.

An interlayer insulating film 11 is deposited on a substrate 10, and a plurality of polysilicon lower wirings 12 constituting a test element group are formed thereon. The lower wiring 12 is arranged at a position independent of the semiconductor integrated circuit. The thickness of each lower layer wiring 12 is, for example, 0.
7 μm, formed in the same width as in the conventional case, and parallel to each other. The gap G between the plurality of lower wirings 12 is different from that of the related art, for example, is changed around 0.5 μm, and becomes larger from the left end to the right. Between and above the plurality of lower wirings 12, for example, PSG
(Phosphor glass) and the like. On the interlayer insulating film 13, a first upper wiring 14 and a second upper wiring 15 are formed with a thickness of, for example, about 0.3 μm. The upper wiring 14 and the upper wiring 15 are formed by the same process as the process of forming the wiring pattern to be inspected in the semiconductor integrated circuit, and are formed by etching a wiring member such as aluminum. Each of the upper layer wiring 14 and the upper layer wiring 15 has a comb shape, and the comb teeth of the upper layer wiring 14 and the upper layer wiring 15 are perpendicular to the direction of the plurality of lower layer wirings 12. The comb teeth of the upper wiring 14 and the comb teeth of the upper wiring 15 are alternately arranged in parallel. The upper wiring 14 is connected to a continuity test pad 16a, and the upper wiring 15 is connected to a continuity test pad 16b.

FIG. 3 is a diagram showing an etching residue generated in FIG. Since the lower wiring 12 is formed, a step occurs in the interlayer insulating film 13, and a step along the direction of the lower wiring 12 also occurs in the upper wirings 14 and 15 on the interlayer insulating film 13. In the upper wirings 14 and 15 having such a step, the etching is incomplete and the wiring member tends to remain in a filament shape. For example, the lower part of the lower layer wiring 12 is located at a portion A where the lower part of the upper layer wirings 14 and 15 is about the height of the lower layer wiring 12 due to a step.
The edge 17 of the wiring member is likely to be generated near the shoulder of the wiring member. Also, in the part B where the gap G between the lower wirings 12 is large and the lower portions of the upper wirings 14 and 15 are close to the bottom of the gap between the lower wirings 12, the upper wiring 1
The edging residue 18 of the wiring member is likely to occur near the bottom of the depressed portion of the wiring members 4 and 15.

By conducting a continuity test by applying a tester to the continuity test pads 16a and 16b, it is possible to verify whether or not the unetched portions 17 and 18 are generated. If etching residues 17 and 18 occur, the pad 16
A conduction state is shown between a and 16b. At this time, since there is a high possibility that a short circuit between wirings has occurred in the semiconductor integrated circuit, the wafer is processed as a defect.

As described above, in the first embodiment,
Since the distance G between the lower wirings 12 is changed, there are plural types of steps, and even if the film thickness or shape of the interlayer insulating film 13 between the upper wirings 14 and 15 and the lower wiring 12 changes. The worst shape in which the upper wirings 14 and 15 are likely to be left unetched can always be ensured, and the reliability of a test for short circuit between wirings in a semiconductor integrated circuit is improved.

Second Embodiment FIG. 4 is a configuration diagram of a test element group according to a second embodiment of the present invention. This test element group is a circuit provided on the upper part of the substrate 20 for determining whether or not there is a short circuit between wires in a semiconductor integrated circuit (not shown). On the substrate 20, an interlayer insulating film 21 is deposited, and a plurality of lower wirings 22 made of polysilicon constituting a test element group are formed thereon. The lower wiring 22 is arranged at a position independent of the semiconductor integrated circuit. The thickness of each lower wiring 12 is, for example, 0.7
μm, unlike the first embodiment, the interval G is made equal and the width W is changed. Each lower wiring 22 is parallel to each other. The interval G between the plurality of lower wirings 22 is
For example, it is 0.5 μm.

The space between and above the plurality of lower wirings 22 is covered with an interlayer insulating film 23 of, for example, PSG (phosphorus glass). On the interlayer insulating film 23, a first upper wiring 24 and a second upper wiring 25 are formed with a thickness of, for example, about 0.3 μm. The upper wiring 24 and the upper wiring 25 are formed by the same process as the process of forming the wiring pattern to be inspected in the semiconductor integrated circuit, and are made of a wiring member such as aluminum. These upper wirings 24
And the upper layer wiring 25 both have a comb shape, and the comb-shaped comb teeth of the upper layer wiring 24 and the upper layer wiring 25 have a plurality of lower layer wirings 2.
2 is perpendicular to the direction. The respective comb teeth of the upper wiring 24 and the respective comb teeth of the upper wiring 25 are alternately arranged in parallel. The upper wiring 24 is connected to a continuity test pad 26a, and the upper wiring 25 is connected to a continuity test pad 26b.

In this test element group, since the lower wiring 22 is formed, a step is generated in the interlayer insulating film 23, and the upper wirings 24 and 2 on the interlayer insulating film 23 are formed.
5 also has a step along the direction of the lower wiring 22. The state of the step differs depending on the difference in the width of the lower wiring 22. In the upper wirings 24 and 25 having such a step, the etching is incomplete and the wiring member tends to remain in a filament shape. Therefore, by conducting a continuity test by applying a tester to the continuity test pads 26a and 26b, it is possible to verify whether or not an unetched portion has occurred. If the unetched portion is generated, a conduction state is shown between the pads 26a and 26b. At this time, since there is a high possibility that a short circuit between wirings has occurred in the semiconductor integrated circuit, the wafer is processed as a defect.

As described above, in the second embodiment,
Since the width G of the lower wiring 22 is changed, there are a plurality of types of steps that can be formed, and the upper wirings 24 and 25 and the lower wiring 2
Even when the film thickness or shape of the interlayer insulating film 23 changes between 2 and 5, the worst shape in which the upper wirings 24 and 25 are likely to cause etching residue can always be ensured, and a short-circuit test between wires in a semiconductor integrated circuit is performed. Reliability is improved.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications. (1) Lower layer wiring 1 in test element group
The width W, interval G, thickness, and the like of 2, 22 are not limited to the first and second embodiments, but are desirably set according to the structure of the semiconductor integrated circuit. (2) In the first embodiment, the distance G between the lower wirings 12 is changed, and in the second embodiment, the width W of the lower wiring 22 is changed. May be changed.

[0020]

As described above in detail, according to the first aspect, since the interval between the plurality of lower wirings is changed, the step between the interlayer insulating film and the first and second upper wirings is formed. And the worst shape in which the first and second upper-layer wirings are apt to be left unetched can always be ensured. Therefore, according to the fifth aspect, the continuity test of the first and second upper wirings is performed to improve the reliability of the test when detecting the presence / absence of a short circuit between the wirings in the semiconductor integrated circuit.

According to the second aspect of the present invention, since the widths of the plurality of lower wirings are respectively changed, there are a plurality of types of steps between the interlayer insulating film and the first and second upper wirings. The worst shape in which etching residue of the upper wiring 2 is likely to occur can always be ensured. Therefore, according to the fifth aspect, the continuity test of the first and second upper wirings is performed to improve the reliability of the test when detecting the presence / absence of a short circuit between the wirings in the semiconductor integrated circuit.

According to the third aspect of the present invention, since the interval and width of the lower wiring are changed, there are a plurality of types of steps of the interlayer insulating film and the first and second upper wirings.
The worst shape that the etching residue of the upper layer wiring is likely to occur can always be secured. Therefore, according to the fifth invention, the continuity test of the first and second upper wirings is performed,
The reliability of the test for detecting the presence / absence of a short circuit between wires in a semiconductor integrated circuit is improved.

According to the fourth invention, the first,
In the second or third invention, a plurality of lower-layer wirings are arranged and formed, an interlayer insulating film is deposited, and the first upper-layer wiring and the second upper-layer wiring are the same as the step of manufacturing a wiring pattern to be inspected. Since it is formed by a process, even if there is a change in the manufacturing conditions of the wiring pattern, it is manifested in the state of the first upper wiring and the second upper wiring. Therefore, the continuity test of the first and second upper-layer wirings is performed to improve the reliability of the test when detecting the presence / absence of a short circuit between the wirings in the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a test element group according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional test element group.

FIG. 3 is a diagram showing an etching residue generated in FIG. 1;

FIG. 4 is a configuration diagram of a test element group according to a second embodiment of the present invention.

[Explanation of symbols]

 10, 20 Substrate 12, 22 Lower wiring 13, 23 Interlayer insulating film 14, 15, 24, 25 Upper wiring G Lower wiring distance W Lower wiring wiring width

Claims (5)

[Claims] A plurality of lower wirings formed independently of the semiconductor integrated circuit on a substrate on which the semiconductor integrated circuit is formed, and arranged in a predetermined direction in parallel with each other at an interval; An interlayer insulating film deposited so as to fill the space between the lower wirings and cover an upper part of the lower wirings; and a comb formed on the interlayer insulating film to form a comb, and the plurality of comb teeth in the comb shape are the plurality of lower wirings A first upper-layer wiring that is oriented in a direction orthogonal to the first wiring, and a plurality of comb teeth in the comb that are formed on the interlayer insulating film in a direction orthogonal to the lower-layer wiring and the first upper wiring. A test element group for detecting a short circuit between wires, comprising: a plurality of comb teeth of the upper wire and a second upper wire arranged alternately. 2. A semiconductor device comprising: a plurality of lower-layer wirings formed on a substrate on which a semiconductor integrated circuit is formed independently of the semiconductor integrated circuit and arranged in a predetermined direction in parallel with each other and with different line widths; An interlayer insulating film deposited so as to fill a space between the lower wirings and cover an upper part of the lower wirings; and a comb formed on the interlayer insulating film, and a plurality of comb teeth in the comb are formed by the plurality of lower layers. A first upper-layer wiring that is oriented in a direction orthogonal to the wiring; and a comb formed on the interlayer insulating film, and a plurality of comb teeth in the comb are oriented in a direction orthogonal to the lower-layer wiring and the first upper wiring. A test element group for detecting a short circuit between wirings, comprising: a plurality of comb teeth of the upper wiring and a second upper wiring arranged alternately. 3. A plurality of lower layers which are formed independently of the semiconductor integrated circuit on a substrate on which the semiconductor integrated circuit is formed, are arranged in a predetermined direction, parallel to each other, and at different intervals and line widths. A wiring, an interlayer insulating film deposited so as to fill a space between the lower wirings and cover an upper part of the lower wiring, and formed on the interlayer insulating film to form a comb, and the plurality of comb teeth in the comb are formed by the plurality of comb teeth. A first upper-layer wiring that faces in a direction orthogonal to the lower-layer wiring, and is formed on the interlayer insulating film to form a comb shape, and a plurality of comb teeth in the comb shape face a direction perpendicular to the lower-layer wiring and An inter-wiring short detection element group, comprising: a plurality of comb teeth of a first upper wiring and a second upper wiring alternately arranged. 4. The method of manufacturing an element group for detecting a short circuit between wirings according to claim 1, 2 or 3, wherein the element group for detecting a short circuit between wirings is provided on an upper portion of the substrate on which the semiconductor integrated circuit is formed. Independently of the semiconductor integrated circuit, the plurality of lower-layer wirings are arranged and formed, and the interlayer insulating film is deposited so as to fill between the lower-layer wirings and cover an upper part of the lower-layer wirings. Forming the first upper layer wiring and the second upper layer wiring on the interlayer insulating film in the same step as the step of manufacturing a wiring pattern to be inspected; Method. 5. An element group for detecting a short circuit between wirings according to claim 1, 2 or 3, is formed on the substrate, and a continuity test between the first upper wiring and the second upper wiring is performed. A method for detecting a short circuit between wirings of the wiring pattern to be inspected in the semiconductor integrated circuit.