JP2000332554A - Variable gain amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier which can easily control a gain in a desirable range while preventing the chip area from increasing. SOLUTION: The variable gain amplifier is provided with a 1st differential amplifier equipped with emitter-connected transistors (TR) Q3 and Q4 and a 2nd differential amplifier equipped with emitter-connected TRs Q5 and Q6. The TRs Q3 to Q6 have the same shape and characteristics. An emitter resistance R3 is connected to the emitter of the TR Q4 and an emitter resistance R4 is connected to the emitter of the TR Q5. Further, the amplifier is provided with a TR Q1 connected to the emitter of the TR Q3 and the emitter resistance R3 and a TR Q2 which is connected to the emitter of the TR Q6 and the emitter resistance 4. Then a 3rd differential amplifier is provided which has TRs Q1 and Q2 and emitter resistances R1 and R2 connected between them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier used for communication equipment and the like, and more particularly to a variable gain amplifier for reducing a chip area and simplifying gain control.

[0002]

2. Description of the Related Art Conventionally, there has been known a variable gain amplifier in which two differential amplifiers are cascode-connected to one differential amplifier, and one transistor is connected to one output terminal. Hereinafter, this conventional example is referred to as a first conventional example.
FIG. 12 is a circuit diagram showing a configuration of a first conventional variable gain amplifier.

The first conventional example is provided with a first differential amplifier having transistors Q23 and Q24 which are emitter-coupled. Similarly, a second differential amplifier having emitter coupled transistors Q25 and Q26 is provided. The transistors Q23 to Q26 have mutually equivalent shapes and characteristics. Further, a transistor Q21 connected to the emitters of the transistors Q23 and Q24 and a transistor Q22 connected to the emitters of the transistors Q25 and Q26 are provided. Further, a third differential amplifier including transistors Q21 and Q22 and emitter resistors R21 and R22 connected therebetween is provided. That is, the first and second
Are cascode-connected to the third differential amplifier.

[0004] A constant current source S21 is connected between a node between the resistors R21 and R22 and the ground potential. Load resistors R25 and R26 are connected to the collectors of the transistors Q23 and Q26, respectively, and the other ends of the load resistors R25 and R26 are connected to the power supply potential Vcc.

[0005] Complementary input signals IN and INB are input to the bases of transistors Q21 and Q22, respectively. On the other hand, the output signals OUT21 and OUT22 are output as the potentials of the collectors of the transistors Q23 and Q26, respectively.

The positive voltage of the control signal Vcont is input to the bases of the transistors Q23 and Q26, and the control signal Vcont is input to the bases of the transistors Q24 and Q25.
The negative voltage of cont is input. The gain of the amplifier is controlled by the control signal Vcont.

[0007] The first constructed in this way in the prior art, people each collector current of the transistor Q21 through _{Q26 i c21, i c22, i} c23, i c24, i c25 and i _{c 26,} the output signal OUT21 and OUT22 V _OUT21
And V _OUT22, load resistors R25 and respectively the resistance value of R26 's R ₂₅ and R _26, I ₂₀ the current value of the constant current source S21, the absolute temperature T, the Boltzmann constant k, the amount of charge q,
Equations 1 to 3 below hold.

[0008]

[Number 1] _{i c21 = i c23 + i c24} i c22 = i c25 + i c26

[0009]

[Number 2] _{I 20 = i c21 + i c22} i c21 = i c22 = I 20/2

[0010]

[Number 3] _{i c23 = i c21 / 1 +} exp (-Vcont / Vt) i c25 = i c22 / 1 + exp (+ Vcont / Vt) Vt = kT / q

In the first conventional example, the collector current i
_Since the gain is determined by the values of _c23 and i _c26 , the voltage drop of the load resistors R25 and R26 changes, and the DC output voltage fluctuates. Therefore, since the DC input voltage in the next stage circuit fluctuates,
The voltage margin is reduced, the AC waveform is clipped, and the junction capacitance of the transistor is affected.
For this reason, it is necessary to connect a capacitor or the like to the output terminal of the variable gain amplifier, which increases the chip area. Further, when a capacitor or the like is connected, there is a disadvantage that the frequency of a signal that can pass therethrough is limited. Note that the DC output voltage is obtained by averaging the AC output voltage and eliminating fluctuations due to time.

Therefore, a variable gain amplifier has been proposed which aims to eliminate these drawbacks. Hereinafter, this conventional example is referred to as a second conventional example. FIG. 13 is a circuit diagram showing a configuration of a second conventional variable gain amplifier.

The second prior art is provided with a first differential amplifier having transistors Q13 and Q14 which are emitter-coupled. Similarly, a second differential amplifier with emitter-coupled transistors Q15 and Q16 is provided. The transistors Q13 to Q16 have shapes and characteristics equivalent to each other. Further, a transistor Q11 connected to the emitters of the transistors Q13 and Q14 and a transistor Q12 connected to the emitters of the transistors Q15 and Q16 are provided. Then, a third differential amplifier including the transistors Q11 and Q12 and the emitter resistors R11 and R12 connected therebetween is provided. That is, the first and second
Are cascode-connected to the third differential amplifier.

A constant current source S11 is connected to a node between the resistors R11 and R12 between the node and the ground potential. The collectors of the transistors Q13 and Q15 and the transistors Q14 and Q16 have load resistors R15 and R15, respectively.
And R16 are connected, and load resistors R15 and R1 are connected.
The other end of 6 is connected to power supply potential Vcc.

The complementary input signals IN and INB are input to the bases of transistors Q11 and Q12, respectively. On the other hand, the output signals OUT11 and OUT12 are output as the potentials of the collectors of the transistors Q13 and Q15 and the transistors Q14 and Q16, respectively.

The positive voltage of the control signal Vcont is input to the bases of the transistors Q13 and Q16, and the control signal Vcont is input to the bases of the transistors Q14 and Q15.
The negative voltage of cont is input. The gain of the amplifier is controlled by the control signal Vcont. Such a variable gain amplifier is generally called a Gilbert circuit.

[0017] the second configured as above in the conventional example, respectively i _c11 collector current of the transistor Q11 through _{Q16, i c12, i c13,} i c14, i c15 and i _c16, the output signal OUT11 and OUT12 _{Set the} voltage to V _OUT11
And V _OUT12, load resistors R15 and respectively R ₁₅ and R ₁₆ the resistance value of R16, the current value of the constant current source S11, the I _10, holds the following equation 4-7.

[0018]

[Number 4] _{i c11 = i c13 + i c14} i c12 = i c15 + i c16

[0019]

[Number 5] _{I 10 = i c11 + i c12} i c11 = i c12 = I 10/2

[0020]

[6] _{i c13 = i c11 / 1 +} exp (-Vcont / Vt) i c15 = i c12 / 1 + exp (+ Vcont / Vt)

[0021]

[Equation 7] _{V OUT11 = R 15 (i c13} + i c15) V OUT12 = R 15 (i c14 + i c16)

That is, the current value of the output signal OUT11 is (i
_c13 + i _c15) to become. Note that the collector currents i _c11 and i
_{Since c12} is out of phase, collector currents i _c13 and i _c15
Also have opposite phases.

When the complementary input signals IN and INB are input to the bases of the transistors Q11 and Q12, they are differentially amplified and input to the first and second differential amplifiers. Current values i _c11 and i _c12 in the first and second differential amplifiers
Is determined by the offset of the control signal Vcont. That is, the division amount is variable. Then, the voltages of the output signals OUT11 and OUT12 are determined and output by the voltage drop due to the load resistors R15 and R16.

FIG. 14 is a graph showing the relationship between the control voltage in the horizontal axis and the gain in the vertical axis, showing the relationship between the two in the second conventional example. FIG. 15 shows the output of various control signals in FIG. It is a graph which shows the waveform of a signal. The solid line in FIG. 15 indicates the waveform of the output signal at point A or F, the broken line indicates the waveform of the output signal at point B or E, and the two-dot chain line indicates the waveform of the output signal at point C or D. Current flowing through transistor Q13 or Q15 and transistor Q14
Or the current signal flowing through Q16 is the complementary signal, as shown in FIGS. 14 and 15, when the voltage of the control signal Vcont is _{0 (mV), i c13 =} i c15 = 0, i c14 =
i _c16 = 0, and the output signal is minimized. Further, as the absolute value of the control voltage increases, the amplitude of the output signal increases.

[0025]

However, in the second conventional example, the gain can be controlled within a desired range, particularly near the lower limit, when there is a variation in the elements of the transistor or when there is a temperature change. There is a problem that it is extremely difficult.

The present invention has been made in view of the above problems, and has as its object to provide a variable gain amplifier capable of easily controlling a gain within a desired range while preventing an increase in chip area. And

[0027]

A variable gain amplifier according to the present invention comprises: a constant current source; first and second transistors connected to the constant current source and receiving signals to be amplified; Third and fourth transistors whose signals output from the second transistor are input and whose gain is controlled by the control signal, and whose signals output the second transistor are input and whose gain is controlled by the control signal The fifth
And a sixth transistor, a first output terminal connected to the third and fifth transistors, and a second output terminal connected to the fourth and sixth transistors. Wherein the voltage of the control signal is 0
It has a finite gain at (mV).

Another variable gain amplifier according to the present invention comprises a constant current source, first and second transistors connected to the constant current source and receiving a signal to be amplified, and an output from the first transistor. And fourth transistors whose amplification factors are controlled by the control signal and the fifth and fifth transistors whose signals are input from the second transistor and whose amplification factors are controlled by the control signal. A variable gain amplifier comprising: a sixth transistor; a first output terminal connected to the third and fifth transistors; and a second output terminal connected to the fourth and sixth transistors. The value of the voltage when the sign of the slope of the gain with respect to the voltage of the control signal is inverted is shifted from 0 (mV).

In the present invention, the voltage of the control signal is 0
(MV) has a finite gain, or the value of the voltage when the sign of the gain gradient with respect to the voltage of the control signal is inverted deviates from 0 (mV). The slope of the gain with respect to the voltage of the control signal at (mV) becomes gentler than that of the conventional one. For this reason,
Even if element variations or temperature changes occur,
Gain variability is reduced. Therefore, it is possible to easily control the gain within a desired range. Further, since the output voltage is substantially constant, it is not necessary to connect a capacitor or the like for preventing a change in the output voltage to the output terminal.

In the present invention, it is desirable that the absolute value of the gradient of the gain with respect to the voltage when the voltage of the control signal is 0 (mV) is 0.11 (dB / mV) or less.

Further, the first transistor and the third transistor
And at least one resistor connected between the second transistor and the fourth transistor and between the second transistor and the fifth and sixth transistors. In this case, it is preferable that the resistor is connected to a transistor to which a negative voltage of the control signal is applied.

Further, the emitter area of at least one of the third to sixth transistors is:
It may be different from the emitter area of other transistors. In this case, it is preferable that the emitter area of the transistor to which the positive voltage of the control signal is applied is larger than the emitter area of the transistor to which the negative voltage of the control signal is applied.

As described above, since one resistor is provided or the emitter area is different, the transfer characteristics from the emitter to the collector of the dual differential transistor are different from each other, and the control signal is different. The value of the voltage when the sign of the gain gradient with respect to the voltage is inverted is 0 (mV).
, And the gain gradient becomes gentle.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a variable gain amplifier according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a configuration of a variable gain amplifier according to a first embodiment of the present invention.

The first embodiment includes a first differential amplifier having transistors Q3 and Q4 that are emitter coupled. Similarly, a second differential amplifier having emitter coupled transistors Q5 and Q6 is provided. The transistors Q3 to Q6 have shapes and characteristics equivalent to each other. An emitter resistor R3 is connected to the emitter of the transistor Q4.
The emitter resistor R4 is connected to the emitter of the reference numeral 5. Further, the emitter of the transistor Q3 and the emitter resistor R3
The transistor Q2 is connected to the emitter of the transistor Q1 and the transistor Q6 and to the emitter resistor 4. The transistors Q1 and Q2 and the emitter resistors R1 and R2 connected therebetween
Is provided. That is, the first and second differential amplifiers are cascode-connected to the third differential amplifier.

A constant current source S1 is connected to a node between the resistors R1 and R2 between the node and the ground potential. Also, transistors Q3 and Q5 and transistors Q4 and Q6
Are connected to load resistors R5 and R6, respectively. The other ends of the load resistors R5 and R6 are connected to the power supply potential Vcc.
It is connected to the.

The complementary input signals IN and INB are input to the bases of transistors Q1 and Q2, respectively. on the other hand,
Output signals OUT1 and OUT2 are output from transistors Q
3 and Q5 and the collector potentials of the transistors Q4 and Q6.

The positive voltage of the control signal Vcont is input to the bases of the transistors Q3 and Q6, and the control signal Vcont is input to the bases of the transistors Q4 and Q5.
Is input. The gain of the amplifier is controlled by the control signal Vcont.

Next, the transistors Q3 and Q4 in the variable gain amplifier of the first embodiment configured as described above
(AC) collector currents _ic3 and _ic4 will be described. FIGS. 2A and 2B are schematic diagrams showing the relationship between the control voltage of the control signal Vcont and the collector current in the first embodiment and the second conventional example, respectively.

In the second conventional example, the transistor Q
If the current I ₁₀ flowing through the 11, the collector current i _c13 and i _c14 are mutually consistent when the control voltage becomes 0 (mV). At this time, as shown in FIG. 14, the output signal becomes minimum. On the other hand, in the first embodiment, when a current flows I ₀ to transistors Q11, a collector current i _c3
And i _c4 coincide with each other when the control voltage becomes a predetermined value shifted to the negative side from 0 (mV). Therefore, when the control voltage is 0 (mV), a voltage based on the difference between the collector currents _ic3 and _ic4 is output as an output signal.

Further, the value of the collector current i _c3 and i _c5 of the transistors Q3 and Q5 are represented by the following equation 8, the sum is a current value of the output signal OUT1.

[0042]

[Equation 8] _{i c3 = i c1 / 1 +} exp (-Vcont / Vt) i c5 = i c2 / 1 + exp (+ Vcont / Vt)

FIG. 3 is a graph showing the relationship between the control voltage in the first embodiment and the control voltage on the horizontal axis and the gain on the vertical axis. In the first embodiment, as described above, the collector currents _ic3 and _ic4 coincide with each other when the control voltage becomes a predetermined value shifted to the negative side from 0 (mV). This is the same for the transistors Q5 and Q6. As a result, as shown in FIG. 3, the value of the control voltage when the gain is minimum becomes a negative value. Therefore, the slope of the curve near the control voltage of 0 (mV) is gentle.

Therefore, for example, the variable range of the gain is -1.
In the case of 5 dB to +15 dB, even if the control voltage at which the gain becomes minimum as shown by the broken line in FIG. -15dB
The deviation from is small. Therefore, it is easy to control the gain to -15 dB.

The absolute value of the gain gradient with respect to the control voltage when the voltage of the control signal is 0 (mV) is 0.11 (d
B / mV) or less, the gain control can be further facilitated.

FIG. 4 is a graph showing a variation in gain in the second conventional example. In the second conventional example, when the variable range of the gain is from −15 dB to +15 dB, there is a variation in characteristics due to transistor element variation or temperature change, so that the gain is minimized as shown by a broken line in FIG. If the voltage slightly shifts, the shift of the gain from -15 dB is extremely large. Therefore, as described above, the gain is -1.
It is difficult to control to 5 dB.

As described above, according to the first embodiment, the rate of change of the gain with respect to the voltage of the control signal Vcont becomes gentle near the control voltage of 0 (mV). Thus, a stable gain variable characteristic can be obtained.

Further, since the DC output voltage is substantially constant, it is not necessary to provide a capacitor or the like required for the first conventional example, so that an increase in chip area can be suppressed. .

In the first embodiment, the emitter resistors R3 and R5 are connected to the emitters of the transistors Q4 and Q5, respectively. However, as shown in FIG. If the rate of change of the gain with respect to the voltage of the control signal Vcont becomes gentle,
The transistor to which the emitter resistance is connected is not particularly limited. For example, transistors Q3 to Q6
May be connected to an emitter resistor.

Further, a voltage control circuit for controlling the voltage of control signal Vcont may be provided. FIG. 5 is a circuit diagram showing an example in which a voltage control circuit is added to the first embodiment. The voltage control circuit is provided with diodes D1 and D2 connected to the input terminal of the power supply potential Vcc, and transistors Q7 and Q8 are connected to the output terminals, respectively. The emitters of the transistors Q7 and Q8 are connected to a constant current source S2. Then, the control signal Vcont is input to the bases of the transistors Q7 and Q8. That is, the voltage characteristics of the control signal Vcont are corrected using the diodes D1 and D2 as loads.

FIG. 6 is a graph showing a change in gain when a voltage control circuit is added. Note that the two-dot line in FIG. 6 is based on the first embodiment in which the voltage control circuit is not added. The addition of the voltage control circuit makes the change of the gain gentle in the variable range of the gain, so that the variation is further reduced.

Next, a second embodiment of the present invention will be described. In the second embodiment, the emitter resistors are not connected to the transistors provided in the first and second differential amplifiers, and the emitter areas of some of these transistors are different from the others. . FIG. 7 is a circuit diagram showing the configuration of the variable gain amplifier according to the second embodiment of the present invention.
In the second embodiment shown in FIG. 7, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment, the emitter resistance R
3 and R4 are not provided, and the emitter areas of the transistors Q3a and Q6a are larger than those of the transistors Q4 and Q5.

In the second embodiment configured as described above, since a difference occurs in the operating resistance of the emitter, it is possible to obtain a stable gain variable characteristic with respect to element variation and temperature change.

The transistor Q3a in the second embodiment
And the value of the collector current i _c3a and i _c5 of Q5 is expressed by the following equation 9, as in the first embodiment, the sum is a current value of the output signal OUT1.

[0056]

[Equation 9] _{i c3a = i c1 / 1 +} exp (-Vcont / Vt) i c5 = i c2 / 1 + exp (+ Vcont / Vt)

In the first and second embodiments,
Although a bipolar transistor is used as the transistor, a field effect transistor may be used.

Further, an inductance may be connected to an emitter of a transistor provided in each of the first and second differential amplifiers.

Next, simulation results for the first and second embodiments and the first and second conventional examples will be described.
In the first embodiment, the resistance values of the emitter resistors R3 and R4 are set to 200Ω. In the second embodiment, the emitter area of the transistors Q3a and Q6a is six times that of the transistors Q4 and Q5. FIGS. 8A and 8B are graphs showing gain simulation results for the first and second embodiments, respectively. FIG.
FIG. 7 is a graph showing a simulation result of an output voltage with respect to the first embodiment. FIGS. 10A and 10B are graphs showing simulation results of gains with respect to the first and second conventional examples, respectively. FIGS. 11A and 11B are graphs showing simulation results of output voltages for the first and second conventional examples, respectively. Note that the output voltage in FIGS. 9 and 11 is, for example, an average of AC voltage, and indicates a DC value. FIG.
As shown in FIG. 11, by providing a so-called Gilbert circuit, fluctuation of the output voltage can be prevented.

[0060]

As described in detail above, according to the present invention,
Since the control signal has a finite gain when the voltage of the control signal is 0 (mV), or the value of the voltage when the sign of the slope of the gain with respect to the voltage of the control signal is inverted deviates from 0 (mV), The gradient of the gain with respect to the voltage of the control signal when the voltage of the control signal is 0 (mV) can be made gentler than that of the conventional one. Thus, even when element variation or temperature change occurs, variation in gain can be reduced, and gain can be easily controlled within a desired range. In addition, since a change in output voltage can be prevented, it is not necessary to connect a capacitor or the like to the output terminal, and an increase in chip area can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a variable gain amplifier according to a first embodiment of the present invention.

FIGS. 2A and 2B are a first embodiment and a second embodiment, respectively.
FIG. 9 is a schematic diagram showing a relationship between a control voltage of a control signal Vcont and a collector current in the conventional example of FIG.

FIG. 3 is a graph showing a relationship between a control voltage and a gain in the first embodiment.

FIG. 4 is a graph showing a variation in gain in a second conventional example.

FIG. 5 is a circuit diagram showing an example in which a voltage control circuit is added to the first embodiment.

FIG. 6 is a graph showing a change in gain when a voltage control circuit is added.

FIG. 7 is a circuit diagram showing a configuration of a variable gain amplifier according to a second embodiment of the present invention.

FIGS. 8A and 8B are graphs showing gain simulation results for the first and second embodiments, respectively.

FIG. 9 is a graph showing a simulation result of an output voltage with respect to the first embodiment.

FIGS. 10 (a) and (b) are graphs showing gain simulation results for the first and second conventional examples, respectively.

FIGS. 11A and 11B are graphs showing simulation results of output voltages for the first and second conventional examples, respectively.

FIG. 12 is a circuit diagram showing a configuration of a first conventional variable gain amplifier.

FIG. 13 is a circuit diagram showing a configuration of a second conventional variable gain amplifier.

FIG. 14 is a graph showing a relationship between a control voltage and a gain in a second conventional example.

FIG. 15 is a graph showing waveforms of output signals of various control signals in FIG.

[Explanation of symbols]

Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q
11, Q12, Q13, Q14, Q15, Q16, Q2
1, Q22, Q23, Q24, Q25, Q26; transistors R1, R2, R3, R4, R5, R6, R11, R1
2, R15, R16, R21, R22, R23, R2
5, R26; resistor S1, S2, S11, S12; constant current source D1, D2; diode

Claims (7)

[Claims] 1. A constant current source, first and second transistors connected to the constant current source and receiving a signal to be amplified, and a signal output from the first transistor being input and receiving a control signal Third and fourth transistors whose gains are controlled, fifth and sixth transistors whose signals output from the second transistor are input and whose gains are controlled by the control signal, And a first output terminal connected to the fifth transistor;
And a second output terminal connected to a sixth transistor, wherein the variable gain amplifier has a finite gain when the voltage of the control signal is 0 (mV). 2. A constant current source, first and second transistors connected to the constant current source and receiving signals to be amplified, and a signal output from the first transistor is input and controlled by a control signal. Third and fourth transistors whose gains are controlled, fifth and sixth transistors to which a signal output from the second transistor is input and whose gain is controlled by the control signal; And a first output terminal connected to the fifth transistor;
And a second output terminal connected to the sixth transistor, the value of the voltage deviating from 0 (mV) when the sign of the gain gradient with respect to the voltage of the control signal is inverted. A variable gain amplifier, comprising: 3. An absolute value of a gain gradient with respect to the voltage when the voltage of the control signal is 0 (mV) is 0.11 (d
B / mV) or less.
3. The variable gain amplifier according to item 1. 4. At least one transistor connected between the first transistor and the third and fourth transistors and between the second transistor and the fifth and sixth transistors. The variable gain amplifier according to any one of claims 1 to 3, further comprising a resistor. 5. The variable gain amplifier according to claim 4, wherein the resistor is connected to a transistor to which a negative voltage of the control signal is applied. 6. The transistor according to claim 1, wherein an emitter area of at least one of the third to sixth transistors is different from an emitter area of another transistor. The variable gain amplifier according to the paragraph. 7. The variable gain according to claim 6, wherein the emitter area of the transistor to which the positive voltage of the control signal is applied is larger than the emitter area of the transistor to which the negative voltage of the control signal is applied. amplifier.