JP2000332045A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable preventing change in characteristics of a semiconductor element by relieving mechanical stresses applied to a bump electrode, when it is mounted. SOLUTION: An electrode pad 2, composed of Al is formed on a P-type semiconductor substrate 1, and a MOS transistor 4 is formed on the semiconductor substrate 1 directly below the electrode pad 2 via an interlayer insulating film 3. A stress-relaxing film 9 constituted of a polyimide film is interposed between the interlayer insulating film 3 on the MOS transistor 4 and the electrode pad 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing a chip size by forming a semiconductor element on a semiconductor substrate immediately below an electrode pad, and more particularly, to mounting such a semiconductor device by a COB method. The present invention relates to a technique for reducing the influence of mechanical stress generated at the time of bonding and mechanical shock during wire bonding on semiconductor device characteristics.

[0002]

2. Description of the Related Art Conventionally, a semiconductor element such as a MOS transistor has not been formed below a pad electrode of a semiconductor device. This is because, when a semiconductor element is formed in such a region, a large mechanical impact is applied to the semiconductor element via a pad electrode during wafer probing and wire bonding, causing fluctuations in element characteristics and deterioration in reliability.

However, if the output MOS transistor is formed at a position distant from the pad electrode, there is a limit in achieving high integration of the LSI. For example, for a driving IC such as an LCD driver, an LED driver, and a thermal head driver, which has a multi-bit output,
The number of output pins is large, which is very disadvantageous in reducing the chip size.

Therefore, as disclosed in Japanese Patent Application Laid-Open No. 9-283525, a material such as solder or gold is mounted on a pad electrode in a ball shape (a so-called bump electrode), and this is thermocompressed or thermocompressed. By melting, COB
In a semiconductor device electrically connected to a substrate, a semiconductor element such as a MOS transistor is formed below the pad electrode. According to this technique, mechanical shocks during wafer probing and wire bonding are not applied to the pad electrodes, and fluctuations in element characteristics due to the mechanical shocks can be prevented.

The structure of the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 9-283525 will be described with reference to FIG. 5
Reference numeral 1 denotes a semiconductor substrate, which has a LOC so as to surround an element formation region.
An OS oxide film 52 is formed, and an output MOS transistor 53 is formed in an element formation region surrounded by the LOCOS oxide film 2. The output MOS transistor 53 includes a gate oxide film 54, a gate electrode 55, a source diffusion layer 56A and a drain diffusion layer 5 formed on both sides of the gate electrode 55.
6B.

Then, a first interlayer insulating film 57 covering the output MOS transistor 53, and the first interlayer insulating film 57
Through the contact hole provided in the source diffusion layer 56.
A, a source electrode 58A and a drain electrode 58B that are in contact with the drain diffusion layer 56B are formed.

Further, a source electrode 58A and a drain electrode 5
A second interlayer insulating film 59 is formed on 8B, and a through hole (Via Hole) 60 is formed in the second interlayer insulating film 59. The pad electrode 61 and the drain electrode 56 formed on the second interlayer insulating film 59 through the through hole 60
B is connected.

Then, a passivation film 62 having an opening is formed on the pad electrode 61. On the pad electrode 61, a Cu film 65 and a solder bump electrode 66 are formed via a plating electrode film 63 and a barrier metal film 64 made of a Cr / Cu film.

[0009]

SUMMARY OF THE INVENTION
By being applied to a semiconductor device using a COB method and using a multi-layered metal wiring, there is an effect that a large mechanical shock during wire bonding is not received and a variation in element characteristics due to the impact can be suppressed. .

However, the above-described semiconductor device is not
In the case of mounting by a method, a mechanical stress is applied to the solder bump electrode 66 due to a difference in thermal expansion coefficient between the semiconductor substrate and the mounting substrate due to a temperature change, and this stress is applied to the pad electrode 61, the first and second pads. The MOS transistor 3 is applied to the MOS transistor 3 via the interlayer insulating films 7 and 9, and characteristics such as a threshold value of the MOS transistor 3 fluctuate, which may cause an abnormality in circuit operation. When a temperature cycle test (125 ° C. to −45 ° C.) was performed by mounting the above semiconductor device by the COB method, an abnormality was sometimes found in circuit operation. According to the stress simulation using the finite element method, it was found that a large stress was applied to the electrode pad 61 portion.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to reduce a chip size by forming a semiconductor element on a semiconductor substrate immediately below an electrode pad, and to mount the semiconductor device by a COB method. It is an object of the present invention to provide a semiconductor device in which the mechanical stress applied to the bump electrode at the time of the reduction, the mechanical shock at the time of wire bonding is reduced, the characteristics of the semiconductor element are prevented from changing, and the reliability is improved. .

[0012]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device having an electrode pad formed on a semiconductor substrate, a bump electrode formed on the electrode pad, and a semiconductor element formed on a semiconductor substrate immediately below the electrode pad via an interlayer insulating film, A stress relaxation film made of a polyimide film is interposed between the interlayer insulating film on the semiconductor element and the electrode pad.

Thus, the mechanical stress applied to the bump electrode when the semiconductor device is mounted by the COB method is reduced.
Variations in the characteristics of the semiconductor element can be prevented.

Further, according to the present invention, there is provided a semiconductor device comprising: an electrode pad formed on a semiconductor substrate; a bump electrode formed on the electrode pad; and a semiconductor element formed on the semiconductor substrate immediately below the electrode pad. And a first interlayer insulating film covering the semiconductor element;
A stress formed by a drain electrode contacting a drain diffusion layer of the semiconductor element, a second interlayer insulating film formed on the drain electrode, and a polyimide film interposed between the second interlayer insulating film and the pad electrode Connecting the relief film, a through hole formed in the second interlayer insulating film outside the end of the stress relaxation film, and the wiring drawn out from the drain electrode and the pad electrode through the through hole. It is characterized by.

[0015] Thereby, the mechanical stress applied to the bump electrode when the semiconductor device is mounted by the COB method is reduced,
It is possible to prevent the characteristics of the semiconductor element from fluctuating, and to apply the present invention to a semiconductor device using multilayer wiring.

Further, the semiconductor device of the present invention has an electrode pad formed on a semiconductor substrate, a bonding wire fixed on the electrode pad, and an interlayer insulating film on the semiconductor substrate immediately below the electrode pad. A stress relief film made of a polyimide film is interposed between the interlayer insulating film on the semiconductor element and the electrode pad.

Thus, the mechanical shock at the time of wire bonding can be reduced, and the characteristics of the semiconductor element can be prevented from changing.

In the above invention, it is preferable that the stress relaxation film is formed so as to extend outside the electrode pad in order to effectively relieve stress.

Further, in the above invention, the stress relaxation film is located outside the pad electrode up to a distance where the strain energy generated in the stress relaxation film decreases to a constant value when the semiconductor device is mounted on the mounting substrate. Preferably it is extended.

In the state where the semiconductor device is mounted on the mounting board, the stress applied to the bump electrode, especially the vicinity of the interface between the bump electrode and the pad electrode, is absorbed as strain energy by the stress relaxation film. According to the stress simulation, as the distance over which the stress relaxation film extends outside the pad electrode increases, this strain energy is dispersed and reduced in the stress relaxation film, and the stress applied to the bump electrode is also reduced. You. The strain energy generated in the stress relaxation film decreases to a constant value at a certain distance from the pad electrode. Therefore, the stress can be effectively relieved by expanding the stress relieving film to such a distance.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a diagram showing a semiconductor device according to the first embodiment. FIG. 1A is a plan view, and FIG.
FIG. 2 is a sectional view taken along line XX in FIG.

An electrode pad 2 made of Al is formed on a P-type semiconductor substrate 1, and a semiconductor substrate 1 immediately below the electrode pad 2 is formed.
A MOS transistor 4 is formed thereon via an interlayer insulating film 3. The MOS transistor 4 includes a gate oxide film 5, an n + -type source diffusion layer 6A and a drain diffusion layer 6A.
B, a gate electrode 7 made of a polysilicon film.

A source electrode 8A made of Al is connected to the source diffusion layer 6A via a contact, and the source electrode 8A is connected to a power supply potential VCC. on the other hand,
The drain diffusion layer 6B has a drain electrode 8B made of Al.
Is connected via a contact, and the drain electrode 8B
Are connected to the pad electrode 2. An output control signal from an internal circuit of the LSI is applied to the gate electrode 7. That is, the MOS transistor 4 is an output transistor.

A stress relaxation film 9 made of a polyimide film is interposed between the interlayer insulating film 3 on the MOS transistor 4 and the electrode pad 2. After the polyimide (PIX) is spin-coated and prebaked, the stress relaxation film 9 is directly exposed and developed in the case of a photosensitive polyimide, and is exposed and developed using a resist in the case of a non-photosensitive polyimide. Etching is performed so as to leave in a predetermined region. In the case of a photosensitive polyimide, a positive polyimide is usually used. To relieve the stress, the thickness of the stress relaxation film 9 is preferably as thick as possible.
There is a limit because there is a risk of disconnection. Therefore,
A film thickness of 2 μm is appropriate.

The above semiconductor device is covered with a passivation film 10 such as a silicon nitride film, but has an opening on the pad electrode 2.

The stress relaxation film 9 is formed immediately below the pad electrode 2. It is conceivable to form a contact hole (or a through hole) in the stress relaxation film 9. And the effect of stress relaxation may be reduced.

Then, a bump electrode (not shown) is formed on the pad electrode 2 in the same manner as in the conventional example, and the semiconductor device is mounted on a mounting substrate. Since the polyimide film is an elastic material and has a property of absorbing stress, the mechanical stress applied to the bump electrode, particularly in the vicinity of the interface between the bump electrode and the pad electrode 2 in the mounted state is relaxed. The stress on a certain MOS transistor 4 is also reduced.

Further, normal wire bonding may be performed on the pad electrode 2. At this time, a bonding wire is formed on the pad electrode 2. According to the semiconductor device of the present invention, since the stress relaxation film 9 is formed, the mechanical shock of wire bonding is reduced,
Variations in characteristics and destruction of the OS transistor 4 can be prevented.

Although the above embodiment is an example of a single-layer Al wiring process, the present invention relates to a multi-layer Al wiring process as described below.
It can also be applied to the l wiring process.

FIG. 2 is a diagram showing a semiconductor device according to the second embodiment.

A MOS transistor 22 is formed on a P-type semiconductor substrate 21. The MOS transistor 22
It comprises a gate oxide film 23, an n + type source diffusion layer 24A and a drain diffusion layer 24B, and a gate electrode 25 made of a polysilicon film.

The MOS transistor 22 is covered with a first interlayer insulating film 26 made of a BPSG film. The source diffusion layer 24A has a source electrode 27A made of Al.
Are connected via a contact, and the source electrode 27A
Are connected to the power supply potential VCC. On the other hand, a drain electrode 27B made of Al is connected to the drain diffusion layer 24B via a contact. An output control signal from an internal circuit of the LSI is applied to the gate electrode 25. That is, the MOS transistor 22 is an output transistor.

Source electrode 27A and drain electrode 27B
A second interlayer insulating film 28 made of a TEOS film is formed thereon. A stress relaxation film 29 made of polyimide is formed on the second interlayer insulating film 28, and a pad electrode 30 made of Al is formed on the stress relaxation film 29. A through hole 31 is formed in the second interlayer insulating film 28 outside the end of the stress relaxation film 29, and the drain electrode 27 </ b> B and the wiring 32 drawn from the pad electrode 22 are connected via the through hole 31. I have.

That is, the through holes 31 are provided in the second interlayer insulating film 28 without forming through holes in the stress relaxation film 30. This is because when the pad electrode 30 is provided on the through hole, a concave portion is formed in the pad electrode 30,
This is because subsequent bump formation becomes difficult.

The semiconductor device is covered with a passivation film 36 such as a silicon nitride film.
An opening is provided on 0. Then, a Cu film 34 and a solder bump electrode 35 are formed on the pad electrode 30 via a barrier metal film 33 made of a Cr / Cu film in the same manner as in the conventional example.

In the first and second embodiments, as shown in FIG. 3A, the stress relaxation films 9 and 29 are formed so as to extend outside the electrode pads 2 and 30 to reduce the stress. It is preferable for effective relaxation. Further, the stress relaxation films 9 and 29 may be extended outward from the pad electrode to a distance where the strain energy generated in the stress relaxation film decreases to a certain value when the semiconductor device is mounted on the mounting substrate. preferable.

In the state where the semiconductor device is mounted on the mounting substrate, the stress applied to the bump electrode 35, particularly the vicinity of the interface between the bump electrode 35 and the pad electrode 30, is absorbed by the stress relaxation film 29 as strain energy. You.

FIG. 3B is a simulation diagram by the finite element method showing the relationship between the strain energy and the distance L from the electrode pad to the end of the stress relaxation film. As shown in the figure, as the distance L over which the stress relaxation film extends outside the pad electrode increases, this strain energy is dispersed and reduced in the stress relaxation film. Then, the stress applied to the bump electrode is also reduced. The strain energy generated in the stress relaxation film decreases to a constant value at a certain distance from the pad electrode. Therefore, the stress can be effectively relieved by expanding the stress relieving film to such a distance.

In the above embodiment, when a semiconductor element other than the MOS transistor, for example, a PN junction diode, a resistance element using a diffusion layer, a capacitance element having a capacitance insulating film between the electrodes, etc. are formed immediately below the pad electrode. However, it is clear that fluctuations in the characteristics of these semiconductor elements can be prevented.

[0041]

As described above, according to the semiconductor device of the present invention, it is possible to alleviate the mechanical stress applied to the bump electrode when mounted by the COB method, and to prevent the fluctuation of the characteristics of the semiconductor element. it can.

Further, the mechanical shock at the time of wire bonding can be reduced, and the fluctuation of the characteristics of the semiconductor element can be prevented.

The stress relieving film can be effectively relieved by forming the stress relieving film so as to extend outside the electrode pad.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a relationship between a semiconductor device according to an embodiment of the present invention and strain energy.

FIG. 4 is a sectional view showing a semiconductor device according to a conventional example.

Claims (6)

[Claims] An electrode pad formed on a semiconductor substrate;
In a semiconductor device having a bump electrode formed on the electrode pad and a semiconductor element formed on a semiconductor substrate immediately below the electrode pad via an interlayer insulating film, the semiconductor device includes the interlayer insulating film on the semiconductor element, A semiconductor device comprising a stress relaxation film made of a polyimide film interposed between an electrode pad. 2. An electrode pad formed on a semiconductor substrate,
In a semiconductor device having a bump electrode formed on the electrode pad and a semiconductor element formed on a semiconductor substrate immediately below the electrode pad, a first interlayer insulating film covering the semiconductor element; A drain electrode contacting a drain diffusion layer of the device; a second interlayer insulating film formed on the drain electrode; and a stress relaxation film comprising a polyimide film interposed between the second interlayer insulating film and the pad electrode. And a through hole formed in the second interlayer insulating film outside the end of the stress relaxation film, and the drain electrode and the wiring drawn from the pad electrode are connected via the through hole. Semiconductor device. 3. An electrode pad formed on a semiconductor substrate,
In a semiconductor device having a bonding wire fixed on the electrode pad and a semiconductor element formed on a semiconductor substrate immediately below the electrode pad via an interlayer insulating film, an interlayer insulating film on the semiconductor element is provided. A semiconductor device comprising a stress relaxation film made of a polyimide film interposed between the electrode pad and the electrode pad. 4. The stress relaxation film according to claim 1, wherein the stress relaxation film is formed to extend outside the electrode pad.
The semiconductor device according to claim 3. 5. The stress relaxation film is extended outward from the pad electrode to a distance where the strain energy generated in the stress relaxation film decreases to a constant value when the semiconductor device is mounted on a mounting substrate. 3. The semiconductor device according to claim 1, wherein: 6. The semiconductor device according to claim 1, wherein the semiconductor element is a transistor, a diode, a resistor, or a capacitor.