JP2000331953A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow manufacturing of a semiconductor device of high performance and reliability by facilitating a minute contact of a drawing electrode. SOLUTION: A process where first and second insulating films 63 and 64 of different kind are laminated on a semiconductor substrate, a process where first and second openings faced by the semiconductor substrate are formed on the insulating films 63 and 64, a process where a step opening part 84B for contact which comprises the first opening as well as a third opening where, communicating with the first opening, only the second insulating film 64 is selected and removed is formed, a process where a conductor 85 is embedded in a step opening part 84B and a second opening 79E, and a process where the conductor 85 is flattened up to the surface of the second insulating film 64 so that conductors 85E and 85B formed in the second opening 79E and the step opening part 84B, respectively, are electrically independent each other, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device such as a bipolar transistor.

[0002]

2. Description of the Related Art Conventionally, there has been proposed an ultra-high-speed bipolar transistor in which a base extraction electrode and an emitter extraction electrode are formed of a polycrystalline silicon film and a base region and an emitter region are formed in a self-aligned manner. .

FIG. 11 shows an example of this ultra-high-speed bipolar transistor. In this bipolar transistor 1,
A base extraction electrode 7 of a first p ⁺ polycrystalline silicon film is provided on an n-type epitaxial layer 4 serving as a collector region 3 on a first conductivity type, for example, a p-type semiconductor substrate 2, and p-type diffusion is performed by impurity diffusion. ⁺ Forming an external base region 8;
⁺ A link base region 11 for connecting the external base region 8 and the intrinsic base region is formed by ion implantation through an opening 10 selectively formed in the polycrystalline silicon film and the SiO ₂ film 9 thereon. A second polycrystalline silicon film 13 is formed at the same time as forming an insulating side wall portion, ie, a SiO ₂ side wall 12, and a p-type impurity and an n-type impurity are introduced through the second polycrystalline silicon film The p-type intrinsic base region 4 and the n-type emitter region 5 are formed by lines, and the second polycrystalline silicon film 13 is configured as an emitter extraction electrode. 14 is an n-type collector buried layer, 15 is a p-type channel stop region, 16
Is an n-type collector extraction region, 20 is a field insulating film,
Reference numerals 17, 18 and 19 are a base electrode, a collector electrode and an emitter electrode made of metal (for example, Al).

FIGS. 9 and 10 show a method of manufacturing a bipolar transistor using a conventional polycrystalline silicon embedding technique (see IED 86 PP420-423). First,
As shown in FIG. 9A, after an n-type collector buried layer 32 and a p-type channel stop region 33 are formed in a p-type silicon substrate 31, an n-type epitaxial layer 34 serving as a collector region is formed. A collector extraction region 35 reaching the collector buried layer 32 is formed, and a field insulating film 36 is formed by selective oxidation. And the Si ₃ N ₄ film 37
After the formation of the CVD SiO ₂ film 38, the opening is patterned to form an opening 39 in a portion corresponding to a base extraction electrode to be formed later.

Next, as shown in FIG. 9B, ap ⁺ polycrystalline silicon film 40a is formed on the entire surface, and a resist film 41 is further formed.
Is formed and then etched back to leave a resist film 41 on the step portion of the p ⁺ polycrystalline silicon film 40.

[0006] Next, as shown in FIG.
Using p as a mask, the p ⁺ polycrystalline silicon film 40a is selectively etched to form a base extraction electrode 40 of the p ⁺ polycrystalline silicon film 40a.

[0007] Next, as shown in FIG.
And the portion corresponding to the collector extraction region 35
O_TwoThe film 38 is selectively removed, and the base extraction electrode 40 is removed.
p⁺Selectively oxidize the surface of the polycrystalline silicon film to form SiO_TwoMembrane 4
Form one. At this time, p ⁺From polycrystalline silicon film to p
Impurity is diffused to partially form p-type external base region 42.
It is.

Next, the Si ₃ N ₄ film 37 is selectively removed with hot phosphoric acid. Then, a p-type impurity is ion-implanted into the active region to form a p-type base region 43. Next, a second n ⁺ polycrystalline silicon film 45a is formed and patterned to form an emitter extraction electrode 46 and a collector extraction electrode 47. Thereafter, annealing is performed to form an n-type emitter region 44 by diffusion of n-type impurities from the n ⁺ polycrystalline silicon film.

Next, a contact hole is formed, and Al
A base electrode 48, an emitter electrode 49, and a collector electrode 50 are formed to manufacture a bipolar transistor 51 shown in FIG. 10E.

[0010]

However, the above-mentioned FIG.
10 has the following problem in the bipolar transistor 51 using the polysilicon embedding technique. (I) Polycrystalline silicon film 40a for extracting base and polycrystalline silicon film 45a for extracting emitter and collector
Are separately formed, so that the number of manufacturing steps increases. (Ii) connecting the base extraction electrode 40 to the emitter extraction electrode 46
Is performed with the thermal oxide film 41 on the surface of the base extraction electrode 40 in order to perform insulation separation from the substrate.
In the selective oxidation using the i ₃ N ₄ film as a mask), crystal defects occur due to the stress near the bird's beak of the thermal oxide film 41, and then the n ⁺ polycrystalline silicon film 4 serving as an emitter extraction electrode
When the emitter region 44 is formed by impurity diffusion from 5 a, there is a risk that the impurity may be accelerated and diffused and a part of the emitter may pass through the base region 43. This causes a leak between the emitter and the collector, thereby deteriorating the transistor characteristics. (iii) The so-called base contact width W between the base extraction electrode 40 and the external base region 42 is equal to the field insulating film 36, the SiO ₂ film 38, and the opening 39 of the Si ₃ N ₄ film 37 in FIG. 8A.
There is a limit to miniaturization because it is determined by the alignment with This limits the reduction of the junction capacitance between the base and the collector, and hinders the increase in speed.

In view of the foregoing, the present invention provides a method for manufacturing a semiconductor device having high performance and high reliability by facilitating fine contact of an extraction electrode.

[0012]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of laminating first and second insulating films of different types on a semiconductor substrate and forming the first and second insulating films on the semiconductor substrate. Forming a first and a second opening; and forming a contact step opening comprising a first opening and a third opening which is selectively removed from the second insulating film in communication with the first opening. A step of forming, a step of embedding a conductor in the step opening and the second opening, and a step of flattening the conductor to the surface of the second insulating film to form the respective conductors formed in the second opening and the step opening. It has a step of making the conductor electrically independent.

In the present invention, a conductor is buried in the step opening and the second opening, and the conductor is flattened to the surface of the second insulating film and formed in the step opening and the second opening, respectively. Are electrically independent from each other, so that independent conductors can be simultaneously formed in the same step. The first and second insulating films between the second opening and the stepped opening function as separating layers for insulating and separating the respective conductors, whereby the respective conductors are reliably electrically separated.

Each of these conductors can be used as an extraction electrode. The contact width between the conductor in the stepped opening and the semiconductor substrate can be reduced to the resolution limit of lithography when forming the first opening. Therefore, the performance can be improved, for example, the junction capacitance determined by the contact width can be reduced, and the device can be manufactured with high reliability.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

First, a basic manufacturing process of the present invention will be described with reference to FIGS. As shown in FIG. 1A, two types of insulating films, that is, a SiO ₂ film 63 and a SiN film 64 in this example, are formed on one main surface of a semiconductor substrate 62. And this S
A first resist mask 65 is formed on the iN film 64.

Next, as shown in FIG. 1B, the first opening 66 is formed by selectively removing the SiN film 64 and the SiO ₂ film 63 through the first resist mask 65 by RIE. Further, a second resist mask 67 is formed.

Next, as shown in FIG. 2C, only the SiN film 64 is partially removed selectively through the second resist mask 67 to form a second opening 68. A step opening 69 is formed.

Next, as shown in FIG. 2D, a conductor such as polycrystalline silicon or metal, in this example, a polycrystalline silicon film 70 is formed on the entire surface including the step opening 69 by CVD, and then etched. Backing is performed so that the polycrystalline silicon film 70 is embedded in the step opening 69.

According to this method, the polycrystalline silicon 70 can be buried in the stepped opening 69 having a step shape.
The embedding it can be used as the polycrystalline taken out silicon 70 electrodes, and the contact width W ₁ of the semiconductor substrate of the extraction electrode in this case is determined by the width W _a of the first resist mask opening 66, the resist mask 65 Can be reduced to the resolution limit of lithography at the time of forming.

FIGS. 3 to 6 show an embodiment of the present invention, in which the present invention is applied to a bipolar transistor manufacturing method utilizing the above method. In this embodiment, an n-type collector buried layer 72 and a p-type channel stop region 7 are formed in a p-type silicon substrate 71 as shown in FIG. 3A.
3. A collector region 75 and an n-type collector extraction region 74 are formed by an n-type epitaxial layer separated by a field insulating film 75, and a p-type base region 76 is formed in the collector region 75.

Next, as shown in FIG. 3B, the SiO ₂ film 6
After the formation of the SiN film 3 and the SiN film 64, a first resist mask 78 having openings 77B, 77E, and 77C is formed in portions corresponding to a base extraction region, an emitter region, and a collector extraction region to be subsequently formed.

Next, as shown in FIG. 4C, the SiN film 64 and the SiO ₂ film 63 are formed through the first resist mask 80.
Is selectively etched to form a first opening 79 facing the silicon surface.
B, 79E and 79C are formed. Next, an opening 81B is formed in a portion straddling the field insulating film from the base extracting region and a portion straddling the field insulating film in the collector extracting region.
And a second resist mask 82 having 81C.

Next, as shown in FIG. 4D, only the upper SiN film 64 is selectively etched away via the second resist mask 82 to form second openings 83B and 83C. Step opening 8 composed of 79B and 83B
Step opening 84C including 4B and openings 79C and 83C
To form

Next, a polycrystalline silicon film 85 is formed on the entire surface by CV.
5D, the surface is flattened by etch back, and the polycrystalline silicon films 85B, 85C, 85E are buried in the step openings 84B, 84C and the opening 79E as shown in FIG. 5E.

Next, although not shown, the polycrystalline silicon film 85 in the stepped opening 84B is selectively inserted through a resist mask.
B is ion-implanted with a p-type impurity such as boron, and the polycrystalline silicon film 85E in the opening 79E and the step opening 84C are formed.
An n-type impurity, for example, arsenic is ion-implanted into the polycrystalline silicon film 85C in the inside and then annealed to form ap ⁺ base extraction region 87 by boron diffusion from the polycrystalline silicon film 85B as shown in FIG. 5F. Crystal silicon film 85E
The n ⁺ emitter region 88 is formed by arsenic diffusion from the GaAs, and a further high-concentration region 89 is formed in the collector extraction region 74 by arsenic diffusion from the polycrystalline silicon film 85C.

In this step, p⁺Polycrystalline silicon film 8
5B becomes a base extraction electrode, and n ⁺Polycrystalline silicon film
85E becomes an emitter extraction electrode, and n⁺Polycrystalline silico
The film 85C serves as a collector extraction electrode.

Thereafter, after further forming an SiO ₂ film 90 on the entire surface, contact holes are formed, and metal (for example, Al) is formed in each of the extraction electrodes 85B, 85E, and 85C.
The base electrode 91, the emitter electrode 92, and the collector electrode 93 are formed to obtain the target npn bipolar transistor 94 shown in FIG.

According to the manufacturing method of the bipolar transistor, since the emitter extraction electrode 85E, the bases extraction electrode 85B and the collector extraction electrode 85C are simultaneously formed by the first polycrystalline silicon film 85, the number of manufacturing steps can be reduced. . Also, the base extraction electrode 85
Since the separation between B and the emitter extraction electrode 85E is performed by self-alignment by the insulating films 63 and 64 used in the stepped opening, unlike the conventional case of thermal oxidation shown in FIGS. Transistor characteristics can be obtained.

Further, the contact width of each extraction electrode including the base extraction electrode 85B can be reduced to the limit of lithography when forming the first opening 77. Therefore, for example, the junction capacitance between the base and the collector can be reduced, and the speed can be increased. As described above, in this embodiment, a highly reliable bipolar transistor capable of high performance and high integration can be easily manufactured.

Although the extraction electrodes 85E, 85B, and 85C are formed of only the polycrystalline silicon film 85 in FIGS. 3 to 6 in the above example, other than that, as shown in FIGS. Each base extraction electrode, emitter extraction electrode and collector extraction electrode may be formed by a polycide film 98 [98E, 98B, 98C] composed of 96 [96E, 96B, 96C] and a metal silicide film 97 [97E, 97B, 97C]. It is possible.

According to the bipolar transistor 99 of this embodiment, the parasitic resistance of each extraction electrode can be reduced, and the thickness of the polycrystalline silicon film 96 is appropriately reduced. Holes are reduced from being accumulated in the polycrystalline silicon film 96E in the emitter extraction electrode, and the predetermined diffusion amount (accordingly, the capacitance between the emitter and the base) can be reduced.

Although the examples shown in FIGS. 3 to 6 are applied to a symmetric npn transistor, a pnp transistor can be formed in the same manner.

FIG. 8 shows another embodiment in which the above method is applied to a MISFET. In this embodiment, an SiO ₂ film 102 serving as a gate insulating film is formed on a silicon substrate 101 of a first conductivity type, and a SiN film 1 is further formed thereon.
After the formation of the gate electrode 03, the left and right symmetric step openings 104S and 104D are formed at intervals corresponding to the gate length, and only the SiN film 103 on the gate portion is selectively removed to form the opening 105G. .

Next, a polycrystalline silicon film 106 is formed on the entire surface, and is flattened to form the respective step openings 104S, 1S.
04D and an opening 105G in the polycrystalline silicon film 106S,
Embedding 106D and 106G.

Then, the respective polycrystalline silicon films 106S, 10
6D and 106G are ion-implanted with a second conductivity type impurity,
Annealing is performed to form a source region 107S and a drain region 107D by impurity diffusion from the polycrystalline silicon films 106S and 106D in the step openings 104S and 104D, and the respective polycrystalline silicon films 106S, 106D and 106G are respectively The MISFET 108 is obtained as an extraction electrode, a drain extraction electrode and a gate extraction electrode.

In the MISFET 108, the contact width of the source extraction electrode 106S and the drain extraction electrode 106D can be reduced, and further miniaturization is possible.

[0038]

According to the method of manufacturing a semiconductor device of the present invention, independent conductors (that is, conductors that are insulated and separated from each other) connected to a semiconductor substrate are simultaneously formed in one step. And the number of manufacturing steps can be reduced. With the first and second insulating films between the step opening and the second opening,
The conductors formed in the step opening and the second opening can be reliably insulated and separated. A step opening for contact is provided which includes a first opening and a third opening in which only the second insulating film is selectively removed, and a conductor is buried therein. The width can be reduced to the limit of lithography when forming the first opening. Therefore, a semiconductor device having high performance and high reliability can be easily manufactured.

[Brief description of the drawings]

FIGS. 1A and 1B are basic manufacturing process diagrams (part 1) of a method for manufacturing a semiconductor device of the present invention.

FIGS. 2C and 2D are basic manufacturing process diagrams (part 2) of the method for manufacturing a semiconductor device of the present invention.

3A and 3B are manufacturing process diagrams (part 1) illustrating one embodiment (applied to a bipolar transistor) of the method of manufacturing a semiconductor device of the present invention.

FIGS. 4A and 4B are manufacturing process diagrams (part 2) illustrating one embodiment (applied to a bipolar transistor) of the method for manufacturing a semiconductor device of the present invention.

FIGS. 5A and 5B are manufacturing process diagrams (part 3) showing one embodiment (applied to a bipolar transistor) of the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a manufacturing process diagram (part 4) showing one embodiment (applied to a bipolar transistor) of the method for manufacturing a semiconductor device of the present invention.

7A and 7B are manufacturing process diagrams showing another embodiment (applied to a bipolar transistor) of a method of manufacturing a semiconductor device of the present invention.

FIG. 8 is a configuration diagram in the case where the method of manufacturing a semiconductor device according to the present invention is applied to a MISFET.

9A to 9C are manufacturing process diagrams (1) showing a manufacturing method of a conventional bipolar transistor.

10A and 10B are manufacturing process diagrams (No. 2) showing a manufacturing method of a conventional bipolar transistor.

FIG. 11 is a configuration diagram showing a conventional example of a bipolar transistor.

[Explanation of symbols]

62 semiconductor substrate, 63 SiO ₂ film, 64 S
iN film, 65, 67 ‥‥ resist mask, 66, 68 ‥
{Opening, 69} step opening, 70} conductor, 71}
{Silicon substrate, 72} Collector buried layer, 73}
Channel stop area, 74 ° collector extraction area,
75 ° field insulating film, 76 ° base region, 77
B, 77C, 77E opening, 78, 82 resist mask, 79B, 79C, 79E opening, 81B, 8
1C opening, 84B, 84C step opening, 85 °
{Polycrystalline silicon film, 85B} Base extraction electrode, 8
5C ‥‥ collector extraction electrode, 85E ‥‥ emitter extraction electrode, 87 ‥‥ base take-out region, 88 ‥‥ emitter region, 90 ‥‥ SiO ₂ film, 91, 92, 93 ‥‥ Al
Electrode, 94 ‥‥ bipolar transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336

Claims (1)

[Claims] A step of laminating first and second insulating films of different types on a semiconductor substrate; a step of forming first and second openings facing the semiconductor substrate in the insulating film; Forming a step opening for contact comprising a first opening and a third opening which is selectively removed from the second insulating film in communication with the first opening; and Embedding a conductor in the second opening; flattening the conductor to the surface of the second insulating film; electrically connecting the conductors formed in the second opening and the step opening to each other; A method of manufacturing a semiconductor device.