JP2000331897A - Semiconductor wafer and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer and its manufacturing method by which breakage of the semiconductor wafer at the time of polishing of end faces of the semiconductor with a notch. SOLUTION: Before forming a notch 1 in a GaAs wafer 10 as semiconductor wafer, by making a plate member touch the orientation flat OF or the index flat IF of the GaAs wafer 10 and orienting it in a specified direction, the force applied to the GaAs wafer 10 is received by its sides and is distributed, breakage of the GaAs semiconductor wafer 10 is prevented and breakage of the semiconductor wafer with a notch at the time of its polishing can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor wafer and a method for manufacturing the same.

[0002]

2. Description of the Related Art GaAs wafers are widely used as substrates for light receiving elements, light emitting elements, high frequency elements and the like. In order to manufacture a semiconductor device by implanting ions or forming an epitaxial layer into these GaAs wafers, the manufacturing cost is lower when a large-diameter wafer is used as in the case of the Si wafer, in consideration of the manufacturing cost. Therefore, Ga
Currently, 4 inch (100 mm) diameter wafers are mainly used for As wafers, but 6 inch (150 mm) diameter wafers are beginning to be used to increase productivity. In the future, 6 inch diameter wafers will become the mainstream. Conceivable.

[0003] As the diameter of Si wafers increases,
Instead of forming an orientation flat and an index flat for specifying the directionality of the Si wafer on the Si wafer, a notched wafer in which a notch called a substantially V-shaped notch 1 is formed on the outer periphery of the Si wafer as shown in FIG. 2 has been used by device manufacturers.
The device maker applies thin pins (not shown) having a diameter of about 1 to 2 mm to the notch 1 to align the directions of the notched wafer 2.

FIG. 6 is a partially enlarged view showing the vicinity of a notch of a conventional semiconductor wafer.

[0005] Notch 1 shown in the figure, the angle theta _a is 89 °
It is formed in a substantially V shape in the range of up to 95 °. Distance L ₁ between the wafer outer peripheral portion and the notch tip 1.00
Is 1.25 mm, the radius of curvature R _a of the notch tip is minimal 0.9 mm, the maximum 2.3mm distance L ₂ is the outermost pin from the wafer outer peripheral portion, from the notch tip pin of the uppermost distance L ₃ between the external is minimal 3.05 mm.
The outer diameter of the pin insertion position (shown by a broken line) was 3 mm.

FIG. 7A is a plan view of a semiconductor wafer used in a conventional semiconductor wafer manufacturing method, and FIG. 7B is a side view of FIG. 7A.

The semiconductor wafer 2 shown in FIGS. 7A and 7B
The outer diameter phi _a of a 152 mm, the thickness t _a is 750μm
It is.

[0008] With the increase in diameter of GaAs wafers, Si
Like wafers, notched wafers are being used by device manufacturers. This is because, as the diameter of the wafer increases, the length of the orientation flat or the index flat increases, and the effective area of the wafer when diced into chips decreases. In addition, when the wafer is rotated in the process of manufacturing the element, as the diameter increases, the moment of inertia during rotation increases and the position shifts.

For this reason, the processing of a notched wafer is performed in the following order.

1) The surface of the grown semiconductor crystal is ground and processed into a cylindrical ingot (not shown).

2) A substantially V-shaped groove is formed on a side surface of the ingot in a specific direction (this groove becomes a temporary notch when a wafer is sliced).

3) The ingot is sliced by a slicer, a wire saw or the like into a disc-shaped wafer having a predetermined thickness.

4) The wafer 2 on which the temporary notch is formed is held on a rotatable wafer grinding stage (hereinafter referred to as “stage”) 3, and the stage 3 approaches the rotary grindstone 4 while the wafer 2 is rotating. Then, the end face of the outer peripheral portion of the wafer 2 is chamfered (see FIG. 8). After the end of the chamfering operation, the rotation of the stage 3 is stopped, the wafer 3 is separated from the rotating grindstone 4 by the stage 3, the notch grinding grindstone 5 is rotated instead of the rotating grindstone 4, and the stage 3 approaches the notch forming position. Then, a notch is formed (see FIG. 9).

5) After the formation of the notch is completed, the polished surface of the wafer 2 is mirror-finished using a polishing machine (not shown).

FIG. 8 is an explanatory diagram of the grinding of the outer peripheral portion of the semiconductor wafer, and FIG. 9 is an explanatory diagram of the notch grinding of the semiconductor wafer.

[0016]

When a notched wafer is processed, a single crystal semiconductor such as a Si wafer or a compound semiconductor wafer such as a GaAs wafer is processed in the above order.

However, the end face of the notched compound semiconductor wafer is easily damaged during the chamfering process in such an order. This is probably because the compound semiconductor wafer is more brittle in material than the Si wafer.

When the end face of the wafer is ground by an end face grinding machine, the wafer is fixed by applying thin pins to a temporary notch in order to align the direction of the wafer before grinding. As described above, the GaAs wafer may be cracked when fixed by applying pins, or cracked during grinding, and cannot be processed at a high yield unlike a Si wafer.

Each time the GaAs wafer breaks, Ga
As wafer fragments are scattered into the grinder, and the grinder must be temporarily stopped to remove the scattered matter, and thereafter the processing is troublesome and time-consuming.

[0020] The material of the pin for fixing the GaAs wafer so as not to be broken and the method of applying the pin have been devised, but there is a problem that the probability that the GaAs wafer is cracked is higher than that of the Si wafer.

It is an object of the present invention to solve the above-mentioned problems and to provide a semiconductor wafer capable of preventing damage to the semiconductor wafer at the time of grinding the end face of the notched semiconductor wafer, and a method of manufacturing the same.

[0022]

According to the present invention, there is provided a method of manufacturing a semiconductor wafer, comprising cutting a semiconductor single crystal and identifying an orientation of the wafer on an outer peripheral portion of the obtained disk-shaped semiconductor wafer. In the method for manufacturing a semiconductor wafer in which a notch for forming is formed by grinding, a semiconductor wafer having an orientation flat formed on an outer peripheral portion is prepared, and a plate-shaped member is applied to the orientation flat to align the semiconductor wafer in a specific direction. To form a notch.

According to the method of manufacturing a semiconductor wafer of the present invention, a semiconductor single crystal is cut, and a notch for identifying the orientation of the wafer is formed on an outer peripheral portion of the obtained disk-shaped semiconductor wafer by grinding. In the method, a semiconductor wafer having an orientation flat and an index flat formed on an outer peripheral portion is prepared, and a notch is formed after aligning the semiconductor wafer in a specific direction by applying a plate-shaped member to the orientation flat and the index flat. Things.

The semiconductor wafer of the present invention is a semiconductor wafer in which a notch for identifying the orientation of the wafer is formed at the outer periphery of a disk-shaped semiconductor wafer obtained by cutting a semiconductor single crystal. The notch is formed after the semiconductor wafer is aligned in a specific direction by applying a plate-shaped member to an orientation flat or an index flat formed in the portion.

According to the present invention, before forming a notch in a semiconductor wafer, a plate-shaped member is applied to an orientation flat or an index flat of the semiconductor wafer so as to be aligned in a specific direction, so that the force applied to the semiconductor wafer is reduced by the side. As a result, the semiconductor wafer, especially the compound semiconductor wafer, is prevented from being damaged, and the semiconductor wafer can be prevented from being damaged when the end face of the notched semiconductor wafer is ground.

[0026]

Embodiments of the present invention will be described below.

According to the method of manufacturing a semiconductor wafer of the present invention, when a notch for identifying the orientation of the wafer is formed on the obtained disc-shaped semiconductor wafer by cutting the semiconductor single crystal, an orientation flat ( Alternatively, a semiconductor wafer on which an index flat is formed is prepared, and a notch is formed after the semiconductor wafer is aligned in a specific direction by applying a plate-shaped member (or a rod-shaped member having a diameter of 3 mm or more) to an orientation flat (index flat). Is what you do.

A semiconductor wafer according to the present invention is a semiconductor wafer in which a notch for identifying the orientation of the wafer is formed on an outer peripheral portion of a disk-shaped semiconductor wafer obtained by cutting a semiconductor single crystal. A notch is formed after a semiconductor wafer is aligned in a specific direction by applying a plate-shaped member to an orientation flat or an index flat formed on an outer peripheral portion of the semiconductor wafer.

According to the present invention, before forming the notch in the semiconductor wafer, the plate member is applied to the orientation flat or the index flat of the semiconductor wafer and aligned in a specific direction so that the force applied to the semiconductor wafer is reduced. The semiconductor wafer is prevented from being damaged, and the semiconductor wafer is prevented from being damaged, and the semiconductor wafer can be prevented from being damaged when the end face of the notched semiconductor wafer is ground.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to numerical values, but the present invention is not limited thereto.

(Embodiment) FIG. 2A is a plan view of a semiconductor wafer having a temporary orientation flat and a temporary index flat formed on an outer peripheral portion, and FIG.
FIG. 2 is a side view of FIG.

GaAs as a semiconductor wafer shown in FIG.
A temporary orientation flat OF and a temporary index flat IF are formed on the wafer 10 in the (110) direction. The thickness t ₁ of the GaAs wafer 10 is, for example, 7
A 50 [mu] m, an outer diameter phi ₁ is about 152 mm. The temporary orientation flat OF length L _OF is 43mm
And the length L _IF of the provisional index flat _IF is 15
mm.

[0033] Such a GaAs wafer 10 is
Prepare 0 sheets.

A rotatable and parallel movable wafer grinding stage (hereinafter referred to as “stage”) 3, a parallel movable chamfering rotary grindstone (diameter of about 100 mm) 4, a parallel movable notch grinding rotary grindstone 5, And an NC shape grinder capable of NC control is prepared (see FIGS. 8 and 9).

This end face shape grinding machine uses GaAs before grinding.
If numerical data such as the outer diameter of the wafer 2 and the rotation reference position is set, the stage 3 is moved forward and backward (in the direction of arrow 6), and the rotating shaft of the rotary grindstone 4 is moved up and down (in the direction of arrow 7) for grinding. It has become.

The GaAs wafer 10 is placed on the stage 3, and a plate-like member (or 3 m in diameter) (not shown) is placed on the orientation flat OF or the index flat IF of the GaAs wafer 10 placed on the stage 3.
The GaAs wafer 10 may be aligned in a specific direction by applying a thick rod-shaped member of m or more.

After aligning the GaAs wafer 10 in a specific direction, the stage 3 of the end face shape grinding machine and the rotating grindstone 4 for chamfering are operated as shown in FIG. 8 to chamfer the GaAs wafer 10 (chamfering grinding). Peripheral speed of grinding wheel for use: 240
0 m / sec). GaAs wafer 1 for chamfering
The outer periphery is ground so that the diameter of 0 is also small.

After the chamfering is completed, the stage 3 and the notch grinding rotary grindstone 5 are operated as shown in FIG. 9 to form the notch 1 having the shape shown in FIG.
When formed on an As wafer (the peripheral speed of the grinding wheel for notch grinding: 1.8 m / sec), the GaAs wafer 11 shown in FIGS. 3A and 3B is obtained.

FIG. 3A is a plan view of the GaAs wafer after chamfering and notching, and FIG.
It is a side view of (a).

The GaAs wafer 11 has an outer diameter φ ₂ (15
0 mm) and a (100) wafer with a thickness t ₁ of 750 μm.

FIG. 4 shows the GaAs shown in FIGS. 3 (a) and 3 (b).
It is sectional drawing of the outer peripheral part end surface of s wafer.

The radius of curvature R of the end face of the outer peripheral portion of the GaAs wafer 11 shown in FIG. 4 is, for example, 300 μm, the inclination angle θ is 22 °, the thickness t ₁ is 750 μm, and the tip of the end face from the inclination start point. the distance L ₄ to is 430μm.

The 1,000 GaAs wafers 11
Among them, none of the GaAs wafers had cracks. After processing, these GaAs wafers 11 are lap-grinded on both sides, and then polished on both sides to be mirror-finished.

When the GaAs wafer 11 shown in FIGS. 3A and 3B is mirror-finished, a GaAs wafer 12 as shown in FIGS. 1A and 1B is obtained.

FIG. 1A is a plan view of a semiconductor wafer formed by the method of manufacturing a semiconductor wafer according to the present invention.
FIG. 1B is a side view of FIG.

FIG. 5 shows the GaAs shown in FIGS. 1 (a) and 1 (b).
It is sectional drawing of the outer peripheral part end surface of s wafer.

The radius of curvature R of the outer peripheral end face of the GaAs wafer 12 shown in FIG. 5 is 300 μm, and the inclination angle θ is 2 μm.
2 °, the thickness t ₂ is 675 μm, and the distance L ₅ from the inclination start point to the tip of the end surface is 337 μm.

The GaAs wafer 12 was not damaged by lapping or polishing. In the present embodiment, the case where the orientation flat OF and the index flat IF are formed on the outer peripheral portion has been described. However, the present invention is not limited to this, and only the orientation flat OF may be formed on the outer peripheral portion. Although the notch 1 is formed at the lowermost end in the drawing, it may be formed at another outer peripheral portion.

[0049] (Comparative Example) FIG. 7 (a), the thickness t _a of GaAs wafers (temporary notch is formed as a semiconductor wafer shown is at 750 [mu] m, an outer diameter phi _a is (b) 152 mm
1,000 (100) GaAs wafers) are prepared,
These GaAs wafer end face shape grinder, to form a notch in the shape as shown in FIG. 6, the outer diameter phi _b is 150mm
(100) wafer (shape is the same as that of FIGS. 3A and 3B).

Here, the cross-sectional shape of the outer peripheral end face was processed as shown in FIG.

At the time of processing the end face, the outer periphery is ground so that the diameter of the GaAs wafer becomes small. The grinding peripheral speed of the grinding wheel for chamfer grinding was set to 2400 m / sec as in the example, and the grinding peripheral speed of the grinding wheel for notch grinding was set to 1.8 m / sec.

Out of 1,000 GaAs wafers, 10 cracked GaAs wafers. These 10
Five of the GaAs wafers were broken starting from the notch. After processing these GaAs wafers,
Both sides were lap-ground and then both sides were polished and mirror-finished to obtain wafers having the shapes shown in FIGS. 1 (a), (b) and FIG. The number of damaged GaAs wafers in lapping and polishing was 20.

From the results of the example and the comparative example, it can be understood that the semiconductor wafer having the temporary orientation flat and the temporary index flat formed thereon can be processed with a higher yield by using the semiconductor wafer to process the notched wafer.

[0054]

In summary, according to the present invention, the following excellent effects are exhibited.

It is possible to provide a semiconductor wafer capable of preventing the semiconductor wafer from being damaged at the time of grinding the end face of the notched semiconductor wafer and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor wafer formed by a method of manufacturing a semiconductor wafer according to the present invention, and FIG. 1B is a side view of FIG.

FIG. 2A is a plan view of a semiconductor wafer having a temporary orientation flat and a temporary index flat formed on an outer peripheral portion, and FIG. 2B is a side view of FIG.

FIG. 3A shows GaAs after chamfering and notching.
It is a top view of s wafer, and (b) is a side view of (a).

FIG. 4 is a sectional view of an outer peripheral end face of the GaAs wafer shown in FIGS. 3 (a) and 3 (b).

FIG. 5 is a sectional view of an outer peripheral end face of the GaAs wafer shown in FIGS. 1 (a) and 1 (b).

FIG. 6 is a partially enlarged view of the vicinity of a notch of a conventional semiconductor wafer.

FIG. 7A is a plan view of a semiconductor wafer used in a conventional semiconductor wafer manufacturing method, and FIG. 7B is a side view of FIG.

FIG. 8 is an explanatory view of grinding an outer peripheral portion of a semiconductor wafer.

FIG. 9 is an explanatory diagram of notch grinding of a semiconductor wafer.

[Explanation of symbols]

 1 Notch 10 Semiconductor wafer (GaAs wafer) OF Orientation flat IF Index flat

Claims (3)

[Claims] In a method for manufacturing a semiconductor wafer, a semiconductor single crystal is cut, and a notch for identifying the orientation of the wafer is formed on an outer peripheral portion of the obtained disk-shaped semiconductor wafer by grinding. A method of manufacturing a semiconductor wafer, comprising: preparing a semiconductor wafer on which is formed, applying a plate-shaped member to the orientation flat, aligning the semiconductor wafer in a specific direction, and then forming the notch. 2. A method for manufacturing a semiconductor wafer in which a semiconductor single crystal is cut and a notch for identifying the orientation of the wafer is formed on an outer peripheral portion of the obtained disk-shaped semiconductor wafer by grinding. And preparing a semiconductor wafer on which an index flat is formed, applying the plate-shaped member to the orientation flat and the index flat, aligning the semiconductor wafer in a specific direction, and forming the notch. A method for manufacturing a semiconductor wafer. 3. A semiconductor wafer having a disk-shaped semiconductor wafer obtained by cutting a semiconductor single crystal and having a notch for identifying the orientation of the wafer formed on the outer periphery of the semiconductor wafer. A semiconductor wafer, wherein the notch is formed after the semiconductor wafer is aligned in a specific direction by applying a plate-shaped member to an orientation flat or an index flat.