JP2001167993A - Compound semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor wafer, capable of identifying the front and the rear thereof. SOLUTION: The surface roughness of a chamfered part 12 of the outer periphery of one surface 11 of the compound semiconductor wafer 10, with a notch formed with a notch 13 on the outer periphery, is different from that of the chamfered part 14 of the notch 13, and the surface roughness of a chamfered part 16 of the outer periphery of the other surface 15 is equal to that of the chamfered part 17 of the notch 13. Accordingly, when the wafer is irradiated with light, the glossiness of the part 12 of the outer periphery of the one surface 11 side of the wafer 10 and the part 17 of the notch 13 become different, and the glossiness of the part 16 of the outer periphery of the other surface 15 side and the part 17 of the notch 13 become equal. Therefore, the front and the rear of the wafer can be discriminated visually.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a compound semiconductor wafer.

[0002]

2. Description of the Related Art GaAs wafers are widely used as substrates for light receiving elements, light emitting elements, high frequency elements and the like.
In order to manufacture semiconductor devices by implanting ions or forming epitaxial layers on these GaAs wafers, considering the manufacturing cost, it is better to use a wafer with a larger diameter as in the case of Si wafers. Can be. For this reason, GaAs wafers are currently mainly 100 m
m (4 inch) diameter wafers are used,
mm (6 inch) diameter wafers have begun to be used,
It is believed that 50 mm diameter wafers will become mainstream.

[0003] As the diameter of Si wafers increases,
Instead of forming an orientation flat or index flat that specifies the direction of the wafer on the wafer,
As shown in FIGS. 2A and 2B, a substantially V
A notched wafer 2 having a notch 1 formed with a notch called a letter-shaped notch 1 has come to be used by a device maker.

FIG. 2A is a plan view of the compound semiconductor wafer, and FIG. 2B is an enlarged view of the vicinity of the notch of the compound semiconductor wafer shown in FIG. 2A.

In FIG. 1, reference numeral 3 denotes a pin having a diameter φ.
Is 3 mm. Notch depth Vh is 1.00 (1.
00 to 1.25) mm, P1 is 2.3 mm or less, P2 is 3.05 mm or more, the notch curvature radius Rv is 0.9 mm or more, and the notch angle θv is 90 ° (89 ° to 95 °).

[0006] With the increase in diameter of GaAs wafers, Si
As with wafers, notched wafers 2 are being used by device manufacturers. This is because, as the diameter of the wafer increases, the length of the orientation flat or index flat (not shown) increases correspondingly, and the area of the usable wafer decreases. In addition, when the wafer is rotated in the element manufacturing process, if the diameter increases, the position shifts because the moment of inertia during rotation increases.

The processing of such a notched wafer is performed in the following order.

1) The surface of the grown crystal is ground and processed into a cylindrical ingot.

2) A V-shaped groove is formed in a specific direction on the side surface of the ingot (this groove becomes a temporary notch when a wafer is sliced). 3) The ingot is predetermined using a slicer, a wire saw, or the like. Slice into wafers of thickness

[0010] 4) The wafer having the temporary notch formed thereon is chamfered at the notch portion and other end surfaces by a wafer end surface grinding machine (chamfering machine).

5) The chamfered wafer is polished, and the polished surface is mirror-finished.

Here, a general wafer edge grinding machine (chamfering machine) has two grinding wheels. One end of the grinding wheel is used for chamfering the entire peripheral surface of the wafer, and the other side is used for chamfering the notch. The surface width and chamfer shape (taper angle,
The R (R) shape can be adjusted by inputting numerical data because the end face grinding machine is an NC machine.

FIG. 3A is a partial sectional view of the grindstone, and FIG. 3B is a diagram showing a state in which a wafer is applied to the grindstone shown in FIG. 3A.

Chamfering whetstone 4 for grinding the end face of wafer 2
Has a shape in which a groove 5 is formed as shown in FIG. 3A, and the groove 5 has tapered portions 5a and 5b and R portions 5c and 5d.
It is composed of Diamond grains having a specific grain size are fixed to these portions.

As shown in FIG. 3B, the outer peripheral portion of the wafer 2 is chamfered by applying the end face of the outer peripheral portion of the wafer 2 to the groove 5 of the chamfering grindstone 4 and grinding. The surface roughness of the chamfer is determined by the grain size of the abrasive grains.

The upper end surface of the wafer 2 is applied to the upper tapered portion 5a of the groove of the grindstone 4, and the lower end surface of the wafer 2 is applied to the lower tapered portion 5b of the groove of the chamfering grindstone 4 for grinding. Beveled by The grinding of the notch portion 1 is different in that the diameter of the grinding wheel for grinding is considerably smaller than the diameter of the chamfering grindstone 4 for the outer periphery of the wafer, but the chamfering method and procedure are the same as those of the outer peripheral portion.

[0017]

When a notched wafer is processed, the processing is performed in the order described above, starting with the Si wafer. Here, the notched wafer 2 has exactly the same shape on the front surface and the back surface. Therefore, when it is necessary to distinguish between the front and back surfaces, care must be taken so that the front and back surfaces are not mistaken in each process. In the process up to chamfering, there is a method that enables identification of the front and back, such as marking one surface of the wafer 2 with a chemical, but if the surface is polished after chamfering, the mark disappears and the front and back cannot be distinguished, There is a problem that the possibility of mistaking the front and back of the wafer in a process after polishing is considerably increased.

Accordingly, an object of the present invention is to solve the above problems and to provide a compound semiconductor wafer capable of distinguishing between front and back.

[0019]

In order to achieve the above object, a compound semiconductor wafer according to the present invention is provided with a notch for identifying the orientation of the wafer at an outer peripheral portion of a wafer obtained by slicing a compound semiconductor single crystal. In the formed compound semiconductor wafer, the surface roughness of the chamfered portion at the outer peripheral portion of one surface and the surface roughness of the chamfered portion of the notch portion are different, and the surface roughness and the notch at the outer peripheral portion of the other surface are different. The surface roughness of the chamfered part is equal.

In addition to the above structure, the compound semiconductor wafer of the present invention is characterized in that the material of the compound semiconductor single crystal is GaAs, InP,
It is preferably InSb, InAs, or GaP.

According to the present invention, the surface roughness of the chamfered portion on the outer peripheral portion of one surface of the notched compound semiconductor wafer having a notch formed on the outer peripheral portion of the compound semiconductor wafer and the surface of the chamfered portion on the notch portion Since the surface roughness of the chamfered portion of the outer surface of the other surface is equal to the surface roughness of the chamfered portion of the notch, the gloss when illuminated is different and the front and back sides can be visually identified. Become.

[0022]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1A is a plan view showing one embodiment of the compound semiconductor wafer of the present invention, and FIG.
FIG. 3A is a sectional view taken along line AA of FIG.

The compound semiconductor wafer shown below (hereinafter "wafer")
That. ) Shows a notched wafer 10 having a surface roughness of a chamfered portion 12 on an outer peripheral portion of one surface 11 and a notch 13.
The surface roughness of the chamfered portion 14 of the notch 13 differs from the surface roughness of the chamfered portion 16 on the outer peripheral portion of the other surface 15.
Have the same surface roughness.

With such a structure, when the compound semiconductor wafer 10 is irradiated with light, the compound semiconductor wafer 10 according to the present invention has a chamfered portion 12 and a chamfered notch 13 on the outer surface on one side 11 of the compound semiconductor wafer 10. The gloss of the portion 14 is different, and the chamfered portion 16 and the notch 13 of the outer peripheral portion on the other surface 15 side are different.
Since the gloss of the chamfered portion 17 becomes equal, the front and back sides can be visually identified.

The compound semiconductor wafer 10 is made of GaAs, InP, InSb, InS
Preferably, it is As or GaP.

[0027]

The present invention will be described with reference to specific numerical values, but the present invention is not limited thereto.

(Example) In the (100) direction, (10) having a temporary notch, a thickness of 750 μm and a diameter of 152 mm
0) 1000 GaAs wafers are prepared, and these wafers are turned into a (100) direction wafer 100 having a diameter of 150 mm and a notch 13 having a shape shown in FIGS. Shaping was performed.

Here, the chamfers of the chamfered portions 12 and 16 on the outer peripheral portion are made such that one surface (upper surface in the drawing) 11 and the other surface (lower surface) 15 of the wafer 10 have a grain size of # 1000. Chamfered using a whetstone. The chamfering of the notch 13 was performed using a notch chamfering grindstone having a grain size of # 3000 on the upper side of the groove and a grain size of # 1000 on the lower side of the groove. That is, the chamfered portion 14 of the notch 13 is chamfered with a grindstone having a grain size of # 3000, and the notch 1
The chamfer 17 of No. 3 is chamfered with a grindstone of the same grain size # 1000 as the chamfers 12 and 16 on the outer peripheral portion.

These 1000 wafers 10 were sent to a polishing process after chamfering and polished, but there was no misunderstanding of the front and back of the wafers 10 in the subsequent processes. This is because the surface roughness of the chamfered portion 14 of the notch 13 on the front side (11th surface side) of the wafer 10 is different from the surface roughness of the chamfered portions 12 and 16 on the outer peripheral portion, so that the presence or absence of gloss can be visually confirmed. It is.

It should be noted that, even after the surface roughness of the notch 13 and the surface roughness of the chamfered portions 12 and 16 on the outer peripheral portion were changed after the polishing step, the wafer was not damaged even if the surface width was changed. .

(Comparative Example) (100) having a thickness of 750 μm and a diameter of 152 mm with a temporary notch in the (100) direction.
1,000 GaAs wafers were prepared, and these wafers were shaped into a (100) wafer having a diameter of 150 mm with a notch having a shape shown in FIGS. 1A and 1B by an end face shape grinder.

Here, the surface roughness of the chamfered portion is set to the same roughness of # 1000 between the outer peripheral portion of the wafer and the notch portion.
Both the chamfering grindstone and the notch grindstone have a grain size of # 10 so that both the chamfering grindstone and the notch grindstone have a grain size of # 1000.
00 whetstone was used. These 1000 wafers
Polishing was performed after chamfering, but in the subsequent steps, 12 misplaced front and back wafers occurred.

In the above, by making the roughness of one surface of the notch portion of the notched wafer different from the surface roughness of the chamfered portion on the outer periphery of the wafer, it is easy to identify the front and back of the wafer, and the front and back of the wafer in wafer manufacturing can be easily obtained. Management can be performed reliably.

[0035]

In summary, according to the present invention, the following excellent effects are exhibited.

It is possible to provide a compound semiconductor wafer that can be distinguished from the front and back with a notched wafer.

[Brief description of the drawings]

FIG. 1A is a plan view showing an embodiment of a compound semiconductor wafer of the present invention, and FIG. 1B is a cross-sectional view taken along line AA of FIG.

FIG. 2A is a plan view of a compound semiconductor wafer,
(B) is an enlarged view near the notch of the compound semiconductor wafer shown in (a).

3A is a partial cross-sectional view of a grindstone, and FIG. 3B is a diagram illustrating a state where a wafer is applied to the grindstone illustrated in FIG.

[Explanation of symbols]

 Reference Signs List 10 compound semiconductor wafer (wafer) 11 one surface 12, 14, 16, 17 chamfered portion 13 notch 15 other surface

Claims (2)

[Claims] 1. A compound semiconductor wafer in which a notch for identifying the orientation of the wafer is formed on an outer peripheral portion of a wafer obtained by slicing a compound semiconductor single crystal. A compound semiconductor, wherein the surface roughness is different from the surface roughness of the chamfered portion of the notch portion, and the surface roughness of the chamfered portion of the outer surface of the other surface is equal to the surface roughness of the chamfered portion of the notch portion. Wafer. 2. The material of the compound semiconductor single crystal is GaAs.
The compound semiconductor wafer according to claim 1, wherein the compound semiconductor wafer is s, InP, InSb, InAs, or GaP.