JP2000326215A - Chemical machine grinding device and manufacture of semiconductor integrated circuit device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To average the load to be added to a semiconductor wafer with respect to a chemical machine grinding device provided with a pressure head comprising a retainer ring having cuts inside thereof, by forming the retainer ring with a lower part retaining the semiconductor wafer and an upper part provided with cuts. SOLUTION: A semiconductor wafer 1 as a material to be ground is retained by a pressure head 2, a wafer surface is ground by an abrasive pad 4 attached to a rotary grinding surface plate 3, and the slurry 7 is supplied from a supply nozzle 6 during the grinding. A surface of the abrasive pad 4 is cut by a dresser 5 to reproduce its performance. The pressure head consists of a wafer carrier 8, a retainer ring 9 and an elastic thin film (PET sheet) 10, and the retainer ring 9 consists of a lower part 9a mounted for preventing the removement of the semiconductor wafer 1 during the grinding, and an upper part 9a provided with cuts capable of receiving the bending of the PET sheet 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a chemical mechanical polishing (Chemical Mechanical Polishing) method for flattening irregularities on a surface of an insulating film or a metal film deposited on a semiconductor wafer. Polishing; CM
P) This relates to technology that is effective when applied to the process.

[0002]

2. Description of the Related Art Pressing C while holding a semiconductor wafer
Various structures have been proposed for the pressure head of the MP device. Most commonly, a wafer chuck for holding a semiconductor wafer, a retainer ring for preventing the semiconductor wafer from coming off during polishing, a backing film for maintaining a surface reference, and a housing for applying pressure while holding these. From the elements, the pressure head is mainly composed.

Further, there are various methods of applying a load to the semiconductor wafer, and one of them is an air bag pressurizing method in which the pressure is additionally adjusted from the back surface of the semiconductor wafer in the housing by air. In this method, the shape can be minutely controlled by partially changing the amount of air supplied to the back surface of the semiconductor wafer, and uniform processing over the entire surface of the semiconductor wafer can be achieved. At present, a method of pressurizing a semiconductor wafer with air via an elastic thin film (for example, a PET (polyethylene terephthalate) sheet) has been put to practical use. In this case, the elastic thin film plays a role as a wafer chuck.

[0004] Note that Toshio Dohi, Toshio Kawanishi, and Takeo Nakagawa, published on July 15, 1998, "Semiconductor Flattening CMP Technology" issued by the Industrial Research Institute of Japan, p. A conceptual diagram of a back pressure method is described.

[0005]

By the way, in CMP, generally, a runoff occurs on a semiconductor wafer. As one means of minimizing this weeping phenomenon and ensuring uniformity of the processed surface, a retainer ring arranged on the outer periphery of a semiconductor wafer is used. The retainer ring is provided to prevent the semiconductor wafer from coming off during processing.However, if the retainer ring arranged on the outer periphery of the semiconductor wafer is treated as a processing dummy, it is possible to reduce the runout. it can.

However, the present inventors have studied and found that when an air load is applied to the semiconductor wafer, the end of the elastic thin film on the retainer ring bends and a concentrated load is generated at the end of the semiconductor wafer. became. It is considered that the concentrated load causes the air load on the semiconductor wafer to be non-uniform, and the in-plane uniformity of the polishing amount to be reduced.

An object of the present invention is to provide a technique capable of improving the uniformity of a polishing amount in a semiconductor wafer surface by averaging a load applied to the semiconductor wafer in the CMP technique.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The chemical mechanical polishing apparatus of the present invention has a pressure head provided with a retainer ring in which a cut is formed inside, and the retainer ring has a lower portion for holding a semiconductor wafer and the cut notch. And the upper part formed.

(2) In the chemical mechanical polishing apparatus according to the present invention, in the pressure head according to the above (1), the thickness of the lower portion of the retainer ring is substantially the same as the thickness of the semiconductor wafer.

(3) In the chemical mechanical polishing apparatus according to the present invention, in the pressure head according to the above (1), the thickness of the upper portion of the retainer ring is set to about 1 mm or less.

(4) In the chemical mechanical polishing apparatus according to the present invention, in the pressure head according to the above (1), a cross section of an upper portion of the retainer ring is rectangular, at least a part is oblique, or at least a part is oblique. It has an arc shape.

(5) In the chemical mechanical polishing apparatus according to the present invention, in the pressure head according to the above (1), the deflection of the elastic thin film is received at at least two points of the retainer ring.

(6) In the chemical mechanical polishing apparatus of the present invention, in the pressure head according to the above (1), the width of the cut is 10 mm or more.

(7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor wafer is held and pressed by using a pressure head having a retainer ring having a cut formed inside, and the semiconductor wafer is formed on the semiconductor wafer. This is for polishing the surface of the film.

According to the above means, when an air load is applied to the semiconductor wafer, the concentrated load due to the bending of the elastic thin film can be received by the retainer ring, the air load on the semiconductor wafer can be averaged, and the semiconductor wafer can be averaged. The uniformity of the polishing amount in the wafer surface can be improved.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a CM according to an embodiment of the present invention.
FIG. 2 shows a schematic diagram of a P device, and FIG. 2 shows a schematic diagram of a cross section of a retainer ring provided in a pressure head of the CMP device. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. 1 is a semiconductor wafer, 2 is a pressure head, 3 is a polishing platen, 4 is a polishing pad, 5 is a dresser, 6
Is a supply nozzle, 7 is a slurry, 8 is a wafer carrier, 9 is a retainer ring, 10 is a PET sheet, 11 is a hole,
2 is an air supply and vacuum line.

A semiconductor wafer 1, which is a material to be polished, is held by a pressurizing edge 2, and the surface of the semiconductor wafer 1 is polished by a polishing pad 4 attached to a rotating polishing platen 3. The pressurizing head 2 can pressurize the semiconductor wafer 1 and has a rotation function. The surface of the polishing pad 4 is cut using a dresser 5 to regenerate its function. During polishing, a slurry 7 is supplied from a supply nozzle 6 provided above the polishing pad 4.

The pressure head 2 includes a wafer carrier 8 for accommodating the semiconductor wafer 1, a retainer ring 9 provided on the outer periphery of a region where the semiconductor wafer 1 is installed, and an elastic thin film.
For example, it is constituted by a PET sheet 10 and is made of PE
The semiconductor wafer 1 is additionally pressurized with air from the back surface via the T sheet 10. The PET sheet 10 also functions as a wafer chuck, and has holes 11 for adsorbing the semiconductor wafer 1. An air supply and a vacuum line 12 are provided leading to the wafer carrier 8.

Further, the retainer ring 9 has a lower portion 9a provided mainly to prevent the semiconductor wafer 1 from coming off during polishing, and an upper portion 9b provided mainly with a notch capable of receiving the deflection of the PET sheet 10. And has a stepped shape in which the cut is provided inside.

The thickness of the lower portion 9a is substantially the same as the thickness of the semiconductor wafer 1. If the thickness of the lower portion 9a is too thin, a concentrated load is applied to the end surface of the semiconductor wafer 1, and if it is too thick, a concentrated load is applied to the central surface of the semiconductor wafer 1, and the load cannot be averaged. On the other hand, upper 9b
The thickness depends on the thickness of the PET sheet 10 and cannot be unconditionally determined, but is typically set to about 1 mm or less.

FIG. 2A is an enlarged sectional view of the retainer ring 9 shown in FIG. In the case where the cross section of the retainer ring 9 is step-shaped, an end point A on the lower portion 9a near the semiconductor wafer 1 and an end portion B on the upper portion 9b near the semiconductor wafer 1 are provided.
The deflection of the PET sheet 10 can be received on the surface passing through the point. The horizontal distance L from the point A to the point B depends on the thickness of the PET sheet 10 and cannot be unconditionally determined. For example, when the thickness of the PET sheet 10 is 100 μm, it is about 10 mm or more, and when the thickness is 250 μm, It is set to about 20 mm or more.

The cross-sectional shape of the upper portion 9b may be any shape as long as it can receive the deflection of the PET sheet 10. For example, a part of the cross-section is oblique (FIG. 2B), or a part thereof is It may have an arc shape (FIG. 2C).

As described above, according to the present embodiment, when an air load is applied to the semiconductor wafer 1, the PET sheet 10
By receiving the concentrated load due to the deflection by the retainer ring 9, the air load on the semiconductor wafer 1 can be averaged, and the uniformity of the polishing amount on the surface of the semiconductor wafer 1 is improved.

Next, a bipolar CMOS (Complementary Metal Oxide) using the CMP apparatus of the present embodiment is described.
FIG. 3 shows a method for manufacturing a multilayer wiring of a semiconductor device.
This will be briefly described with reference to FIGS. In the figure, Q ₁ is an npn-type bipolar transistor, and Q ₂ is a p-channel MISFET (Metal Insulator Semiconductor Field).
Effect Transistor), Q ₃ is an n-channel type MISFE
T.

First, as shown in FIG.
Semiconductor substrate 2 made of p-type silicon single crystal of about m
1, an n ⁺ -type buried layer 22 and a p ⁺ -type buried layer 23 are formed. Next, after forming an n-type epitaxial layer on the semiconductor substrate 21, an n-type well 24 is formed on the n ⁺ -type buried layer 22 and a p-type well 25 is formed on the p ⁺ -type buried layer 23. .

Next, the n-type well 24 and the p-type well 2
5, an isolation insulating film 26 is formed. At this time, in order to prevent the operation of the parasitic n-channel MISFET,
A p-type channel stopper region 27 is formed below the element isolation insulating film 26 in the p-type well 25.

Next, as shown in FIG. 4, n-type well region forming the npn type bipolar transistor Q ₁ 24
After forming the n-type semiconductor region serving as a collector taking-out region 28 in a part, p-type impurity into the n-type well 24 in the region for forming the p-channel type MISFET Q _2, for example, boron (B) is ion-implanted sills The value voltage control layer 29 is formed. Further, an n-type impurity, for example, phosphorus (P) is added to the p-type well 25 in a region where the n-channel type MISFET Q ₃ is formed.
Is ion-implanted to form the threshold voltage control layer 30.

Next, as shown in FIG.
After forming a gate insulating film 31 having a thickness of about 8 nm on each surface of the p-type well 25 and the
A polycrystalline silicon film (not shown) of about 200 nm is deposited. Then, p-channel-type p-type impurity MISFET Q ₂ to the polycrystalline silicon film in the region for forming, for example the B ions are implanted, n-type impurity into the polycrystalline silicon film in the region for forming the n-channel type MISFET Q _3, for example, P Is ion-implanted. Next, after depositing a silicon nitride film 32 on the polycrystalline silicon film,
Then, the p-type gate electrode 33a and the n-type gate electrode 33b are formed by sequentially etching the polycrystalline silicon film.

Next, p is set using the gate electrode 33a as a mask.
P-type impurity such as B is ion-implanted into the n-type well 24 in the region for forming a channel type MISFET Q _2, p constituting the source, a portion of the drain ^- -type semiconductor region 34. Further, n-type impurities into the p-type well 25 in the region for forming the n-channel type MISFET Q ₃ the gate electrode 33b as a mask, arsenic (As) is ion-implanted, forming a source, a portion of the drain n ^- -type semiconductor An area 35 is formed.

Next, as shown in FIG.
The silicon nitride film deposited thereon is processed by anisotropic etching to form sidewall spacers 36 made of the silicon nitride film on the side walls of the gate electrodes 33a and 33b.
Next, the gate electrode 33a and the sidewall spacer 3
P-type impurity such as B ions are implanted and 6 to n-type well 24 in the region for forming the p-channel type MISFET Q ₂ as a mask, forming a p ⁺ -type semiconductor region 37 constituting the source, the other part of the drain I do. In addition, the gate electrode 3
P-type impurity such as P is ion-implanted 3b and the sidewall spacers 36 on the p-type well 25 in the region for forming the n-channel type MISFET Q ₃ as a mask, source, n ⁺ -type semiconductor constituting the other part of the drain Area 3
8 is formed. Further, p-type impurity into the n-type well 24 in the region for forming the npn type bipolar transistors Q _1,
For example, B is ion-implanted to form the base region 39 and the external base region 40.

Next, as shown in FIG.
After an insulating film 41 made of, for example, a silicon oxide film is deposited thereon, a contact hole 42 is formed by opening an insulating film in the same layer as the insulating film 41 and the gate insulating film 31 on the base region 39. Next, after depositing a polycrystalline silicon film on the semiconductor substrate 21, an n-type impurity, for example, As is ion-implanted into the polycrystalline silicon film, and the n-type impurity is diffused into the base region 39 by heat treatment to form an emitter region 43. To form Next, the polycrystalline silicon film is etched to form an emitter extraction electrode 44.

Next, after a first interlayer insulating film 45 is formed on the insulating film 41, the first interlayer insulating film 45 and the insulating film 41 are formed.
Then, a contact hole 46 is formed in the insulating film in the same layer as the gate insulating film 31, and then a metal film deposited on the first interlayer insulating film 45 is etched to form a first layer wiring 47.

Next, as shown in FIG.
The second interlayer insulating film 48 formed in the upper layer
9, a metal film is formed on the second interlayer insulating film 48,
For example, the tungsten film 50 is formed by chemical vapor deposition (Chemical
Vapor deposition (CVD) is deposited.

Next, the surface of the tungsten film 50 is polished using the CMP apparatus shown in FIG. 1 which is the present embodiment. First, after the semiconductor wafer 1 is stored in the wafer carrier 8, the wafer carrier 8 is brought into contact with the polishing pad 4. In this state, the semiconductor wafer 1 is rotated and pressurized and polished while dropping the slurry 7 from the supply nozzle 6, so that the surface is flattened and embedded in the through hole 49 as shown in FIG. Tungsten film 5
A plug 51 made of zero is formed. At this time, since the concentrated load due to the deflection of the PET sheet 10 can be received by the retainer ring 9, the air load on the semiconductor wafer 1 can be averaged.

Next, as shown in FIG.
The second layer wiring 52 is formed by etching a metal film, for example, an aluminum film deposited on the first layer 52. Thereafter, although not shown, a wiring above the second-layer wiring 52 is formed via an interlayer insulating film, thereby completing a bipolar CMOS device. Note that the CMP apparatus shown in FIG. 1 may be used for forming plugs provided to connect upper and lower wirings, or for planarizing the surface of upper wirings.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in this embodiment, the bipolar C
Although the description has been given of the case where the present invention is applied to a method of manufacturing a MOS device, the present invention is applicable to a method of manufacturing any semiconductor integrated circuit device using a CMP technique.

[0040]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, in the CMP technique, the air load on the semiconductor wafer can be averaged, and the uniformity of the polishing amount on the semiconductor wafer can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a CMP apparatus according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of a retainer ring provided in the CMP apparatus according to one embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a bipolar CMOS device using a CMP apparatus according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Pressure head 3 Polishing platen 4 Polishing pad 5 Dresser 6 Supply nozzle 7 Slurry 8 Wafer carrier 9 Retainer ring 9a Lower part 9b Upper part 10 PET sheet 11 Vacancy 12 Air supply and vacuum pipe 21 Semiconductor substrate 22 n ⁺ type Buried layer 23 p ⁺ -type buried layer 24 n-type well 25 p-type well 26 isolation insulating film 27 channel stopper region 28 collector lead-out region 29 threshold voltage control layer 30 threshold voltage control layer 31 gate insulating film 32 nitride Silicon film 33 a Gate electrode 33 b Gate electrode 34 p ⁻ type semiconductor region 35 n ⁻ type semiconductor region 36 sidewall spacer 37 p ⁺ type semiconductor region 38 n ⁺ type semiconductor region 39 base region 40 external base region 41 insulating film 42 contact hole 43 Emitter area 44 Emitter extraction electrode 45 First interlayer insulating film 46 Contact hole 47 First layer wiring 48 Second interlayer insulating film 49 Through hole 50 Tungsten film 51 Plug 52 Second layer wiring

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yukio Takada 3-16-0 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center 3C058 AA07 AA09 AA12 AB04 BA05 BB04 BC02 CB01 CB10 DA12 DA17

Claims (7)

[Claims] 1. A pressure head having a retainer ring having a cut formed therein, wherein the retainer ring includes a lower portion for holding a semiconductor wafer and an upper portion formed with the cut. A chemical mechanical polishing apparatus characterized in that: 2. The chemical mechanical polishing apparatus according to claim 1, wherein a thickness of a lower portion of said retainer ring is substantially equal to a thickness of a semiconductor wafer to be held. 3. The chemical mechanical polishing apparatus according to claim 1, wherein a thickness of an upper portion of the retainer ring is about 1 mm or less. 4. The chemical mechanical polishing apparatus according to claim 1, wherein a cross section of an upper portion of the retainer ring is rectangular, at least a part is oblique, or at least a part is an arc. Mechanical polishing equipment. 5. The chemical mechanical polishing apparatus according to claim 1, wherein a deflection of the elastic thin film is received at at least two points of the retainer ring. 6. The chemical mechanical polishing apparatus according to claim 1, wherein the width of the cut is about 10 mm or more. 7. A semiconductor wafer is held by using a pressure head having a retainer ring having a cut formed inside.
A method for manufacturing a semiconductor integrated circuit device, comprising applying pressure and polishing the surface of a film formed on the semiconductor wafer.