JP2000307852A - Image reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image reader which adjusts the input timing of a clock highly accurately without changing hardware, in the case of changing image sensors and the input timing of a drive (sampling) clock in an ADC that performs A/D conversion of its image output. SOLUTION: The phase of a driver clock is adjusted by setting adjustment data from a CPU 101 to the register of a timing circuit 112, which outputs an ADCLK for sampling to ADCs (R, G and B) 119 to 121, outputs an ICLK and a three-line CCD 111 to an image processing system and outputs a drive clock to an analog processing system, etc. White reference is used in an adjustment operation mode, a digital value detection circuit 122 is served also as a shading correction circuit and a memory detects outputs of the ADCs 119 to 121 of each phase obtained, by shifting an image clock by a reciprocal of the integral multiples, and the input timing of the clock is adjusted by evaluating the value, selecting an optimum phase and setting it as adjustment data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus provided in a scanner, a digital copying machine, a digital color copying machine, a facsimile, a color facsimile, and the like, and more particularly, to a photoelectric conversion means (line) for reading an original image. The present invention relates to a photoelectric conversion unit and a phase adjustment technique of a drive (sampling) clock of the A / D conversion unit in an image reading apparatus having an A / D conversion unit that samples an analog signal output from an image sensor and converts the analog signal into a digital signal.

[0002]

2. Description of the Related Art Conventionally, in a scanner, a digital copying machine, or the like, photoelectric reading has been performed to convert a document image into data. CC as the photoelectric conversion means used for photoelectric reading
A device that detects an analog image signal by scanning a line of a converted pixel line like a D line sensor is employed. In order to extract a good analog signal from such a photoelectric conversion means (CCD), it is necessary to provide a drive clock with an appropriate phase. In addition, when the necessary adjustment is made to the phase of the drive clock of the photoelectric conversion means, this also affects the drive clock in the next-stage analog processing circuit that processes the detected image signal. In addition, the output delay time of the analog signal from the photoelectric conversion unit depends on the driving clock frequency, the output voltage level, and the like. Therefore, in order to perform sample and hold at an appropriate output position, it is necessary to perform actual device evaluation. An A / D converter (ADC) is used to digitize the analog signal after the actual evaluation, but it is necessary to generate a sampling clock of the analog image signal at an appropriate position in the image signal period. As means for generating a drive clock to be applied to such image data processing means, a timing LSI has been conventionally used. However, LS
As a problem of I-ization, complete design specifications are required in the early stage of LSI development, and long-term development of LSI requires a long time for commercialization.

[0003]

Accordingly, when it is necessary to slightly delay or advance the timing of the driving clock in the latter half of the product development, it is necessary to use an LSI to prevent the development from being prolonged. At the final stage of the manufacturing process, a proposal has been made to make it possible to deal with this by making a hardware change such as adding a delay line, but this has been very difficult. The present invention has been made in view of such problems of the related art, and has as its object to sample an analog signal output from a photoelectric conversion unit (line image sensor) for reading a document image and convert the analog signal into a digital signal. Photoelectric conversion means and A / D in image reading apparatus having A / D conversion means
When it is necessary to change the timing of the drive (sampling) clock of the conversion means, it is possible to drive the phase delay state and the phase advance state with high accuracy without changing hardware. An object of the present invention is to provide an image reading apparatus provided with a (sampling) clock phase adjusting means.

[0004]

According to a first aspect of the present invention, there is provided a line image sensor for reading an image, A / D conversion means for converting an analog image signal output from the line image sensor into digital image data, An image reading apparatus comprising: a drive clock generating unit for generating respective drive clocks for operating a line image sensor and an A / D conversion unit; and a control unit for controlling operations of the line image sensor and the A / D conversion unit. The means adjusts the output timing of the drive clock by setting phase adjustment data to the drive clock generation means via a data bus.

According to a second aspect of the present invention, in the image reading apparatus according to the first aspect, the image reading apparatus has digital data detection means for detecting digital image data from the A / D conversion means, and the control means Generates phase adjustment data based on the detection result of the digital data detection means.

According to a third aspect of the present invention, in the image reading device according to the first or second aspect, the image reading device detects an output difference between the ODD and EVEN image signals obtained by the sub-scanning of the line image sensor. ODD and E after correction
Further comprising analog processing means for adjusting the gain so as to give a constant DC level offset between the VEN signals,
The output of the analog processing means is input to the A / D conversion means.

According to a fourth aspect of the present invention, in the image reading apparatus according to any one of the first to third aspects, the step of adjusting the phase adjustment data is set to a length equal to an integral number of a cycle of the pixel clock. It is a feature.

According to a fifth aspect of the present invention, in the image reading device according to any one of the second to fourth aspects, the adjustment width of the phase adjustment data is set to a length corresponding to one cycle of the pixel clock. Things.

According to a sixth aspect of the present invention, in the image reading device according to any one of the second to fifth aspects, the image reading device has a shading correction means at a stage subsequent to the A / D conversion means, and The detection means is characterized in that a memory holding the detection data is also used as a memory of the shading correction means.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described based on the following embodiments shown in the accompanying drawings. First, an outline of a digital color copier capable of suitably implementing the image reading apparatus of the present invention will be described. FIG. 1 is a diagram showing an outline of the overall configuration of the digital color copying machine of the present embodiment. This digital color copying machine is roughly divided into a color image reading device and a color image recording device. The color image reading device includes an image reading unit (scanner) 2, an image processing unit 3
On the other hand, the color image recording apparatus has an image writing unit 4, a drum unit 8, a developing unit 10, an intermediate transfer unit 9, a paper feeding unit 11, a fixing unit 12, and a copying machine mechanism unit 6. A system control unit 1, a working unit 5, and an image display unit 7 are provided in order to perform control operations common to both reading and recording apparatuses.

The outline of the operation when color copying is performed by the digital color copying machine of the present embodiment is as follows. The image reading unit 2 scans a document illuminated by illumination light from a light source while sub-scanning the document. The reflected light is detected by a three-line CCD sensor to read an image, and the image data is sent to the image processing unit 3. The image processing unit 3 sends to the image writing unit 4 image data that has been subjected to image processing such as scanner γ correction, color conversion, main scanning magnification, image separation, processing, area processing, and gradation correction processing. The image writing unit 4 drives an LD (laser diode) by performing modulation according to the image data. In the drum unit 8, an electrostatic latent image is written by a laser beam from the LD onto a uniformly charged rotating photosensitive drum, and the developing unit 10 attaches toner to make the image visible. The image formed on the photosensitive drum is transferred to the intermediate transfer unit 9.
Is re-transferred onto the transfer belt. 4 colors for full color copy (Black: Bk, Cyan: C, Mg) on the intermediate transfer belt
toner: M, Yellow: Y) are sequentially superimposed. In the case of full-color copying, transfer paper is fed from the paper feeding unit 11 at the time when the image forming / transferring process of four colors of Bk, C, M, and Y is completed, and the paper is transferred. The toner is transferred to the transfer paper from the intermediate transfer belt at the same time in four colors. The transfer paper to which the toner has been transferred is sent to the fixing unit 12 via the conveyance unit, and is thermally fixed by the fixing roller and the pressure roller, and is discharged.

When performing the above-described copy operation, copy conditions such as a copy mode set by a user's selection are input by the operation unit 5. The operation mode to be executed in accordance with the copy conditions such as the set copy mode is notified to the system control unit 1, and the system control unit 1 performs a control process for executing the set copy mode. At this time, the system control unit 1 issues a control instruction to units such as the image reading unit 2, the image processing unit 3, the image writing unit 4, and the image display unit 7. FIG. 2 is a diagram illustrating an example of the operation panel of the operation unit 5. As shown in FIG. 2, the operation panel of the operation unit 5 has ten keys 4
1. Mode clear / preheat key 42, interrupt key 43,
Image quality adjustment key 44, program key 45, print start key 46, clear / stop key 47, area processing key 48, brightness adjustment knob 49, touch panel key (on LCD panel 26 in FIG. 3 described later) 50, initial setting key 5
1 is provided.

The ten keys 41 are used to input numerical values such as the number of copies. The mode clear / preheat key 42 is used to cancel the set mode and return to the initial setting, or to set the preheating state by pressing continuously for a certain period of time or more. The interrupt key 43 is used to interrupt during copying and to copy another document. The image quality adjustment key 44 is used to adjust the image quality. The program key 45 is used to register or call a frequently used mode. The print start key 46 is a key for starting copying.
The clear / stop key 47 is used when clearing the input numerical value or when interrupting copying during copying. The area processing key 48 is used to execute a mode such as area processing / editing on the image display unit (display editor) 7. Brightness adjustment knob 49 is LCD
The brightness of the screen of the panel (see FIG. 3 described later) is adjusted. Further, the touch panel key 50 sets a key area in the same range as the range of various keys displayed on the LCD panel, and when the touch panel detects a press within the set range, processing of the set key is performed. I do. The initial setting key 51 is pressed when the user selects each initial setting.

To display an image read from the image reading unit 2 on the image display unit 7 (FIG. 1), the image reading unit 2 starts reading a document image in accordance with a control instruction from the system control unit 1. , For the image signal from the image reading unit 2,
After performing image processing suitable for display on the image display device in the image processing unit 3, the image data of the document is output to an image display device such as an LCD panel. FIG. 3 is a functional block diagram illustrating a circuit configuration of the image display unit 7.
As shown in FIG. 3, the image display unit 7 is connected to the system control unit 1 via a command line and to the image processing unit 3 via a data line.
IFO (line buffer) 21, DRAM (image data memory) 22, CPU 23, VRAM (video memory)
24, LCDC (LCD controller) 25, LCD
(Liquid crystal panel) 26, ROM 27, SRAM 28, serial communication driver 29, image data signal buffer (driver / receiver) 30, and keyboard 31.

The image data output from the image processing unit 3 is transmitted via the FIFO 21 of the image display unit 7 to
The image data is stored in the DRAM 22 for storing image data by a DMA controller built in the CPU 23. Since the image data control signal is sent to the image display unit 7 together with the image data, it is possible to capture only the effective image area. The valid image data stored in the DRAM 22 is DMA-transferred to the VRAM 24 by the CPU 23. At this time, it is also possible for the CPU 23 to transfer an arbitrary portion of the image data in the DRAM 22 and to perform processing such as enlargement, reduction, thinning, and the like. The image data transferred to the VRAM 24 is stored in an LCDC (LCD controller) 2.
5 is displayed on the LCD panel 26.

FIG. 4 is a view showing one embodiment of the LCD panel of the image display unit 7 shown in FIG. The image display unit 7 displays an image on the LCD panel 26. Also,
A display editor for designating an editing / processing area / setting a mode on the display screen may also be used. 4 correspond to the keyboard 31 in the functional block diagram of FIG. Important parts for the image reading apparatus of the present invention are a reading key and a brightness adjustment key, and the reading key starts reading a document,
A key for displaying the entire read image on a display, and a brightness adjustment key is a key for adjusting the brightness of the display.

FIG. 5 shows an example of a screen displayed on the LCD panel 26. As shown in FIG. 5, on the LCD screen, a color mode, an automatic density, a manual density, an image quality mode (automatic image separation), an automatic paper selection, a paper tray, a paper automatic magnification, a magnification (actual magnification), a sort, There is a mode selection display such as stacking, and a sub-screen selection display such as create, color processing, double-sided, and scaling is also provided. Further, the LCD panel 26 is used as a touch panel, and keys having the same size as the size of each display unit are set. Some keys can be displayed on the screen by depressing the keys.
FIG. 6 shows an example of screen development by pressing the scaling key on FIG. When the scaling key is pressed, the scaling setting screen is scrolled up from the bottom of the screen. A key ← for a fixed magnification (magnification mode in which a magnification is set in advance) is set on the magnification setting screen. For example, when the touch panel key of the 71% portion is pressed, a scaling ratio of 71% is selected. Further, on this screen, a zoom key, a dimensional zoom key, and an independent zoom / enlarge continuous shooting key are set on the left side of the screen in order to select a zoom mode other than the standard zoom mode.

The detection circuit of the above touch panel and its operation will be described. FIG. 7 is a diagram illustrating an example of a configuration of the touch panel detection circuit. FIG. 8 shows a setting state of the potentials of the X and Y electrodes of the touch panel in the detection circuit of FIG. As shown in FIG. 7, the touch panel detection circuit includes a touch panel 71, a controller 72, an A / D converter 73, and an operation switching circuit. The controller 72 sets the detection terminal to the high state, and sets the touch panel 71
The potentials X1, X2, Yl, and Y2 of the respective electrodes are set as shown in FIG. The Yl and Y2 circuits are pulled up by resistors, so when the touch panel 71 is OFF, Yl is + 5v and ON
In the case of, it becomes 0v. Therefore, the ON / OFF state is confirmed from the output of the A / D converter 73. Controller 72
Switches to the measurement mode when the ON state of the touch panel 71 is detected. In the X direction, X1 becomes +5 V and X2 becomes 0 V, and the potential at the input position is passed through Yl to the A / D converter 7.
3 and the coordinates are calculated. The coordinates in the Y direction are calculated in the same manner by switching the circuit. With such a detection circuit, the pressed position of the touch panel 71 is detected.

The circuit configuration and operation of the operation unit 5 in which the image display unit and various input keys are integrated on the operation panel (see FIG. 2) will be described below. FIG. 9 is a functional block diagram illustrating an example of a circuit configuration of the operation unit. As shown in FIG. 9, the operation unit 5 includes a CPU 53, an address latch 54, and an LCDC.
(LCD controller) 55, address decoder 56,
System reset 57, ROM 58, LED driver 5
9, keyboard 60, touch panel 61, LCD module 62, ROM 63, RAM 64, optical transceiver 6
5 is provided.

An address signal from the CPU 53 is taken into an address latch 54, and an address signal is applied to each memory for controlling access to the memory. A part of the address signal output from the address latch 54 enters an address decoder 56, where a chip select signal for each IC is created and used for creating a memory map. Also,
Address is ROM58 (or RAM) memory or LCDC
55 and used for addressing. On the other hand, CPU5
The data bus from No. 3 is connected to the ROM 58 and the LCDC 55 to perform bidirectional data communication. LCDC55
In addition to the address bus and the data bus from the CPU 53, an LED driver 59, a keyboard 60, an analog touch panel 61, an LCD module 62, a display data ROM 63, a RAM 64, and the like are connected.
The LCDC 55 is provided with a signal from a keyboard and a touch panel 6.
The display data is created from the data in the ROM 63 and the RAM 64 in accordance with the signal from 1 and the screen display of the LCD module 62 is controlled. An optical transceiver 65 as an optical fiber connector is connected to the CPU 53 to communicate with the outside.

Next, an image reading apparatus to which the present invention is applied, which is provided in the above-described digital color copying machine, will be described in more detail. 10 and 11 are overall block diagrams mainly showing a read image signal processing system and a scanner (image reading unit 2) control system of the color image reading apparatus of the present embodiment. This processing / control system (hereinafter, scanner I
The function of each element constituting a PU (image processing unit) control unit will be described with reference to FIG.

The CPU 101 on the scanner IPU control unit executes a program stored in the ROM 102 and
03 by reading and writing data etc.
It controls the entire U control unit. Also, the CPU 101
Is connected to the system control unit 104 by serial communication, and performs an operation instructed by transmission and reception of commands and data. The system control unit 104 is connected to the operation display unit 105 by serial communication, and can set an instruction such as an operation mode in response to a key input instruction from a user (the system control unit is related to the system control unit 1 in FIG. 1). See description above). On the other hand, CPU 101
/ O 106 is connected to a document detection sensor, HP sensor, pressure plate open / close sensor, cooling fan, etc.
Control of operations such as detection and ON / OFF at 106 is performed. The scanner motor driver 107 is a CPU
The pulse motor 10 is driven by the PWM output from the pulse generator 101 to generate an excitation pulse sequence and
8 is driven.

An original image is illuminated by a halogen lamp 110 driven below a lamp regulator 109, and reflected light from the original surface passes through a plurality of mirrors and lenses to form an image on a light receiving surface of a three-line CCD 111, thereby forming an image on the original surface. The image is read. The three-line CCD 111 is supplied with a driving clock for each line by a timing circuit 112 on the scanner IPU control unit, and receives red, green,
Emitter followers 113 to 115 convert analog image signals of odd fields (hereinafter referred to as “ODD”) and even fields (hereinafter referred to as “EVEN”) in blue (hereinafter referred to as “R”, “G” and “B”, respectively). Output to The analog outputs from the emitter followers 113 to 115 are input to analog processing circuits 116 to 118, respectively. The subtraction method CDS is executed in the analog processing circuits, and the line clamp is performed by detecting the optical black portion of the CCD.
Each amplifier gain is adjusted to correct so that the VEN output difference disappears. After the gain adjustment, the signals are synthesized by the multiplexer, and finally, after the DC level offset adjustment (detailed in the operation of the phase adjustment mode described later), R,
The G and B signals are input to respective A / D converters (hereinafter referred to as [ADC]) 119 to 121 for RGB.

R input to ADCs 119 to 121,
The G and B analog signals are digitized and input to the shading correction circuit 122. The shading correction circuit 122 has a function of correcting non-uniform light amounts of the illumination system and variations in the pixel output of the CCD. The shading-corrected image data is stored in the line-to-line correction memories 123, 1
The image data corresponding to the number of B, G, and B and R lines of the three-line CCD input to the CCD 24 is delayed by a memory, and one or more lines of the read image signals of B, G, and R are aligned, and a dot correction circuit 125 is provided. Output to The dot correction circuit 125 corrects the dot deviation of the image data output from the inter-line correction memories 123 and 124 within one line of R, G, and B data. Next, the scanner linear correction 126 corrects the linear reflectance data for each color using a look-up table method.

The corrected image data is input to an RGB filter / color conversion / magnification / magnification processing / create processing circuit 130 via an automatic original color determination circuit 128, an automatic image separation circuit 129, and a delay memory 127. The automatic document color determination circuit 128 performs an ACS (chromatic / achromatic determination) process, that is, a determination of black and gray. In the automatic image separation circuit 129, edge determination (determined by the continuity of white pixels and black pixels), halftone dot determination (determined by a repeated pattern of peak / valley peak pixels in an image), and photo determination (character / halftone dot) (When there is image data outside), the area of the character and print (halftone) part and the photograph part is determined and transmitted to the CPU 101,
Subsequent RGB filter, color conversion, printer gamma correction, YM
Used for switching parameters and coefficients in the CK filter and gradation processing.

The R, G, B image data that has passed through the delay memory 127 is input to an RGB filter of an RGB filter, a color conversion process, a scaling process, and a create processing circuit 130. The RGB filter performs processing such as MTF correction of R, G, and B, smoothing, edge enhancement, and through by switching and setting the filter coefficient according to the determination result of the previous area. In the subsequent color conversion processing circuit, the R, G, B data is converted to YM
CK conversion, UCR and UCA processing are executed. Further, the image data input to the scaling processing circuit is enlarged /
Execute the reduction process. After this processing, the image data is branched, and a part of the branched image data is input to the image display unit 132 via the I / F. By doing so, the read image is displayed on the image display unit 13 of the digital color copying machine.
2 can be displayed on the LCD panel (see FIG. 3) and the reading result can be monitored. The create processing circuit performs create editing and color processing. In the create edit, italic, mirror, shadowing, hollowing out processing and the like are executed. In color processing, processing such as color conversion, designated color erasure, and under color is performed.

The write processing circuit 131 for printer γ correction, YMCK filter and the like sets coefficients to be used for printer γ conversion and YMCK filter based on the determination of the previous area. In the gradation process included in the writing process, a dither process is executed, and in the video control, a writing timing setting, an image region, a white region setting, a test pattern generation such as a gray scale and a color patch can be performed,
It is processed so that it can be output to an LD (laser diode) in the final image data writing process, and is output to the LD. The execution of each of the above-described functional processes is performed by performing the setting and operation of each process according to an instruction of the system control unit 104 using a program stored in the ROM 102 connected to the CPU 101.

Here, a processing system for a read image signal, which is a part closely related to the present invention in the scanner IPU control unit of the color image reading apparatus of the above-described embodiment, will be described in detail. FIG. 12 is a block diagram of a processing system for a read image signal, and shows a part of the processing system shown in FIGS.
The same components as those shown in both figures are denoted by the same reference numerals. With reference to FIG. 12, the operation of the processing system will be described focusing on the timing control operation of the drive clock signal related to the processing of the read image signal of this embodiment. The timing circuit 112 sends A (for R, G, B) 119 to 121 to the ADC.
DCLK signal (ADC sampling clock) and ICL to digital processing system after shading correction circuit 122
A K signal (image processing system signal clock) is output. Also,
The timing circuit 112 also outputs a drive clock to the 3-line CCD 111, analog processing system, and the like. With this drive clock, the 3-line CCD 111 outputs analog signals as CCD outputs for each of ODD and EVEN for each of R, G, and B. Similarly, the analog processing circuits 116 to 118 separately process ODD and EVEN, and then combine the signals. ADC1
It is output as an input signal to 19 to 121. The signal waveforms and the timing between the signals are shown in the timing chart of FIG. In the drawing, a scanner image CLK having the same cycle as the basic clock from the oscillator, an OLSYNC (line synchronization signal) determined according to the CCD line, and a quadrupled CLK obtained by quadrupling the basic clock are generated. ADCLK and ICLK, and the scanner image CLK
2 shows the state of the output of the analog image signal (ADC input signal) after the synthesis in the CCD output driven by the analog output circuit and the analog processing circuit that processes the CCD output.

Next, the phase adjustment of the drive clock ADCLK signal output from the timing circuit 112 to the ADCs 119 to 121 and the drive clock ICLK signal to the digital processing system after the ADCs 119 to 121 will be described. The instruction of the phase adjustment is sent from the CPU 101 to the address bus /
A signal is sent to the timing circuit 112 via the data bus and provided to the timing circuit 112 via the bus I / F.
The adjustment is performed by writing adjustment data to the DCLK and ICLK phase adjustment registers. A control signal is output based on the adjustment data value, and the phase is adjusted. The basic clock of the timing circuit 112 is input from an oscillator (not shown). In this example, the basic clock frequency of the oscillator is the same as the scanner image clock frequency, and a quadrupled clock is generated by the PLL circuit (see FIG. 13).
And the basic CLK (scanner image CLK) are input to the phase adjustment circuit and the phases are adjusted, and then output to the ADCs 119 to 121 and the digital processing circuits.

The ADCLK and ICLK phase adjustment registers are the following 8-bit registers. [ADCLK, ICLK phase adjustment register (8 bits)] D7 D6 D5 D4 D3 D2 D1 D0------SEL ADC1 ADC0 Two bits D0 and D1 (ADCO and ADC1 bits) in the 8-bit phase adjustment register are used as ADCLK. , ICLK
The ADCLK and ICLK phase adjustment selection data are written in the signal phase adjustment data in one bit (SEL bit) of D2. SEL bit is “0” and ADCL
Select a mode to adjust K and ICLK in phase,
"1" enables a mode in which only ADCLK is phase-adjusted while ICLK is fixed. The reason for these two modes is selected based on the clock phase of the latch timing of the image data of the digital processing circuit after the shading correction circuit 122. In other words, the ADC to use
What is necessary is just to select a side where the digital data output timing of 119 to 121 and the settling time and hold time of the digital processing circuit in the subsequent stage fall within the allowable value range. For example, even when a newly developed ADC is adopted and the circuit configuration is changed, the sampling clock and the digital data output timing are changed, so that it is possible to respond by selecting the side that satisfies the condition.

In this example, a quadrupled clock is used and the ADC is used.
Since the LK and ICLK signals are generated, there are four patterns of phase adjustment based on the signal period of the quadrupled clock. This is P
It goes without saying that the number of resolution bits differs depending on the number of multiplications selected in the LL circuit. FIGS. 14 and 15 show ADCLK phase-adjusted from the signal period of the quadrupled clock,
4 shows four patterns of an ICLK signal. Both figures are timing charts when the register setting value is changed in four stages (x0h to x3h). FIG. 14 shows ADCLK and ICL.
FIG. 15 shows an example in which K is adjusted in phase, and FIG. 15 shows an example in which only ADCLK is adjusted while ICLK is fixed.
In executing the above, the setting of the ADCLK and ICLK signals is performed by the initial setting of the software of the CPU 101 executed when the power is turned on. Therefore, when the phase adjustment is changed, the software needs to be changed. In addition,
It is also possible to perform the phase adjustment without changing the software. For example, the phase adjustment may be performed by switching a dip switch on the control board or changing the SP mode of the operation display unit 105. In the case of a change from the operation display unit 105, the phase adjustment data input from the operation display unit 105 is transmitted as serial communication data to the CPU 101 of the scanner IPU control unit via the system control unit 104, and the received phase adjustment data is sent to the CPU 101. The adjustment operation is performed based on the data.

Next, another embodiment for adjusting the phase of the ADCLK and ICLK signals will be described below. In the above description, the phase adjustment is performed by setting conditions prepared in advance for hardware or software by input operation when using the present apparatus, but here, when the adjustment amount is changed, An output change is detected, and an optimum adjustment amount is selected based on the detection result. In order to execute the phase adjustment operation mode, a procedure of changing the phase of the ADCLK and ICLK signals, detecting the digital image output when the phase is changed, evaluating the detection result, and determining the phase adjustment data according to the evaluation. Need. In this embodiment, the phase adjustment mode is set to the analog processing circuits 116 to 118 and the ADCs 119 to 121.
And shading correction circuit (digital value detection circuit) 1
22. At this time, a phase detection is performed using a digital value detection circuit which also serves as the shading correction circuit 122 without providing a new circuit for detecting the image signal output after being processed by the ADCs 119 to 121. , The image signal output after being driven and processed by the ADCLK and ICLK signals having changed is detected and evaluated.

Hereinafter, the phase adjustment mode of this embodiment will be described in detail. When an ADC phase adjustment key (not shown) in the SP mode of the operation display unit 105 is pressed, the ADC phase adjustment mode is executed. The CPU 101 notifies the shading correction circuit 122 of the transition to the ADC phase adjustment mode to the register setting unit in the circuit via the bus I / F. As a result, the memory normally used as a white memory for shading correction is set to a state in which an average value (for example, an average of 10 lines) for each dot of read image data can be stored. A detection circuit. Here, ADCLK, ICL
ADC with SEL bit of K phase adjustment register set to “0”
A case where LK and ICLK are adjusted in phase will be described.

FIG. 16 shows a flowchart of the ADC phase adjustment mode. According to the flow shown in FIG.
The operation in the phase adjustment mode will be described. Note that the step numbers shown in FIG. 16 are added in parentheses to the description for reference. This flow is started when the ADC phase adjustment key of the operation display unit 105 is pressed. First, the shift to the ADC phase adjustment mode is notified to the shading correction circuit 122, and the mode is set to the phase adjustment mode in which the operation is performed as a digital value detection circuit. (S1). Next, since the phase is adjusted based on the data on the white reference plate, the carriage on which the illumination system is mounted is moved from the home position onto the white reference plate, and the exposure lamp is turned on (S2). The exposed white reference plate is imaged on the three-line CCD 111, and AD is obtained by the photoelectric conversion output signal.
A CLK phase adjustment subroutine is executed (S3). AD
After the CLK phase adjustment subroutine is completed and the exposure lamp is turned off, return to the home position (S4), and the operation of the digital value detection circuit according to the setting of the phase adjustment mode is performed by the original shading correction circuit 122. Then, the operation of the ADC phase adjustment mode is completed (S5).

The ADCLK phase adjustment subroutine in the operation flow of the ADC phase adjustment mode will be described in detail. FIG. 17 is a chart showing an operation flow of the ADCLK phase adjustment subroutine. According to the illustrated flow, AD
The operation of the CLK phase adjustment subroutine will be described. This flow corresponds to step S3 in the ADC phase adjustment mode described above.
In FIG. 16, the exposed white reference plate is three lines C
Image was formed on CD111, line-scanned, and photoelectrically converted
It starts when ODD and EVEN image output signals are obtained. In the analog processing circuits 116 to 118, the ODD and E by the white reference plate input from the emitter followers 113 to 115 are output.
After performing the correction for eliminating the output difference of the VEN image signal, the signal level difference value between ODD and EVEN is further increased by a certain amount: A
The gain is adjusted so as to be shifted only by one (S3
01).

Next, the CPU 101 controls the timing circuit 11
Set value to ADCLK and ICLK phase adjustment registers
x0h is written (S302). Here, it is confirmed whether or not the line synchronization signal has been counted 10 in order to average the output in the set phase for a certain period of time (S303), and after the confirmation, the digital device operates in the mode set in the previous step S1 (FIG. 16). The CPU 101 reads the averaged data value for each dot from the memory of the value detection circuit 122 (S304). A difference is calculated for a value obtained by averaging the read line unit data for each ODD and EVEN, a difference value: B is obtained, and a value set in the previous step S301: A (between ODD and EVEN) Signal level difference), that is, (AB), and its absolute value: |
AB | is obtained as the result: C (S305), and the obtained result C is stored in the RAM (S306).

Next, the CPU 101 sets the timing circuit 1
The setting value = x1h for setting the next shift value is written to the 12 ADCLK and ICLK phase adjustment registers (S30).
7), that is, the state of shift 1 (one pulse delay) (FIG. 1)
4 and 15), and as in the previous steps,
After a predetermined time required for averaging (S308), the CPU 101 reads the average value data for each dot from the memory of the digital value detection circuit 122 (S309). The same processing as described above is executed from the read line-by-line data, C = | AB | is calculated (S310), and the obtained result is stored in the RAM (S311). Then, CP
U101 is ADCLK and ICL of the timing circuit 112.
Set value for setting the next shift value in the K phase adjustment register =
x3h is written (S312), that is, shift 4 (1
In the state of “pulse advance” (see FIGS. 14 and 15), similarly to the previous step, after a certain period of time necessary for averaging (S313), the memory of the digital value detection circuit 122 stores one dot at a time. The CPU 101 reads the average value data (S314). The same processing as described above is executed from the read line-by-line data, C = | AB | is calculated (S315), and the obtained result is stored in the RAM (S316). RA obtained at each shift position described above
Result stored in M〜: C = | A−B | is compared to determine the best phase adjustment data (S317),
One of the determined x0h to x3h is ADCLK, IC
The ADCLK phase adjustment subroutine is completed by setting the LK phase adjustment register (S318).

In this embodiment, the quadrupled clock is generated by the PLL circuit for the phase adjustment. However, the resolution of the phase adjustment is increased by using the 8-multiplied clock and the 16-multiplied clock, and the adjustment is performed with better accuracy. Is also good. In this case, a good result can be obtained by taking several pulses of the phase delay and advance pulses from the reference position and comparing the data of the previous calculation to determine the phase. In the present invention, gain adjustment is performed for each of the ODD and EVEN image data such that the difference between the signal levels of the two is shifted by a certain amount: A. OD
By making a difference between the image signal levels of D and EVEN,
If sampling is not performed at the correct position, data at the change point will be taken in. B (difference value obtained by averaging data in line units for ODD and EVEN)
Becomes small, and the result C becomes a large value. That is, if the value of the result C becomes smaller, the sampling is performed at an appropriate position.
It becomes easy to determine the optimal adjustment, for example, it becomes easy to visually confirm the sampling position of the D conversion with an oscilloscope or the like.

[0039]

(1) Line image sensor and A /
Conventionally, the drive clock of the D converter (ADC) is restricted by a hardware change such as adding a delay line when adjusting the timing because the clock is conventionally generated by a timing LSI. Although it has been difficult, according to the present invention, clock generation means for adjusting the output timing of the driving clock by the phase adjustment data is provided. By writing the clock, the clock is generated in a state where the phase is delayed or advanced, without changing the hardware (such as inserting a conventional delay line), and the gate and sample and hold at the appropriate output position Then, it becomes possible to drive the line image sensor and the ADC. In addition, in order to reduce radiation noise performed in accordance with EMI regulations, a CCD drive clock, an analog processing execution clock,
In addition, it is necessary to smooth the clock waveform by inserting a filter or a damping resistor or changing the constant in the ADC clock.
A delay occurs at the falling edge and a delay occurs in the signal output. For this reason, insertion of a filter or a damping resistor or change of a constant must be adjusted at a level that does not affect image data. However, according to the present invention, even if the delay occurs, the phase can be adjusted. The adverse effects of the countermeasures can be prevented, the signal output can be sampled at a good timing even under such conditions, and the radiation noise level can be greatly reduced, thereby expanding the range of use.

(2) In addition to the above-mentioned effect (1), digital data obtained by converting an analog image signal obtained by photoelectric conversion from a line image sensor by an ADC is detected, and phase adjustment data generated based on the detection result is obtained. By adjusting the timing of the drive clock by using, the ADC can be driven by sampling and holding at a more appropriate output position.

(3) In addition to the above effects (1) and (2), analog processing for adjusting the gain of the analog image signal so as to give an offset to the DC level after correcting the output difference between ODD and EVEN. By providing means,
If driving (gate, sample) can be performed at an appropriate position when adjusting the phase, the same data value as the level difference given to ODD and EVEN is taken; otherwise, the difference given by the gain adjustment (for example, a pixel change point) And it is easy to visually check the pixel position and the A / D conversion sampling position with an oscilloscope or the like, and it is possible to provide a data result which is easy to process when judging a change in the output value. It becomes possible to raise it.

(4) In addition to the effects of the above (1) to (3), the step of adjusting the phase adjustment data is performed by using a multiplying circuit or the like by a PLL by an integer of the cycle of the pixel clock (ADC driving clock). By eliminating the accumulation and accumulation of the delay amount of the gate as the length of 1, the phase can be adjusted more accurately.

(5) In addition to the effects of the above (1) to (4), by adjusting the adjustment width of the phase adjustment data over one cycle of the pixel clock (drive clock of the ADC), Since the adjustment can be performed, not only the delay direction but also the advance direction can be adjusted, and the optimum operation can be performed.

(6) In addition to the above effects (1) to (5), the digital data detecting means uses the memory holding the detected data as the memory of the shading correcting means, so that the digital data detecting means can be referred to. In addition, it is possible to suppress an increase in cost when newly preparing an expensive memory only for phase adjustment.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of an overall configuration of a digital color copying machine capable of suitably implementing an image reading apparatus of the present invention.

FIG. 2 is a diagram showing an example of an operation panel of an operation unit of the digital color copying machine shown in FIG.

FIG. 3 is a functional block diagram showing a circuit configuration of an image display unit of the digital color copying machine shown in FIG.

FIG. 4 is a view showing one embodiment of an LCD panel of the image display unit shown in FIG. 3;

5 is a diagram showing an example of a screen displayed on the LCD panel shown in FIG.

6 shows an example of screen expansion by pressing a scaling key on the screen shown in FIG.

FIG. 7 is a diagram illustrating an example of a configuration of a touch panel detection circuit.

8 illustrates a setting state of potentials of X and Y electrodes of the touch panel in the detection circuit of FIG.

9 is a functional block diagram showing an example of a circuit configuration of an operation unit of the digital color copying machine shown in FIG.

FIG. 10 is an overall block diagram (part 1) mainly showing a read image signal processing system and a scanner control system of the color image reading apparatus to which the present invention is applied.

FIG. 11 is an overall block diagram (part 2) mainly showing a read image signal processing system and a scanner control system of the color image reading apparatus to which the present invention is applied.

FIG. 12 is a block diagram of a processing system of a read image signal in the image reading apparatus to which the present invention is applied.

FIG. 13 is a chart showing signal waveforms of a processing system for a read image signal and timing between signals.

FIG. 14 shows four patterns of ADCLK and ICLK signals (in-phase) whose phases have been adjusted from the signal period of the quadrupled clock.

FIG. 15 shows four patterns of an ADCLK signal (ICLK signal fixed) whose phase has been adjusted from the signal period of the quadrupled clock.

FIG. 16 is a chart showing an operation flow in an ADCLK phase adjustment mode.

FIG. 17 is a chart showing an operation flow of an ADCLK phase adjustment subroutine.

[Explanation of symbols]

101: CPU, 104: System control unit,
105: operation display unit, 111: 3-line CCD,
112: timing circuit, 116 to 118: analog processing circuit (for R, G, B), 119 to 121: ADC
(A / D converter) (for R, G, B), 122... Shading correction circuit (digital value detection circuit).

Continued on front page F-term (reference) 5B047 AA01 BB02 CA06 CB17 CB30 DA01 DA04 DB01 5C051 AA01 BA03 DA03 DB01 DB15 DE03 DE15 DE17 DE18 5C072 AA01 BA04 EA05 FB08 FB12 FB23 RA20 UA02 UA05 UA06 XA01 5C03 PP03 PP03 PP03 RR01 SS01 TT06

Claims (6)

[Claims] 1. A line image sensor for reading an image, A / D conversion means for converting an analog image signal output from the line image sensor into digital image data, and operation of the line image sensor and A / D conversion means In an image reading apparatus having a drive clock generating means for generating each drive clock to be driven and a control means for controlling the operations of the line image sensor and the A / D conversion means, the control means converts phase adjustment data via a data bus. An image reading apparatus, wherein output timing of a drive clock is adjusted by setting the drive clock generation means. 2. The image reading apparatus according to claim 1, further comprising digital data detection means for detecting digital image data from said A / D conversion means, wherein said control means outputs phase adjustment data based on a detection result of said digital data detection means. The image reading device according to claim 1, wherein the image reading device generates the image. 3. The image reading apparatus according to claim 1, wherein said image reading device corrects the ODD and EVEN image signals obtained by the sub-scanning of the line image sensor so as to eliminate an output difference between the signals, and then offsets a certain DC level between the ODD and EVEN signals. 3. The image reading apparatus according to claim 1, further comprising an analog processing unit that performs a gain adjustment so as to provide a gain, and inputs an output of the analog processing unit to the A / D conversion unit. 4. The image reading apparatus according to claim 1, wherein the step of adjusting the phase adjustment data is performed by setting the length of the phase adjustment data to a length that is a fraction of the cycle of the pixel clock. 5. The image reading apparatus according to claim 2, wherein an adjustment width of the phase adjustment data is set to a length corresponding to one cycle of the pixel clock. 6. The image reading apparatus according to claim 1, further comprising a shading correction unit provided downstream of the A / D conversion unit, wherein the digital data detection unit uses a memory for storing the detection data as a memory for the shading correction unit. The image reading device according to claim 2, wherein: