JP2000306932A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JP2000306932A
JP2000306932A JP11114132A JP11413299A JP2000306932A JP 2000306932 A JP2000306932 A JP 2000306932A JP 11114132 A JP11114132 A JP 11114132A JP 11413299 A JP11413299 A JP 11413299A JP 2000306932 A JP2000306932 A JP 2000306932A
Authority
JP
Japan
Prior art keywords
resin
wire
substrate
semiconductor element
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11114132A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yamakawa
裕之 山川
Takashi Nagasaka
長坂  崇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP11114132A priority Critical patent/JP2000306932A/en
Publication of JP2000306932A publication Critical patent/JP2000306932A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To achieve a manufacturing method, wherein a resin can be applied to a wire-bond mounting section so that no voids remain within the resin without increasing the sealing region and application time, in a resin-sealed semiconductor device. SOLUTION: Semiconductor chips 21 to 26 mounted on a board 10 are wire- bonded to the board 10 with wires 30, after which first resin portions 40 are applied to connecting parts between the wires 30 and the board 10, using a dispenser in a manner filling the clearances between the wires 30 and the board 10. Thereafter, second resin portions 50 are applied onto the chips 21 to 26 using the dispenser, the resin portions 50 having a lower viscosity than that of the resin portions 40, and successively the resin portions 40 and 50 are cured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、基板上にワイヤボ
ンド実装された半導体素子を樹脂で封止してなる半導体
装置(以下、樹脂封止型半導体装置という)の製造方法
に関し、特に、樹脂の封止方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device (hereinafter referred to as a resin-encapsulated semiconductor device) in which a semiconductor element wire-bonded on a substrate is sealed with a resin. A sealing method.

【0002】[0002]

【従来の技術】従来の一般的な樹脂封止型半導体装置を
図4に示す。樹脂封止型半導体装置J1においては、プ
リント基板やセラミック基板等よりなる基板J2上に搭
載された半導体素子J3に対してワイヤボンディングを
行うことにより、半導体素子J2と基板J1の電極部と
が、ワイヤJ4にて結線され電気的に接続されている。
2. Description of the Related Art FIG. 4 shows a conventional general resin-sealed semiconductor device. In the resin-encapsulated semiconductor device J1, by performing wire bonding to the semiconductor element J3 mounted on the substrate J2 such as a printed board or a ceramic substrate, the semiconductor element J2 and the electrode portion of the substrate J1 are connected to each other. They are connected by wires J4 and are electrically connected.

【0003】そして、このような半導体素子J3及びワ
イヤJ4よりなるワイヤボンド実装部は、エポキシ樹脂
等よりなる樹脂J5により包み込むように封止されてい
る。この樹脂J5にて、半導体素子J3、ワイヤJ4、
及び基板J2の電極部を封止した構成とすることによ
り、熱、湿気、振動等の外的環境から接続部や半導体回
路部が保護されている。
[0003] Such a wire bond mounting portion composed of the semiconductor element J3 and the wire J4 is sealed so as to be surrounded by a resin J5 composed of an epoxy resin or the like. With this resin J5, a semiconductor element J3, a wire J4,
The connection portion and the semiconductor circuit portion are protected from an external environment such as heat, moisture, and vibration by sealing the electrode portion of the substrate J2.

【0004】図5は、樹脂封止型半導体装置J1の従来
製造方法を示す工程図であり、基板J2上に複数個の半
導体素子J3をワイヤボンド実装した場合の樹脂封止方
法を示す工程図である。樹脂封止型半導体装置J1にお
いては、一個の半導体素子J3の外周部分に液状の樹脂
J6をディスペンサ(注射器のようなもの)を用いるデ
ィスペンス方式にて塗布した後、半導体素子J3上に同
じ液状の樹脂J6をディスペンス方式にて塗布する。そ
して、この工程を各半導体素子J3毎に繰り返した後、
熱処理等による樹脂の硬化を行う。こうして、図4に示
した樹脂封止型半導体装置J1が形成される。
FIG. 5 is a process chart showing a conventional method of manufacturing a resin-sealed semiconductor device J1, and is a process chart showing a resin-sealing method when a plurality of semiconductor elements J3 are mounted by wire bonding on a substrate J2. It is. In the resin-encapsulated semiconductor device J1, a liquid resin J6 is applied to the outer peripheral portion of one semiconductor element J3 by a dispensing method using a dispenser (such as a syringe), and then the same liquid is applied onto the semiconductor element J3. The resin J6 is applied by a dispense method. Then, after repeating this process for each semiconductor element J3,
The resin is cured by heat treatment or the like. Thus, the resin-sealed semiconductor device J1 shown in FIG. 4 is formed.

【0005】[0005]

【発明が解決しようとする課題】ところで、近年、電子
機器の小型化に伴い、図6に示す様に、半導体装置J1
におけるワイヤJ4の狭ピッチ化やワイヤJ4の長さを
短くする傾向となってきている。このような高密度化さ
れたワイヤJ4において、上記した従来の樹脂封止方法
を用いた場合、図4及び図6に示す様に、樹脂の塗布後
に、半導体素子J3の外周端部に位置するワイヤJ4の
直下部分(ワイヤJ4と基板J2との空隙)Bにボイド
(気泡)が残る。このボイドは、信頼性上、ワイヤJ4
の断線(オープン)やワイヤJ4間のリークの原因とな
る。
By the way, in recent years, with the miniaturization of electronic equipment, as shown in FIG.
, The pitch of the wire J4 is becoming narrower and the length of the wire J4 is becoming shorter. When the above-described conventional resin sealing method is used for such a high-density wire J4, as shown in FIGS. 4 and 6, after the resin is applied, the wire J4 is located at the outer peripheral end of the semiconductor element J3. Voids (bubbles) remain in the portion B immediately below the wire J4 (the gap between the wire J4 and the substrate J2). This void is wire J4 for reliability.
Disconnection (open) and leakage between the wires J4.

【0006】ここで、従来より、ボイドの発生を防止す
る手段としては、塗布する樹脂の粘度を下げる(樹脂自
身の粘度を下げる、あるいは、加温する)方法がある
が、この方法の場合、低粘度の樹脂が基板上で流れやす
く、封止領域が増大してしまうという問題がある。封止
領域の増大は半導体装置の高密度実装化にとって好まし
くない。
Here, conventionally, as a means for preventing the generation of voids, there is a method of lowering the viscosity of the resin to be applied (reducing the viscosity of the resin itself or heating). In the case of this method, There is a problem that the low-viscosity resin easily flows on the substrate and the sealing area increases. An increase in the sealing area is not preferable for high-density mounting of the semiconductor device.

【0007】また、ディスペンサとしてニードル径の細
いものを用い、ワイヤボンド実装部全域に渡って、ゆっ
くり塗布する方法があるが、この方法だと塗布時間が長
くなってしまうという問題がある。本発明は上記問題に
鑑み、樹脂封止型半導体装置において、封止領域や塗布
時間を増加させることなく、樹脂内にボイドが残らない
ようにワイヤボンド実装部に樹脂を塗布することのでき
る製造方法を提供することを目的とする。
In addition, there is a method in which a thin needle is used as a dispenser and the dispenser is applied slowly over the entire area of the wire bond mounting portion. However, this method has a problem that the application time is lengthened. In view of the above problems, the present invention provides a resin-encapsulated semiconductor device in which a resin can be applied to a wire bond mounting portion without increasing voids in the resin without increasing a sealing area or application time. The aim is to provide a method.

【0008】[0008]

【課題を解決するための手段】本発明者等は、ボイド残
りの発生位置が、上述のように、半導体素子の外周端部
に位置するワイヤの直下部分に主に発生することから、
半導体素子以外のワイヤ部分に塗布する工程と半導体素
子上に塗布する工程とで、樹脂の粘度や塗布方法等を変
えることに着目し、本発明を創出するに至った。
According to the present inventors, since the position where the void remains is mainly generated in the portion directly below the wire located at the outer peripheral end of the semiconductor element as described above,
The present invention was created by paying attention to changing the viscosity of the resin, the coating method, and the like between the step of applying to a wire portion other than the semiconductor element and the step of applying to the semiconductor element.

【0009】即ち、請求項1記載の発明においては、ワ
イヤボンディングを行った後、ワイヤ(30)と基板
(10)との間隙を埋めるように、該ワイヤと該基板と
の接続部に第1の樹脂(40)をディスペンサを用いて
塗布する第1の塗布工程と、この後、半導体素子(21
〜26)上に、該第1の樹脂の塗布時における状態より
も低粘度とした状態で第2の樹脂(50)をディスペン
サを用いて塗布する第2の塗布工程と、続いて、塗布さ
れた該第1及び第2の樹脂を硬化させる硬化工程とを備
えることを特徴としている。
That is, according to the first aspect of the present invention, after the wire bonding is performed, the first connecting portion between the wire (30) and the substrate (10) is so filled as to fill the gap between the wire (30) and the substrate (10). A first application step of applying the resin (40) by using a dispenser, and thereafter, a semiconductor element (21)
To 26), a second application step of applying the second resin (50) using a dispenser in a state where the viscosity is lower than that at the time of application of the first resin, and And a curing step of curing the first and second resins.

【0010】本製造方法によれば、第1の塗布工程に
て、第1の樹脂を、ワイヤと基板との接続部に対して、
ワイヤと基板との空隙を埋めるようにディスペンス方式
で塗布することで、塗布後の樹脂における上記ワイヤの
直下部分にボイドが残らない。そして、第2の塗布工程
にて、残りの部分である半導体素子上に、第1の樹脂の
塗布時における状態よりも低粘度とした状態で第2の樹
脂をディスペンス方式で塗布し、硬化工程にて、樹脂の
硬化を行い、ワイヤボンド実装部の樹脂封止が完了す
る。
According to this manufacturing method, in the first coating step, the first resin is applied to the connection between the wire and the substrate.
By applying by a dispense method so as to fill the gap between the wire and the substrate, no void remains in the resin immediately after the wire in the applied resin. Then, in the second application step, the second resin is applied by dispensing on the remaining semiconductor element in a state where the second resin has a viscosity lower than that at the time of application of the first resin, and a curing step is performed. Then, the resin is cured, and the resin sealing of the wire bond mounting portion is completed.

【0011】ここで、上述した従来の方法では、半導体
素子外周部のワイヤと基板との接続部への塗布工程と、
半導体素子上への塗布工程とを、同じ樹脂を用いて行っ
ているが、この後者の塗布工程に相当する塗布工程を、
本発明では、第2の塗布工程において、より低粘度の樹
脂を用いて行っており、塗布領域への樹脂の広がりを速
くすることができるため、従来よりも塗布時間の短縮が
図れる。
Here, in the above-mentioned conventional method, a step of coating a connection portion between a wire and a substrate at an outer peripheral portion of a semiconductor element is performed,
The coating step on the semiconductor element is performed using the same resin, but the coating step corresponding to the latter coating step is
In the present invention, in the second application step, a resin having a lower viscosity is used, and the spread of the resin to the application region can be accelerated, so that the application time can be reduced as compared with the related art.

【0012】なお、第1の塗布工程では、ワイヤと基板
との空隙を埋めるようにディスペンス方式で塗布するた
め、その塗布時間は、単位塗布面積当たりで考えれば従
来と同程度であるが、塗布領域がワイヤボンド実装部全
体ではなく、半導体素子以外の部分であるワイヤと基板
との接続部であるため、少ない領域で済む。よって、第
1及び第2の塗布工程を合わせた塗布時間は、従来と同
程度か従来よりも短い時間となる。
In the first coating step, since the coating is performed by a dispense method so as to fill the gap between the wire and the substrate, the coating time is substantially the same as that of the related art when considered per unit coating area. Since the region is not the entire wire bond mounting portion but the connection portion between the wire and the substrate, which is a portion other than the semiconductor element, only a small region is required. Therefore, the application time including the first and second application steps is equal to or shorter than the conventional one.

【0013】また、第1の塗布工程により、高粘度の第
1の樹脂で半導体素子周囲部分を先に囲んでしまうた
め、次に、第2の塗布工程にて、低粘度の第2の樹脂を
塗布しても、第2の樹脂が流れだすのを抑制できる。従
って、本発明によれば、封止領域や塗布時間を増加させ
ることなく、樹脂内にボイドが残らないようにワイヤボ
ンド実装部に樹脂を塗布することのできる樹脂封止型半
導体装置の製造方法を提供することができる。
In the first coating step, the peripheral portion of the semiconductor element is first surrounded by the high-viscosity first resin, so that the low-viscosity second resin is used in the second coating step. Can be prevented from flowing out of the second resin. Therefore, according to the present invention, a method of manufacturing a resin-encapsulated semiconductor device capable of applying a resin to a wire bond mounting portion without increasing voids in the resin without increasing a sealing region or application time Can be provided.

【0014】ここで、請求項2記載の発明のように、第
2の塗布工程において、第1の塗布工程に用いたディス
ペンサよりもニードル径の大きいディスペンサを用いれ
ば、塗布時間をより短くできる。また、請求項3記載の
発明では、請求項1の製造方法と同様に、第1の塗布工
程及び硬化工程を行うが、第1の塗布工程及び硬化工程
の間に行う第2の工程において、半導体素子(21〜2
6)上に、第2の樹脂(50)を印刷法により塗布する
ことを特徴としている。
Here, as in the second aspect of the invention, in the second application step, if a dispenser having a larger needle diameter than the dispenser used in the first application step is used, the application time can be further shortened. In the invention according to claim 3, the first coating step and the curing step are performed as in the manufacturing method of claim 1, but in the second step performed between the first coating step and the curing step, Semiconductor element (21-2
6) The method is characterized in that the second resin (50) is applied by a printing method.

【0015】本製造方法によれば、請求項1の発明と同
様、第1の塗布工程によりボイドの発生及び封止領域の
増加を防止でき、通常のディスペンス方式に比べて塗布
時間が塗布面積にさほど影響されない印刷法を用いて、
第2の工程を行うことで、塗布時間を短縮できるから、
上記目的を達成することができる。また、請求項4記載
の発明では、請求項1の製造方法と同様に、第1の塗布
工程及び硬化工程を行うが、第1の塗布工程及び硬化工
程の間に行う第2の工程において、固形状とした第2の
樹脂(50)を半導体素子(21〜26)上に配置した
後、溶融させることにより、該第2の樹脂を該半導体素
子上に塗布することを特徴としている。
According to the present manufacturing method, similarly to the first aspect of the present invention, generation of voids and an increase in the sealing area can be prevented by the first coating step, and the coating time can be reduced as compared with the ordinary dispensing method. Using a printing method that is less affected,
By performing the second step, the coating time can be reduced.
The above object can be achieved. Further, in the invention according to claim 4, the first application step and the curing step are performed similarly to the manufacturing method of claim 1, but in the second step performed between the first application step and the curing step, The method is characterized in that the solid second resin (50) is disposed on the semiconductor element (21 to 26) and then melted to apply the second resin onto the semiconductor element.

【0016】本製造方法によれば、請求項1の発明と同
様、第1の塗布工程によりボイドの発生及び封止領域の
増加を防止でき、第2の工程においては、第2の樹脂を
固形物として配置して溶融させるだけで塗布でき、塗布
時間が塗布面積に影響されない。よって、本製造方法に
よっても、上記目的を達成することができる。なお、上
記各手段の括弧内の符号は、後述する実施形態に記載の
具体的手段との対応関係を示す一例である。
According to the present manufacturing method, similarly to the first aspect of the present invention, generation of voids and an increase in the sealing area can be prevented by the first coating step, and the second resin is solidified in the second step. It can be applied simply by disposing and melting it as an object, and the application time is not affected by the application area. Therefore, the above object can also be achieved by the present manufacturing method. It should be noted that reference numerals in parentheses of the above-described units are examples showing the correspondence with specific units described in the embodiments described later.

【0017】[0017]

【発明の実施の形態】以下、本発明を図に示す実施形態
について説明する。図1は、本実施形態に係る樹脂封止
型半導体装置の製造方法を示す工程図であり、基板にお
ける半導体素子の搭載面上方からみたものである。本実
施形態は、ワイヤボンド実装部が基板上に複数個搭載さ
れた半導体装置に適用したものとして説明する。以下、
製造工程順に説明していく。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 1 is a process diagram showing a method for manufacturing a resin-encapsulated semiconductor device according to the present embodiment, as viewed from above a mounting surface of a substrate on which a semiconductor element is mounted. This embodiment will be described as applied to a semiconductor device in which a plurality of wire bond mounting units are mounted on a substrate. Less than,
The description will be made in the order of the manufacturing process.

【0018】まず、図1(a)に示す様に、ワイヤボン
ド実装部が複数個搭載された基板10を用意する。基板
10は、例えば樹脂製のプリント基板やセラミック基板
等に対して図示しない電極部(配線部)が形成されたも
のである。この基板10上には、複数個(図示例では6
個)の平面矩形の半導体チップ(本発明でいう半導体素
子)21〜26がAgペースト等により接着、搭載され
ている。
First, as shown in FIG. 1A, a substrate 10 on which a plurality of wire bond mounting portions are mounted is prepared. The substrate 10 is formed by forming an electrode portion (wiring portion) (not shown) on a resin printed board, a ceramic substrate, or the like, for example. On the substrate 10, a plurality (6 in the illustrated example)
Semiconductor chips (semiconductor elements according to the present invention) 21 to 26 are bonded and mounted with an Ag paste or the like.

【0019】個々の半導体チップ21〜26と基板10
の上記電極部とは、ワイヤボンディングを行うことによ
り形成された金やアルミニウム等よりなるワイヤ30に
より、結線され電気的に接続されている。そして、半導
体チップ21〜26及びワイヤ30よりなる個々のワイ
ヤボンド実装部は、基板10の上記電極部とともに、電
気的に回路を構成している。
The individual semiconductor chips 21 to 26 and the substrate 10
Are connected and electrically connected to the above-mentioned electrode portion by a wire 30 made of gold, aluminum or the like formed by performing wire bonding. The individual wire bond mounting portions including the semiconductor chips 21 to 26 and the wires 30 together with the electrode portions of the substrate 10 electrically configure a circuit.

【0020】そして、用意された基板10に対して、ワ
イヤ30と基板10との間隙を埋めるように、ワイヤ3
0と基板10との接続部に第1の樹脂40を、ディスペ
ンサを用いて塗布する第1の塗布工程を行い、次に、半
導体チップ21〜26上に、上記第1の樹脂40の塗布
時における状態よりも低粘度とした状態で第2の樹脂5
0を、ディスペンサを用いて塗布する第2の塗布工程を
行う。
Then, the wire 3 is placed on the prepared substrate 10 so as to fill the gap between the wire 30 and the substrate 10.
A first application step of applying the first resin 40 to a connection portion between the first resin 40 and the substrate 10 using a dispenser is performed, and then, when the first resin 40 is applied onto the semiconductor chips 21 to 26. In the state where the viscosity is lower than the state in
0 is applied using a dispenser.

【0021】具体的には、図1(a)に示す様に、用意
された基板10における半導体チップ21の1辺の外周
部に、例えばエポキシ系樹脂等の高粘度の硬い樹脂(第
1の樹脂、図中、斜線ハッチングで図示)40をディス
ペンサを用いて塗布する(ディスペンスする)。この
際、望ましくは基板10を加温(例えば60℃)してお
くことにより、ワイヤ30間の第1の樹脂40の回り込
みが良くなる。
More specifically, as shown in FIG. 1A, a high-viscosity hard resin such as an epoxy resin (first resin) is provided on the outer periphery of one side of the semiconductor chip 21 in the prepared substrate 10. A resin 40 (shown by hatching in the figure) is applied (dispensed) using a dispenser. At this time, the substrate 10 is desirably heated (for example, at 60 ° C.), so that the first resin 40 between the wires 30 is better wrapped around.

【0022】次に、チップ22、チップ23、チップ2
4、チップ25、チップ26の各々の1辺の外周部に塗
布した後、図1(b)に示す様に、チップ21における
1辺と直交する次の辺の外周部に塗布する。同様の塗布
(ディスペンス)の繰り返しを実施し、図1(c)に示
す様に、チップ21〜26すべての4辺の外周部に第1
の樹脂40を塗布する。これら図1(a)〜(c)の工
程が第1の塗布工程である。
Next, chip 22, chip 23, chip 2
4, the coating is applied to the outer peripheral portion of one side of each of the chip 25 and the chip 26, and then to the outer peripheral portion of the next side of the chip 21 orthogonal to the one side, as shown in FIG. By repeating the same application (dispensing), as shown in FIG.
Is applied. These steps in FIGS. 1A to 1C are a first coating step.

【0023】ここで、複数個ある各チップ21〜26毎
に1辺ずつ塗布することにより、各チップにおける1辺
と次の辺との塗布の間に時間差が設けられるため、確実
にワイヤ30と基板10との間に第1の樹脂40が回り
込み、空気閉じこめによるボイドの発生を防止すること
ができる。次に、第2の塗布工程では、図1(d)に示
す様に、各チップ21〜26の中央部上に、第1の樹脂
40よりも低粘度の樹脂(第2の樹脂、図中、点ハッチ
ングで図示)50をディスペンサを用いて塗布する。
Here, by applying one side to each of the plurality of chips 21 to 26, a time difference is provided between the application of one side and the next side of each chip, so that the wire 30 is surely connected to the other side. The first resin 40 goes around between the substrate 10 and the substrate 10, so that it is possible to prevent the occurrence of voids due to trapped air. Next, in the second coating step, as shown in FIG. 1D, a resin having a lower viscosity than the first resin 40 (the second resin, , 50 shown by dot hatching) using a dispenser.

【0024】第2の樹脂50としては、例えば、第1の
樹脂40と同じ樹脂であっても溶剤を多くして低粘度と
したものや、第1の樹脂40とは異なる樹脂としてチク
ソ係数を変えることで低粘度としたものを用いることが
できる。特に限定しないが、第1及び第2の樹脂40、
50としては、上記のエポキシ系樹脂の他、アクリル系
樹脂、フェノール系樹脂等の中から、硬化工程にて同時
に硬化可能な組み合わせを採用可能である。
As the second resin 50, for example, the same resin as the first resin 40 but having a low viscosity by increasing the solvent, or a resin different from the first resin 40 having a thixotropic coefficient By changing it, a material having a low viscosity can be used. Although not particularly limited, the first and second resins 40,
As 50, a combination that can be simultaneously cured in the curing step can be adopted from among the above-mentioned epoxy resins, acrylic resins, phenolic resins, and the like.

【0025】なお、第2の塗布工程に用いるディスペン
サのニードル径を、第1の塗布工程に用いたディスペン
サよりも大きいものとすれば、その分、より多量の樹脂
を一度に供給できるから、塗布時間をより短くできる。
この後、樹脂のチクソ性(粘性)により一体化した第1
及び第2の樹脂40、50を、加熱処理して硬化させる
(硬化工程)。こうして、各ワイヤボンド実装部の樹脂
封止が完了する。図2は、樹脂封止完了後の完成した半
導体装置の概略断面(基板10と直交する断面)を示
す。
If the needle diameter of the dispenser used in the second coating step is made larger than that of the dispenser used in the first coating step, a larger amount of resin can be supplied at a time by that amount. Time can be shorter.
Thereafter, the first resin is integrated by the thixotropic property (viscosity) of the resin.
Then, the second resins 40 and 50 are cured by heat treatment (curing step). Thus, the resin sealing of each wire bond mounting portion is completed. FIG. 2 shows a schematic cross section (a cross section orthogonal to the substrate 10) of the completed semiconductor device after the resin sealing is completed.

【0026】ところで、上記製造方法によれば、第1の
塗布工程にて、第1の樹脂40を、ワイヤ30と基板1
0との接続部に対して、ワイヤ30と基板10との空隙
を埋めるようにディスペンス方式で塗布することで、塗
布後の第1の樹脂40におけるワイヤ30の直下部分
(図2中の破線で囲んだC部)にボイドが残らない。つ
まり、全ての半導体チップ21〜26について、先に外
周部に塗布を行い、次に、時間差を設けてチップ21〜
26上に塗布を行うため、第1の樹脂40が十分にワイ
ヤ30の直下部分に行き渡り、ワイヤ30と基板10と
の空隙を埋めることができるのである。
According to the above-described manufacturing method, the first resin 40 is connected to the wire 30 and the substrate 1 in the first coating step.
In the first resin 40 after application, the portion directly below the wire 30 (indicated by the broken line in FIG. 2) is applied to the connection portion with the wire 30 by a dispense method so as to fill the gap between the wire 30 and the substrate 10. No void remains in the enclosed C section). In other words, for all the semiconductor chips 21 to 26, the outer peripheral portion is first applied, and then a time lag is provided for the chips 21 to 26.
Since the coating is performed on the upper surface 26, the first resin 40 sufficiently spreads to the portion directly below the wire 30, and can fill the gap between the wire 30 and the substrate 10.

【0027】また、上記製造方法によれば、第2の塗布
工程において第1の樹脂40よりも低粘度の第2の樹脂
50を用いて行い、塗布領域への樹脂の広がりを速くす
ることができるため、従来よりも塗布時間の短縮が図れ
る。また、第1の塗布工程では、ワイヤ30と基板10
との空隙を埋めるようにディスペンス方式で塗布するた
め、その塗布時間は、単位塗布面積当たりで考えれば従
来と同程度であるが、塗布領域がワイヤボンド実装部全
体ではなく、半導体チップ21〜26以外の部分である
ワイヤ30と基板10との接続部であるため、少ない領
域で済む。よって、第1及び第2の塗布工程を合わせた
塗布時間は、従来と同程度か従来よりも短い時間とな
る。
According to the above manufacturing method, the second coating step is performed using the second resin 50 having a lower viscosity than the first resin 40, so that the spread of the resin to the coating region can be accelerated. As a result, the coating time can be shortened as compared with the related art. In the first coating step, the wire 30 and the substrate 10
Is applied by a dispensing method so as to fill the gap between the semiconductor chips 21 to 26. Since it is a connection portion between the wire 30 and the substrate 10 which is a portion other than the above, only a small area is required. Therefore, the application time including the first and second application steps is equal to or shorter than the conventional one.

【0028】また、第1の塗布工程により、高粘度の第
1の樹脂40で半導体チップ21〜26の周囲部分を先
に囲んでしまうため、次に、第2の塗布工程にて、低粘
度の第2の樹脂50を塗布しても、第2の樹脂50が流
れだすのを抑制できる。従って、本実施形態によれば、
封止領域や塗布時間を増加させることなく、樹脂内にボ
イドが残らないようにワイヤボンド実装部に樹脂を塗布
することのできる樹脂封止型半導体装置の製造方法を提
供することができる。
Further, in the first coating step, the peripheral portions of the semiconductor chips 21 to 26 are first surrounded by the high-viscosity first resin 40. Even if the second resin 50 is applied, it is possible to suppress the second resin 50 from flowing out. Therefore, according to the present embodiment,
It is possible to provide a method of manufacturing a resin-encapsulated semiconductor device that can apply a resin to a wire bond mounting portion without increasing voids in the resin without increasing a sealing region and application time.

【0029】ところで、上記図1では、サイズが同程度
の整列した複数個のワイヤボンド実装部毎に、樹脂封止
を行うものであったが、複数個のワイヤボンド実装部を
一括して樹脂封止する場合でも、上記製造方法は適用可
能である。図3に、その一例を示す。図3では、各半導
体チップ21〜26が異なるサイズのもので、且つ、ラ
ンダムに配置されたものとなっている。
By the way, in FIG. 1 described above, resin sealing is performed for each of a plurality of wire bond mounting portions having substantially the same size and aligned. Even in the case of sealing, the above manufacturing method is applicable. FIG. 3 shows an example. In FIG. 3, the semiconductor chips 21 to 26 have different sizes and are arranged at random.

【0030】このような封止領域が大きい場合について
も、まず、第1の塗布工程(図3(a)、(b)参照)
にて、ワイヤ30と基板10との接続部に第1の樹脂
(斜線ハッチング部)40を、ディスペンサを用いて塗
布し、次に、第2の塗布工程(図3(c)参照)にて、
各チップ21〜26の中央部、及び、その他の第1の樹
脂40で囲まれた領域上に、第2の樹脂(点ハッチング
部)50をディスペンサを用いて塗布する。次に、硬化
工程を行い、半導体装置が完成する。 (他の実施形態)なお、第2の塗布工程を、印刷法によ
り行っても良い。具体的には、第2の樹脂50を溶剤等
に溶かした溶液状態とし、半導体チップ21〜26の直
上を開口するように基板10をマスク部材等でマスキン
グし、前記溶液をスキージ等を用いて塗布すればよい。
この場合、印刷に用いられる第2の樹脂50は、第1の
樹脂40と粘度が同じでも異なるものでも良い。
Even in the case where the sealing region is large, first, the first coating step (see FIGS. 3A and 3B)
Then, a first resin (hatched portion) 40 is applied to a connection portion between the wire 30 and the substrate 10 using a dispenser, and then in a second application step (see FIG. 3C). ,
A second resin (dot hatched portion) 50 is applied using a dispenser on the central portion of each of the chips 21 to 26 and the other region surrounded by the first resin 40. Next, a curing step is performed to complete the semiconductor device. (Other Embodiments) The second application step may be performed by a printing method. Specifically, the second resin 50 is made into a solution state in which the second resin 50 is dissolved in a solvent or the like, the substrate 10 is masked with a mask member or the like so as to open directly above the semiconductor chips 21 to 26, and the solution is squeezed or the like. What is necessary is just to apply.
In this case, the second resin 50 used for printing may have the same or different viscosity as the first resin 40.

【0031】また、第2の塗布工程を、市販されている
ような樹脂の固形物(固形ペレット)を用いて行っても
良い。これは、第2の樹脂50よりなる固形ペレットを
半導体チップ21〜26上に配置し加熱等により溶融さ
せ、第1の樹脂40と一体化させることで可能である。
これら印刷法及び固形ペレットを用いた第2の塗布工程
においては、ディスペンス方式に比べて、第2の樹脂5
0の塗布面積の大小にそれほど影響されることなく塗布
がなされるため、塗布時間の短縮が図れる。
Further, the second coating step may be performed using a solid resin (solid pellet) of a commercially available resin. This can be achieved by disposing solid pellets made of the second resin 50 on the semiconductor chips 21 to 26, melting them by heating or the like, and integrating them with the first resin 40.
In the printing method and the second application step using the solid pellets, the second resin 5 is used in comparison with the dispensing method.
Since the coating is performed without being greatly affected by the size of the coating area of 0, the coating time can be shortened.

【0032】また、半導体装置としては、ワイヤボンド
実装部、つまり半導体チップが1個のものであっても、
本発明は同様に適用可能である。
Further, as a semiconductor device, even if a wire bond mounting portion, that is, one semiconductor chip is used,
The invention is equally applicable.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態に係る樹脂封止型半導体装置
の製造方法を示す工程図である。
FIG. 1 is a process chart showing a method for manufacturing a resin-sealed semiconductor device according to an embodiment of the present invention.

【図2】上記実施形態に係る樹脂封止型半導体装置を示
す概略断面図である。
FIG. 2 is a schematic sectional view showing a resin-sealed semiconductor device according to the embodiment.

【図3】上記実施形態に係る樹脂封止型半導体装置の製
造方法の他の例を示す工程図である。
FIG. 3 is a process chart showing another example of the method for manufacturing the resin-sealed semiconductor device according to the embodiment.

【図4】従来の一般的な樹脂封止型半導体装置を示す概
略断面図である。
FIG. 4 is a schematic sectional view showing a conventional general resin-sealed semiconductor device.

【図5】従来の樹脂封止型半導体装置の製造方法を示す
工程図である。
FIG. 5 is a process chart showing a method for manufacturing a conventional resin-encapsulated semiconductor device.

【図6】樹脂封止型半導体装置におけるボイド発生を説
明する説明図である。
FIG. 6 is an explanatory diagram illustrating void generation in a resin-sealed semiconductor device.

【符号の説明】[Explanation of symbols]

10…基板、21〜26…半導体チップ、30…ワイ
ヤ、40…第1の樹脂、50…第2の樹脂。
DESCRIPTION OF SYMBOLS 10 ... board | substrate, 21-26 ... semiconductor chip, 30 ... wire, 40 ... 1st resin, 50 ... 2nd resin.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板(10)上に半導体素子(21〜2
6)を搭載し、ワイヤボンディングを行うことにより、
前記半導体素子と前記基板とをワイヤ(30)にて結線
した後、樹脂にて前記半導体素子及び前記ワイヤを包み
込むように封止する半導体装置の製造方法において、 前記ワイヤボンディングを行った後、前記ワイヤと前記
基板との間隙を埋めるように、前記ワイヤと前記基板と
の接続部に第1の樹脂(40)を、ディスペンサを用い
て塗布する第1の塗布工程と、 この第1の塗布工程の後、前記半導体素子上に、前記第
1の樹脂の塗布時における状態よりも低粘度とした状態
で第2の樹脂(50)を、ディスペンサを用いて塗布す
る第2の塗布工程と、 続いて、塗布された前記第1及び第2の樹脂を硬化させ
る硬化工程とを備えることを特徴とする半導体装置の製
造方法。
A semiconductor device (21 to 2) is provided on a substrate (10).
6), and by performing wire bonding,
In a method for manufacturing a semiconductor device in which the semiconductor element and the substrate are connected by a wire (30), and then the semiconductor element and the wire are encapsulated by a resin, the method includes the steps of: A first application step of applying a first resin (40) to a connection portion between the wire and the substrate by using a dispenser so as to fill a gap between the wire and the substrate; and a first application step. After that, a second application step of applying a second resin (50) on the semiconductor element with a dispenser in a state where the second resin (50) has a lower viscosity than the state at the time of application of the first resin, And a curing step of curing the applied first and second resins.
【請求項2】 前記第2の塗布工程では、前記第1の塗
布工程に用いた前記ディスペンサよりもニードル径の大
きいディスペンサを用いて前記第2の樹脂(50)を塗
布することを特徴とする請求項1に記載の半導体装置の
製造方法。
2. In the second application step, the second resin (50) is applied using a dispenser having a larger needle diameter than the dispenser used in the first application step. A method for manufacturing a semiconductor device according to claim 1.
【請求項3】 基板(10)上に半導体素子(21〜2
6)を搭載し、ワイヤボンディングを行うことにより、
前記半導体素子と前記基板とをワイヤ(30)にて結線
した後、樹脂にて前記半導体素子及び前記ワイヤを包み
込むように封止する半導体装置の製造方法において、 前記ワイヤボンディングを行った後、前記ワイヤと前記
基板との間隙を埋めるように、前記ワイヤと前記基板と
の接続部に第1の樹脂(40)を、ディスペンサを用い
て塗布する第1の塗布工程と、 この第1の塗布工程の後、前記半導体素子上に、第2の
樹脂(50)を印刷法により塗布する第2の塗布工程
と、 続いて、塗布された前記第1及び第2の樹脂を硬化させ
る硬化工程とを備えることを特徴とする半導体装置の製
造方法。
3. A semiconductor device (21 to 2) on a substrate (10).
6), and by performing wire bonding,
A method of manufacturing a semiconductor device in which the semiconductor element and the substrate are connected by a wire (30), and then the semiconductor element and the wire are sealed so as to surround the semiconductor element and the wire; A first application step of applying a first resin (40) to a connection portion between the wire and the substrate by using a dispenser so as to fill a gap between the wire and the substrate; and a first application step. Thereafter, a second application step of applying a second resin (50) on the semiconductor element by a printing method, and a curing step of curing the applied first and second resins are described below. A method for manufacturing a semiconductor device, comprising:
【請求項4】 基板(10)上に半導体素子(21〜2
6)を搭載し、ワイヤボンディングを行うことにより、
前記半導体素子と前記基板とをワイヤ(30)にて結線
した後、樹脂にて前記半導体素子及び前記ワイヤを包み
込むように封止する半導体装置の製造方法において、 前記ワイヤボンディングを行った後、前記ワイヤと前記
基板との間隙を埋めるように、前記ワイヤと前記基板と
の接続部に第1の樹脂(40)を、ディスペンサを用い
て塗布する第1の塗布工程と、 この第1の塗布工程の後、固形状とした第2の樹脂(5
0)を前記半導体素子上に配置した後、溶融させること
により、前記第2の樹脂を前記半導体素子上に塗布する
第2の塗布工程と、 続いて、塗布された前記第1及び第2の樹脂を硬化させ
る硬化工程とを備えることを特徴とする半導体装置の製
造方法。
4. A semiconductor device (21 to 2) on a substrate (10).
6), and by performing wire bonding,
A method of manufacturing a semiconductor device in which the semiconductor element and the substrate are connected by a wire (30), and then the semiconductor element and the wire are sealed so as to surround the semiconductor element and the wire; A first application step of applying a first resin (40) to a connection portion between the wire and the substrate by using a dispenser so as to fill a gap between the wire and the substrate; and a first application step. After that, the solidified second resin (5
0) is disposed on the semiconductor element and then melted to apply the second resin onto the semiconductor element. Subsequently, the applied first and second resins are applied. And a curing step of curing the resin.
JP11114132A 1999-04-21 1999-04-21 Manufacture of semiconductor device Pending JP2000306932A (en)

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JP11114132A JP2000306932A (en) 1999-04-21 1999-04-21 Manufacture of semiconductor device

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JP2000306932A true JP2000306932A (en) 2000-11-02

Family

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005242032A (en) * 2004-02-26 2005-09-08 Kyocera Corp Display device
WO2006079104A2 (en) * 2005-01-24 2006-07-27 Spatialight, Inc. Encapsulation of circuit components to reduce thermal cycling stress
JP2009295964A (en) * 2008-05-07 2009-12-17 Panasonic Corp Electronic component and resin packaging method for electronic component
JP2011035334A (en) * 2009-08-06 2011-02-17 Panasonic Corp Semiconductor device
CN104779194A (en) * 2014-01-14 2015-07-15 北大方正集团有限公司 PN junction isolation structure and manufacturing method thereof
KR102110143B1 (en) * 2019-11-25 2020-05-13 테라셈 주식회사 Image sensor package and manufacturing method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005242032A (en) * 2004-02-26 2005-09-08 Kyocera Corp Display device
JP4562403B2 (en) * 2004-02-26 2010-10-13 京セラ株式会社 Manufacturing method of display device
WO2006079104A2 (en) * 2005-01-24 2006-07-27 Spatialight, Inc. Encapsulation of circuit components to reduce thermal cycling stress
WO2006079104A3 (en) * 2005-01-24 2006-08-24 Spatialight Inc Encapsulation of circuit components to reduce thermal cycling stress
JP2009295964A (en) * 2008-05-07 2009-12-17 Panasonic Corp Electronic component and resin packaging method for electronic component
JP2011035334A (en) * 2009-08-06 2011-02-17 Panasonic Corp Semiconductor device
CN104779194A (en) * 2014-01-14 2015-07-15 北大方正集团有限公司 PN junction isolation structure and manufacturing method thereof
KR102110143B1 (en) * 2019-11-25 2020-05-13 테라셈 주식회사 Image sensor package and manufacturing method thereof

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