JP2000304785A - Circuit and method for detecting phase difference - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase difference detecting circuit which can detect a signal having a large phase difference, such as the wander of a high-frequency signal, with high resolution by means of a lower-speed circuit element by constituting the circuit by combining a low-speed phase counting circuit with a high- resolution phase counting circuit, and a method for detecting phase difference. SOLUTION: The phase difference detecting circuit detects the phase-counted result corresponding to the phase difference detected by means of a phase comparator circuit 2 and a phase counting circuit 3 and the phase difference, which has not been detected by means of the counting circuit 3, with high resolution by means of a high-resolution phase counting circuit 5 of the poststage. Thereby, the circuit 1 which can operate at a frequency lower than that of a received extracted clock signal inputted from a transmission system to be measured can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase difference detection circuit and a phase difference detection method suitable for measuring transmission quality in a transmission apparatus or a backbone network compatible with a high-speed digital communication system.

[0002]

2. Description of the Related Art In recent years, with the rapid increase in demand for information communication, there is an urgent need to develop a communication technology that can respond to an increase in transmission speed and an increase in transmission capacity. There is also a demand for the establishment of a measurement technique for evaluating such a communication technique.As a measurement technique for evaluating the transmission quality in a transmission system such as a transmission apparatus or a backbone network corresponding to a high-speed digital communication system, for example, A phase difference detection technique for detecting jitter (high frequency component) or wander (low frequency component), which is a phase fluctuation component generated in a transmission system, is important.

As a conventional phase difference detection circuit for detecting jitter or wander, there is a circuit which uses a counter circuit and outputs a phase difference between a reference clock signal and a reception extraction clock signal to be measured as a count value.

[0004]

However, in a phase difference detection circuit using a conventional counter circuit, a phase difference having a large phase difference such as a wander of a high-frequency signal of a GHz level used in a high-speed digital communication system. In order to detect a signal with high resolution, a higher processing speed and a larger bit length are required, so that it has been difficult to form a signal only with a counter circuit.

[0005] An object of the present invention is to combine a low-speed phase count circuit and a high-resolution phase count circuit to form a signal having a large phase difference such as a wander of a high-frequency signal with a lower-speed circuit element. An object of the present invention is to provide a phase difference detection circuit and a phase difference detection method that enable detection with a resolution.

[0006]

According to a first aspect of the present invention, there is provided a phase difference detecting circuit for comparing a phase of a reference clock signal with a phase of a received clock signal and outputting a first phase difference signal. , A phase comparison circuit 1), counts a predetermined number of clocks included in the first phase difference signal output from the phase comparison circuit, outputs a first phase count result, and outputs the phase difference A first phase counting circuit (for example, phase counting circuit 3) for outputting a signal as a second phase difference signal, and a predetermined phase included in the second phase difference signal output from the first phase counting circuit. A second phase counting circuit (eg, a high-resolution phase counting circuit 5) that counts the number of clocks and outputs a second phase counting result; and a first phase counting result output from the first phase counting circuit. And the second phase counting cycle The second phase counting result and the adds and outputs a phase difference detection result adding circuit output from (e.g., an adder 4) is characterized by comprising a, a.

According to the phase difference detection circuit of the present invention, the phase comparison circuit compares the phases of the reference clock signal and the reception clock signal and outputs a first phase difference signal. The phase counting circuit counts a predetermined number of clocks included in the first phase difference signal output from the phase comparison circuit, outputs a first phase counting result, and outputs the phase difference signal whose counting has been omitted. Output as a second phase difference signal,
A second phase counting circuit that counts a predetermined number of clocks included in the second phase difference signal output from the first phase counting circuit and outputs a second phase counting result; ,
A first phase counting result output from the first phase counting circuit and a second phase counting result output from the second phase counting circuit are added to output a phase difference detection result.

According to a fourth aspect of the present invention, there is provided a phase difference detecting method comprising:
A phase comparing step of comparing the phase difference between the reference clock signal and the received clock signal to output a first phase difference signal, and a predetermined clock included in the first phase difference signal output in the phase comparing step A first phase counting step of counting the number and outputting a first phase counting result, and outputting the phase difference signal whose counting has been omitted as a second phase difference signal; and a first phase counting step of outputting the first phase counting result. A second phase counting step of counting a predetermined number of clocks included in the second phase difference signal and outputting a second phase counting result; and a first phase counting step of outputting the first phase counting signal. An adding step of adding the phase counting result and the second phase counting result output in the second phase counting step to output a phase difference detection result.

According to the phase difference detecting method of the present invention, the first phase difference signal is output by comparing the phase difference between the reference clock signal and the received clock signal in the phase comparing step. Counting a predetermined number of clocks included in the first phase difference signal output by the phase comparing step in the phase counting step, and outputting a first phase counting result;
The phase difference signal whose count has been omitted is output as a second phase difference signal, and the predetermined number of clocks included in the second phase difference signal output by the first phase counting step is counted by the second phase counting step. And outputs a second phase counting result. The first phase counting result output by the first phase counting step by the adding step and the second phase counting result output by the second phase counting step. The result is added to output a phase difference detection result.

Therefore, by using the phase difference detection circuit and the phase difference detection method, it is possible to detect the phase difference generated in the transmission system with high resolution. For example, a transmission system compatible with a high-speed digital communication system can be used. Can be detected with a high resolution.

In this case, as in the second aspect of the present invention, in the phase difference detecting circuit according to the first aspect, the second phase counting circuit is output from the first phase counting circuit. A delay circuit (for example, fixed delay units 501 to 503) that outputs a plurality of phase delay signals obtained by sequentially delaying the phase of the second phase difference signal by a plurality of stages of fixed delay units;
A sampling circuit (for example, flip-flops 511 to 513) that samples a plurality of phase delay signals output from the delay circuit at a predetermined sampling timing and outputs a series of sampling data; and a sampling data output from the sampling circuit. Data counting circuit (for example, encoders 521 to 521) that counts the delay data included in the data and outputs the second phase counting result.
523 and an adder 531).

According to the phase difference detecting circuit of the second aspect of the present invention, in the second phase counting circuit, the delay circuit includes a delay circuit for detecting the second phase difference signal output from the first phase counting circuit. A plurality of phase delay signals whose phases are sequentially delayed by a plurality of stages of fixed delay means are output, and a sampling circuit samples the plurality of phase delay signals output from the delay circuit at a predetermined sampling timing and performs a series of sampling. The data is output, and the delay data counting circuit counts the delay data included in the sampling data output from the sampling circuit and outputs the second phase counting result.

[0013] In this case, as in the invention described in claim 5, in the phase difference detection method according to claim 4, the second phase counting step is output by the first phase counting step. A delay step of outputting a plurality of phase delay signals in which the phase of the second phase difference signal is sequentially delayed by a plurality of stages of fixed delay means, and a plurality of phase delay signals output by the delay step are output at a predetermined sampling timing. A sampling step of sampling and outputting a series of sampling data; and a delay data counting step of counting delay data included in the sampling data output in the sampling step and outputting the second phase counting result. It is effective to include further.

According to a fifth aspect of the present invention, in the phase difference detecting method, the second phase counting step includes the step of delaying the phase of the second phase difference signal output in the first phase counting step. A plurality of phase delay signals sequentially delayed by a plurality of stages of fixed delay means, and a plurality of phase delay signals output by the delay step are sampled at a predetermined sampling timing by a sampling step to output a series of sampling data. In the delay data counting step, the delay data included in the sampling data output in the sampling step is counted, and the second phase counting result is output.

Therefore, it is possible to realize a phase difference detection circuit which operates at a frequency lower than the frequency of the reception clock signal and detects the phase difference with high resolution. By increasing the number of connection stages of the fixed delay means and the sampling circuit, the speed can be reduced. It is possible to detect a higher-speed phase difference of the received clock signal with high resolution while maintaining the operation.

According to a third aspect of the present invention, in the phase difference detecting circuit according to the second aspect, the sampling circuit samples the plurality of phase delay signals a plurality of times at a predetermined sampling timing to form a series. The sampling data is output a plurality of times, and the delay data counting circuit counts each delay data included in each sampling data output a plurality of times from the sampling circuit and outputs the second phase counting result. It is valid.

According to the phase difference detection circuit of the invention, the sampling circuit samples the plurality of phase delay signals a plurality of times at a predetermined sampling timing and outputs a series of sampling data a plurality of times. ,
The delay data counting circuit counts each delay data included in each sampling data output a plurality of times from the sampling circuit and outputs the second phase counting result.

Further, as in the invention described in claim 6,
6. The phase difference detection method according to claim 5, wherein the sampling step samples the plurality of phase delay signals a plurality of times at a predetermined sampling timing and outputs a series of sampling data a plurality of times. It is effective to count each delay data included in each sampling data output a plurality of times in the sampling step and output the second phase counting result.

According to the phase difference detecting method of the present invention, in the sampling step, the plurality of phase delay signals are sampled a plurality of times at a predetermined sampling timing to output a series of sampling data a plurality of times. ,
The delay data counting step counts each delay data included in each sampling data output a plurality of times in the sampling step, and outputs the second phase counting result.

Therefore, the detection accuracy of the phase difference included in the received clock signal can be improved.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 to 5 are diagrams showing one embodiment of a phase difference detection circuit to which the present invention is applied.

First, the configuration will be described. FIG. 1 is a block diagram illustrating a circuit configuration of a phase difference detection circuit 1 according to the present embodiment. In FIG. 1, the phase difference detection circuit 1 includes a phase comparison circuit 2, a phase counting circuit 3, an adder 4, and a high-resolution phase counting circuit 5.

The phase comparison circuit 2 compares the phase of a reference clock signal input from an external oscillator (not shown) with the phase of a received extraction clock signal input from an external transmission system (not shown) to be measured. The phase difference signal as the comparison result is output to the phase counting circuit 3.

The phase count circuit 3 samples the phase difference signal input from the phase comparison circuit 2 using an internal clock signal, and uses the number of internal clocks included in the sampling period of the phase difference signal as a phase count result as an adder 4. And outputs the phase portion of the phase difference signal leaked from the sampling timing to the high-resolution phase counting circuit 5 as a phase difference signal.

The adder 4 adds the phase count result input from the phase count circuit 3 and the phase count result input from the high-resolution phase count circuit 5, and receives numerical data as the addition result. The extracted clock signal is output as a phase difference detection result.

As shown in FIG. 2, the high-resolution phase counting circuit 5 includes a plurality of fixed delay units 501 to 503,.
And a plurality of flip-flops (FF) 511 to 513,
.., A plurality of encoders 521 to 523, and an adder 531.

The fixed delay section 501 includes a phase count circuit 3
Is delayed by a predetermined fixed phase difference (for example, 1-bit data) and output to the flip-flop 512 and the fixed delay unit 502. Fixed delay section 502 further delays the delay signal input from fixed delay section 501 by a predetermined fixed phase difference, and outputs the delayed signal to flip-flop 513 and fixed delay section 503. The fixed delay unit 503 further delays the delay signal input from the fixed delay unit 502 by a preset fixed phase difference, and outputs the delayed signal to a next-stage flip-flop (not shown) and a fixed delay unit.

In FIG. 2, the fixed delay units 501 to 501
Although illustration of the number of connection stages between the 503 and the flip-flops 511 to 513 is omitted, the number of stages corresponding to the number of resolutions for detecting a phase difference is required. As shown in (5), a 9-stage fixed delay section and 10-stage flip-flops are required so that the phase difference of the phase difference signal is counted with a resolution of 10 bits.

Flip-flops 511 to 51 for ten stages
.. Represent the phase difference signal input from the phase counting circuit 3 and the nine fixed delay units 501 to 503.
.. each fixed delay output from each stage of × n (n: 1 to 1)
9) The signal is sampled at the same sampling timing based on the high-speed internal clock signal, and the sampled phase difference signal and each fixed delay × n
(N: 1 to 9) 2 for 10 bits composed of
The value data is sequentially output to the encoders 521 to 523 at an output timing corresponding to the sampling timing.

The encoder 521 includes a flip-flop 5
.. Composed of a phase difference signal sampled and input at 11-513,... At the first sampling timing and each fixed delay × n (n: 1-9) signal
Count the number of "1" included in the binary data for bits,
The counting result is encoded and output to the adder 531.

The encoder 522 includes a flip-flop 5
.. Composed of a phase difference signal sampled and input at 11 and 513,... At an intermediate sampling timing and each fixed delay × n (n: 1 to 9) signals.
Count the number of "1" included in the binary data for bits,
The counting result is encoded and output to the adder 531.

The encoder 523 includes a flip-flop 5
.. Composed of phase difference signals sampled and input at the final sampling timing and fixed fixed delay × n (n: 1 to 9) signals from 11 to 513,.
Count the number of "1" included in the binary data for bits,
The counting result is encoded and output to the adder 531.

The above-described first sampling timing, intermediate sampling timing, and final sampling timing are shown in the timing chart of FIG. 5 referred to in the description of the operation of the high-resolution phase counting circuit 5 described later.

The adder 531 includes encoders 521 to 52
3 and adds the count values respectively input thereto, and outputs the result to the adder 4 as a phase count result.

Next, the operation of this embodiment will be described. First, the operation of the phase comparison circuit 2 of FIG. 1 will be described with reference to the timing chart shown in FIG. 3A shows a reference clock signal input from an external oscillator (not shown), FIG. 3B shows a reception extraction clock signal input from an external transmission system (not shown), and FIG. Is a phase difference signal output from the phase comparison circuit 2.

The phase comparison circuit 2 converts the rising edge (“Lo” → “Hi”) of the reference clock signal shown in FIG. 3 (a) to the rising edge (“Lo” →→ ”) of the received extracted clock signal shown in FIG. 3 (b).
The phase difference up to “Hi”) is output to the phase counting circuit 3 as a phase difference signal shown in FIG.

Next, the operation of the phase counting circuit 3 will be described with reference to the timing chart shown in FIG. 4A shows a phase difference signal input from the phase comparison circuit 2, FIG. 4B shows an internal clock signal, FIG. 4C shows a phase count result output from the phase count circuit 3, (D) is a phase difference signal output from the phase counting circuit 3.

The phase counting circuit 3 converts the phase difference signal of FIG. 4A input from the phase comparing circuit 2 into the phase difference signal of FIG.
(C) which is the number of internal clocks included in the sampling period of the phase difference signal at the rising (“Lo” → “Hi”) timing of the internal clock signal of FIG.
The phase count result "1" or "2" is output to the adder 4 as a binary number "1" or "10", and the phase portion of the phase difference signal leaked from the sampling timing is shown in FIG. It is output to the high-resolution phase counting circuit 5 as a phase difference signal.

Next, the operation of the high-resolution phase counting circuit 5 will be described with reference to the timing chart shown in FIG. 5A shows a phase difference signal input from the phase counting circuit 3, and FIGS.
(E) is a fixed delay signal in each fixed delay stage of the phase difference signal, (f) is a high-speed internal clock signal,
(G) shows each count value output from the encoders 521 to 523 at the first, middle, and final sampling timings and the encoded output.

The high-resolution phase counting circuit 5 sequentially delays the phase of the phase difference signal shown in FIG. 5A from the phase counting circuit 3 by nine stages of fixed delay units 501 to 503,. Then, the phase difference signal + fixed delay × n (n: 1 to 9) signals shown in FIGS. 8B to 8E are replaced with a phase difference signal and each phase difference signal + fixed delay × n signal by 10 flip-flops. , And further, flip-flops 511-513,..., And the phase difference signals input from the fixed delay units 501-503,. (F)
Rising edge of the high-speed internal clock signal (“Lo” → “H”)
i ″) Simultaneously sample at the timing.

At this time, flip-flops 511-51
.. Represent the high-speed internal clock signal 3 in FIG.
At each rising timing of the clock, the first sampling timing, the halfway sampling timing, and the last sampling timing indicated by the dashed arrow in FIG.
A fixed delay × n signal is sampled.

That is, the phase difference signal sampled at the first sampling timing and each phase difference signal +
The fixed delay × n signal is a 10-bit 2 signal shown in FIG.
Encoder 5 as value data "1000000000000"
21 and the phase difference signal and each phase difference signal + fixed delay × n signal sampled at an intermediate sampling timing are output to the encoder 522 as 10-bit binary data “1111111111” shown in FIG. , The phase difference signal sampled at the final sampling timing and each phase difference signal + fixed delay × n
The signal is the 10-bit binary data “0” shown in FIG.
000000001 ”to the encoder 523.

The encoder 521 includes a flip-flop 5
.. Are encoded from the 10-bit binary data “1000000000000” input at the first sampling timing from 11 to 513,..., And “1” shown in FIG. Output to the device 531.

The encoder 522 includes a flip-flop 5
11 to 513, ..., the number of "1" is encoded from the input 10-bit binary data "1111111111" sampled at an intermediate sampling timing and "10" shown in FIG. 5 (g) is added. Output to the device 531.

The encoder 523 includes the flip-flop 5
.. Are encoded from the 10-bit binary data “00000000001” input from 11-513,... At the final sampling timing, and “1” shown in FIG. Output to the device 531.

The adder 531 includes encoders 521 to 52
3, the encoded values "1" and "1"
"12" obtained by adding "0" and "1" to the binary number "110"
It is output to the adder 4 of FIG. 1 as a phase count result of "0".

The adder 4 adds the phase count result “1” or “10” input from the phase count circuit 3 and the phase count result “1100” input from the high-resolution phase count circuit 5, and adds the result. Addition result "110
"1" or "1110" is output to an external display device or the like as a phase difference detection value to display the phase difference detection value of the received extracted clock signal.

For example, in the case of a received extraction clock signal of 1 GHz (gigahertz), the phase difference detection circuit 1 of the present embodiment uses a clock that is 1/10 of the clock, 100.
By operating at MHz (megahertz), a phase difference can be detected on the order of nsec with a high resolution of 10 bits.

Therefore, in the phase difference detecting circuit 1 of the present embodiment, the phase comparing circuit 2 and the phase counting circuit 3
A phase count result corresponding to the phase difference detected by
The phase difference not detected by the phase counting circuit 3 can be detected at a high resolution by the high-resolution phase counting circuit 5 at the subsequent stage, so that the phase difference is higher than the frequency of the reception extraction clock signal input from the transmission system to be measured. A phase difference detection circuit that operates at a low frequency can be realized.

As a result, by using the phase difference detection circuit 1 of this embodiment, it is possible to detect wander generated in a transmission system compatible with a high-speed digital communication system with high resolution.

Although the high-resolution phase counting circuit 5 has a resolution of 10 bits in the phase difference detecting circuit 1 in the above-described embodiment, the high-speed phase counting circuit 5 has a low-speed operation by increasing the number of connection stages of the fixed delay unit and the flip-flop. While maintaining the operation, it is possible to detect the phase difference of the higher-speed reception / extraction clock signal with high resolution.

Therefore, in the circuit configuration of the phase difference detection circuit 1, by changing the number of fixed delay stages and the number of latch stages of the high-resolution phase counting circuit 5, wander generated in a transmission system compatible with a high-speed digital communication system of various frequencies. Can be easily realized with a phase difference detection circuit for detecting the phase difference at a high resolution.

[0053]

According to the first aspect of the present invention, there is provided a phase difference detecting circuit,
According to the phase difference detection method according to the fourth aspect, by using the present phase difference detection circuit and the phase difference detection method, it is possible to detect a phase difference generated in a transmission system with high resolution. Wander or the like, which is a phase fluctuation generated in a transmission system compatible with a high-speed digital communication system, can be detected with high resolution.

According to the phase difference detecting circuit of the present invention and the phase difference detecting method of the present invention, the phase difference detecting circuit operates at a frequency lower than the frequency of the received clock signal and detects the phase difference with high resolution. Phase detection circuit that can be realized, and by increasing the number of connection stages of the fixed delay means and the sampling circuit, it is possible to detect a phase difference of a higher-speed reception clock signal with high resolution while maintaining low-speed operation. Become.

According to the phase difference detection circuit of the third aspect and the phase difference detection method of the sixth aspect, it is possible to improve the detection accuracy of the phase difference included in the received clock signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a phase difference detection circuit 1 according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration in a high-resolution phase counting circuit 5 of FIG.

FIG. 3 is a timing chart for explaining an operation in the phase comparison circuit 2 of FIG. 1;

FIG. 4 is a timing chart for explaining an operation in the phase counting circuit 3 of FIG. 1;

FIG. 5 is a timing chart for explaining an operation in the high-resolution phase counting circuit 5 of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase difference detection circuit 2 Phase comparison circuit 3 Phase count circuit 4 Adder 5 High resolution phase count circuit 501-503 Fixed delay unit 511-513 Flip-flop 521-523 Encoder 531 Adder

Claims (6)

[Claims] 1. A phase comparison circuit for comparing a phase of a reference clock signal with a phase of a reception clock signal and outputting a first phase difference signal, wherein the phase comparison circuit includes a first phase difference signal output from the phase comparison circuit. A first phase counting circuit that counts the predetermined number of clocks and outputs a first phase count result, and outputs a phase difference signal whose count has been omitted as a second phase difference signal; A second phase counting circuit that counts a predetermined number of clocks included in the second phase difference signal output from the circuit and outputs a second phase counting result; and a second phase counting circuit that outputs the second phase counting result. An adding circuit for adding the first phase counting result and the second phase counting result output from the second phase counting circuit to output a phase difference detection result. Phase difference detection circuit. 2. The method according to claim 1, wherein the second phase counting circuit includes a plurality of phase delay signals obtained by sequentially delaying the phase of the second phase difference signal output from the first phase counting circuit by a plurality of stages of fixed delay means. A sampling circuit that outputs a series of sampling data by sampling a plurality of phase delay signals output from the delay circuit at a predetermined sampling timing, and includes a sampling data output from the sampling circuit. The phase difference detection circuit according to claim 1, further comprising: a delay data counting circuit that counts the obtained delay data and outputs the second phase count result. 3. The sampling circuit samples a plurality of phase delay signals a plurality of times at a predetermined sampling timing, and outputs a series of sampling data a plurality of times. 3. The phase difference detection circuit according to claim 2, wherein each delay data included in each output sampling data is counted and the second phase counting result is output. 4. A phase comparison step of comparing a phase difference between a reference clock signal and a reception clock signal to output a first phase difference signal; and the first phase difference signal output in the phase comparison step is included in the first phase difference signal. Counting the predetermined number of clocks, and outputs a first phase counting result, and outputs the phase difference signal whose count has been omitted to the second phase counting signal.
A first phase counting step of outputting as a phase difference signal, and a second phase counting result by counting a predetermined number of clocks included in the second phase difference signal output by the first phase counting step. A second phase counting step of outputting the first phase counting result, and adding the first phase counting result output by the first phase counting step and the second phase counting result output by the second phase counting step. Adding a phase difference detection result to the phase difference detection result. 5. The method according to claim 1, wherein the second phase counting step includes a step of sequentially delaying a phase of the second phase difference signal output in the first phase counting step by a plurality of stages of fixed delay means. A sampling step of sampling a plurality of phase delay signals output by the delay step at a predetermined sampling timing and outputting a series of sampling data; and a sampling step included in the sampling data output by the sampling step. 5. The phase difference detecting method according to claim 4, further comprising: a delay data counting step of counting the obtained delay data and outputting the second phase counting result. 6. The sampling step includes sampling the plurality of phase-delay signals a plurality of times at a predetermined sampling timing and outputting a series of sampling data a plurality of times. 6. The phase difference detecting method according to claim 5, wherein each of the delay data included in each of the output sampling data is counted and the second phase counting result is output.