JP2000299471A - Thin-film transistor and optoelectronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor having satisfactory characteristics. SOLUTION: A thin-film transistor formed on the surface of an insulating substrate is provided with a crystalline semiconductor containing source regions, drain regions, and channel forming regions 7 and 7' formed between the source regions and drain regions, gate electrodes 4 and 4', and gate insulating films 3 and 3' between the channel forming regions 7 and 7' and gate electrodes 4 and 4'. To total amount of oxygen, nitrogen, and carbon contained in the channel forming regions 7 and 7' is adjusted to 1×1020 cm-3 to 20 atm.%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor (hereinafter referred to as a TFT) having a thin film structure used for an active type liquid crystal display device or an image sensor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an active liquid crystal display device using a TFT has been known. In this case, an amorphous or polycrystalline semiconductor having crystal grain boundaries is used for the TFT.
A TFT of only one of the P and N conductivity types is used for one pixel. That is, in general, an N-channel TFT (NTFT
Is connected in series to the pixel.

However, a semiconductor having an amorphous structure has a low carrier mobility, and in particular, a hole has a carrier mobility of 0.1.
As small as 1 cm ² / Vsec or less. Also, semiconductors with a polycrystalline structure
There are drawbacks that the drain breakdown voltage cannot be sufficiently increased due to impurities such as oxygen segregated at the crystal grain boundaries and dangling bonds, and it is difficult to form a P-channel TFT. Furthermore, they have light sensitivity (called photosensitivity PS),
There is a disadvantage that Vg- _ID (gate voltage-drain current) characteristics and the like are greatly changed by light irradiation.

Therefore, it is an important step to form a light shielding layer so that light is not irradiated to the channel forming region.

[0005]

In FIG. 3, the liquid crystal (1
2), and an NTFT (11) is provided in series with it and arranged in a matrix. Generally 640
In this drawing, a 2 × 2 matrix arrangement was simply used in the same meaning as in the case of × 480 or 1260 × 960. A voltage is applied to each pixel from the peripheral circuits (16) and (17), a predetermined pixel is selectively turned on, and the other pixels are turned off. Then, when the on / off characteristics of the TFT are generally good, a liquid crystal display device having a high contrast can be manufactured. However, when actually manufacturing such a liquid crystal display device, when the output of the TFT, that is, the voltage V _LC (10) of the input to the liquid crystal (referred to as liquid crystal potential) is often set to “1” (High) when it should be set to “1” (High). Sometimes it does not become "(High), and conversely, it does not become" 0 "(Low) when it should become" 0 "(Low). The liquid crystal (12) is inherently insulating in its operation, and the liquid crystal potential (V _LC ) floats when the TFT is off. Since the liquid crystal 12 is equivalently a capacitor, _VLC is determined by the electric charge stored therein. This charge is leaked through the TFT channel when the light is not adequately shielded, because conventional TFTs are photosensitive.
(15), and as a result, the level of _VLC fluctuates. Furthermore, the liquid crystal becomes relatively small in resistance due to _RLC , and the leakage occurs.
If the step (14) occurs, _VLC will be in an incomplete state. Therefore, in a liquid crystal display device having 200,000 to 5 million pixels in one panel, a high yield cannot be achieved.

[0006]

According to the present invention, a thin film insulated gate field effect transistor is made non-photosensitive. Also, the source and drain are more P ⁺ or N ⁺
It is intended to be. In an active type liquid crystal display device as an application thereof, the liquid crystal potential is reduced by one frame.
This is a TFT that is constantly maintained at the same value as the initial value during the system, and keeps the predetermined level, so that the level does not drift.

According to the present invention, the semiconductor material in the channel forming region of the TFT is made of a material which is insensitive to light.
The silicon is formed by selectively adding oxygen, carbon or nitrogen impurities to the channel forming region of T 1, and the region has crystallinity but has no photosensitivity. The source and drain constituting the pair of impurity regions are not doped with or less than the impurity, thereby improving the ionization rate of the P or N type conductivity type impurity.

The total amount of impurities of O, C, and N is selectively reduced to 1 × 10 ²⁰ cm ^{-3 to} 20 by ion implantation or the like in the channel forming region.
Atomic%, preferably 3 × 10 ²⁰ cm ^{-3 to} 5 atomic%, renders it non-photosensitive, but 500 to 750
Crystallized by a heat treatment at a temperature of 5 ° C., so as to have a carrier mobility of 5 cm ² / Vsec or more.
In addition, it is a semiconductor material having crystallinity.

This material is non-photosensitive, that is, a current change in the on state is 10% or less, and a dark current in the off state (sub-threshold state) of 10 ^-9 A is 10%. ^-7
Intensity less than the order of A, that is, the degree of change is reduced to two digits or less.
This was achieved by irradiating with 00 candela visible light.

When the present invention is applied to a liquid crystal display device, each pixel (a transparent conductive film and a TF
The output terminal of the complementary TFT was connected to the electrode of one of the transparent conductive films (pixels) of T). That is, a P-channel TFT is provided for all pixels arranged in a matrix.
(Hereinafter referred to as PTFT) and NTFT as a complementary type (hereinafter referred to as C / TFT) to form a pixel.

A typical example is shown as a circuit in FIG. FIG. 5 shows an example of an actual pattern layout (arrangement diagram).

That is, in the example of the 2 × 2 matrix shown in FIG. 4, the gates of the PTFT and the NTFT are connected to each other, and
Connected to the axial line V _GG (22), or V _{GG '} (23). The common output of the C / TFT is connected to the liquid crystal (12). Input of PTFT (Vss side) of the X-axis direction of the line V _DD (18), connected to the V _{DD '(18'),} and the input of the NTFT of (V _SS side) is connected to Vss (19). Then, when V _DD (18) and V _GG (22) are “1”, the liquid crystal potential (1
0) is "0", V _DD (18) is "1", and V _GG (22) is "0".
At this time, the liquid crystal potential (10) becomes "1". That is, V _GG and V _LC are in “opposite phase”.

The liquid crystal potential (10) is fixed to either V _DD (18), ground or V _SS (19), so
It does not become a ting.

[0014] In FIG 4, when arranged in reverse the NTFT and PTFT, and V _GG and V _LC can be "in phase".

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on examples.

[0016]

Embodiment 1 In this embodiment, the present invention will be described with reference to FIGS. A manufacturing process when a C / TFT is made on a glass substrate is shown based on FIGS.

In FIG. 1, an oxidation as a blocking layer (38) is performed on a glass (1) such as AN glass or Pyrex (registered trademark) glass which can withstand a heat treatment at about 600 ° C. by magnetron RF (high frequency) sputtering. 1000 to 30 silicon film
It was manufactured to a thickness of 00 mm.

Process conditions are 100% oxygen atmosphere, film formation temperature
The temperature was 150 ° C, the output was 400 to 800 W, and the pressure was 0.5 Pa. Film formation rate using quartz or single crystal silicon as target is 30Å
/ Min.

On top of this, the total amount of oxygen, carbon or nitrogen is
7 × 10¹⁹cm^-3Preferably 1 × 10¹⁹cm ^-3Add only below
LPCVD (low pressure gas phase) method, sputter method
Alternatively, it was formed by a plasma CVD method. In the decompression gas phase method
If formed, 450 to 100-200 ° C below the crystallization temperature
At ~ 550 ° C, for example 530 ° C, disilane (Si_TwoH₆) Or bird
Silane (Si_ThreeH₈) Was supplied to a CVD apparatus to form a film. Reactor
The internal pressure was 30 to 300 Pa. Deposition rate is 30-1000 / min
Met. NTET and PTFT threshold voltage (Vt
h) using boron and diborane to control
1 × 10¹⁵~ 5 × 10¹⁷cm^-3Added during film formation as a concentration of
May be.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ⁻⁵ Pa or less, single crystal silicon is used as a target, and argon is mixed in an atmosphere containing 50 to 80% by volume of hydrogen. For example, argon was 20% by volume and hydrogen was about 80% by volume. The film formation temperature was 150 ° C., the frequency was 13.56 MHz, and the sputter output was 400 to 800 W. The pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a reactive gas. these
The film was introduced into a PCVD apparatus, and a film was formed by applying a high frequency power of 13.56 MHz.

The coatings formed by these methods are:
Oxygen was only contained at 7 × 10 ¹⁹ cm ^−3, preferably at 1 × 10 ¹⁹ cm ⁻³ or less. Then, although this film has photosensitivity, it has a feature that crystallization is easier than when no oxidation or the like is added.

In this embodiment, as shown in FIG.
Semiconductor film (2), (2 ')
And other parts were removed. Further, using the second photomask, the photoresist (35) was selectively removed. The removed regions (36) and (35) cover the channel forming regions of PTFT and NTFT, respectively. The holes (35) and (36) are filled with C, N or O, for example, O by 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm.
^{A -2} dose impurity was added by ion implantation. The applied voltage was 30 to 50 KeV, for example, 35 KeV.

As a result, the source or drain region, which is a pair of impurity regions, has a very small amount of impurities such as oxygen, and crystallization proceeds more strongly. A part thereof is provided in a certain region such as a source and a drain in a later step to a depth of 0 to 5 μm in a lateral direction. That is, ideally, 0 is preferable, but in consideration of the problem in the process, it is preferable to provide in the lateral direction within a range of about 5 μm including 0.

In other words, C, O, and N may be added to make the film non-photosensitive. However, if it is too much, it becomes difficult to crystallize even in the subsequent heat treatment, and the carrier mobility becomes 5 cm ² / Vsec or more, preferably 10 10 This is because 100100 cm ² / Vsec cannot be obtained.

Thus, the amorphous silicon film is reduced to 50
After fabrication to a thickness of 0-10000 Å (1 μm), for example 2000 Å,
Heat treatment was performed in a non-oxide atmosphere at a medium temperature of 500 to 750 ° C. at a temperature that does not cause crystal growth for 12 to 70 hours. For example, it was kept at a temperature of 600 ° C. in a nitrogen or hydrogen atmosphere.

Since a silicon oxide film having an amorphous structure is formed on the lower substrate surface of the semiconductor film, no specific nucleus is present in this heat treatment, and the whole is annealed uniformly. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By this annealing, the semiconductor film in the channel formation region shifts from an amorphous structure to a highly ordered state, and a part of the semiconductor film exhibits a crystalline state. In particular, a region having a relatively high order at the time of forming a silicon film is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, the silicon mutually pulls each other. When the crystal is measured by laser Raman spectroscopy, the peak of the single crystal silicon (111) crystal orientation is 522.
A (111) crystal peak having a lattice strain shifted to a lower frequency side than cm ⁻¹ is observed. Calculated from the half-value width, the apparent particle size is 50 to 500 mm, which is like a microcrystal.In fact, there are many regions with high crystallinity and a cluster structure. Was able to form a film having a semi-amorphous structure in which silicon mutually bonded (anchored).

For example, when the distribution in the depth direction is measured by SIMS (Secondary Ion Mass Spectroscopy), the lowest region (surface or a position away from the surface (inside)) as an additive (impurity)
As a result, 3.4 × 10 ²⁰ cm ⁻³ of oxygen and 4 × 10 ¹⁷ cm ⁻³ of nitrogen were obtained. Hydrogen is 4 × 10 ²⁰ cm ⁻³ and silicon is 4 × 10 ²² cm ^−3.
Was 1 atomic%.

In this crystallization, the oxygen concentration is, for example, 1.5 × 10 ²⁰
In the case of cm ^-3 , heat treatment at 600 ° C. (48 hours) is possible with a film thickness of 1000 °. If this is set to 5 × 10 ²⁰ cm ⁻³ , the film thickness becomes 0.
Crystallization by annealing at 600 ° C. was possible with a thickness of 3 to 0.5 μm, but heat treatment at 650 ° C. was required for crystallization with a thickness of 0.1 μm. That is, crystallization was easier as the film thickness was increased and the concentration of impurities such as oxygen was decreased.

As a result, the coating exhibits a state substantially free of grain boundaries (GB). Carriers can easily move from one cluster to another through anchored locations, resulting in higher carrier mobility than so-called GB polycrystalline silicon. That is, hole mobility (μh) = 10 to 50 cm ² / Vsec and electron mobility (μe) = 15 to 100 cm ² / Vsec.

Further photo sensitivity is, Vg (gate voltage) of the TFT -I _D (drain current) characteristic by irradiating light of 2000 lux from the glass side while gaining I _D is 10% or less in the area of on-state The measurement was performed under the condition that only fluctuation (no drift) or under the condition that the _ID is increased (drift) by two digits or less in the sub-threshold voltage region (the condition where the off-current is sufficiently small). Then, when the oxygen concentration in the channel formation region is as low as 8 × 10 ¹⁹ cm ⁻³ or the like, there is a drift. However, when the oxygen concentration is 1 × 10 ²⁰ cm ⁻³ or more, preferably 3 × 10 ²⁰ cm ⁻³ or more, almost no drift occurs. Drift is PT
Neither FT nor NTFT.

On the other hand, when the film is polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at medium temperature as described above, segregation of impurities such as oxygen in the film by solid phase growth from nuclei. In GB, impurities such as oxygen, carbon, and nitrogen are increased in GB, and the mobility in the crystal is large. However, a barrier is formed in GB to hinder the movement of carriers there. As a result, only a mobility of 5 cm ² / Vsec or less can be obtained, and in fact, a reduction in withstand voltage due to a drain leak or the like at a crystal grain boundary occurs.

That is, in the embodiments of the present invention, as described above, a silicon semiconductor having a semi-amorphous or semi-crystalline structure having no photosensitivity and having crystallinity is used.

Further, a silicon oxide film was formed thereon as a gate insulating film to a thickness of 500 to 2000 (for example, 1000). This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. A small amount of fluorine may be added during this film formation.

In order to improve the interface characteristics between the silicon oxide and the underlying semiconductor film and remove the interface level, it is preferable to simultaneously apply ultraviolet light and perform ozone oxidation. That is, when the sputtering method and the photo CVD method were used together under the same conditions as those for forming the blocking layer (38), the interface level could be reduced.

After this, phosphorus is added on the upper side by 1 to 5 ×.
Silicon film with a concentration of 10 ²⁰ cm ^-3 or this silicon film and molybdenum (Mo), tungsten (W), MoSi ₂
Alternatively, a multilayer film with WSi ₂ was formed. This was patterned using a third photomask. Then, a gate electrode (4) for PTFT and a gate electrode (4 ′) for NTFT were formed. For example, a channel length is 10 μm, and a gate electrode is made of phosphorous silicon.
2 μm, and molybdenum was formed thereon to a thickness of 0.3 μm.

In FIG. 1C, a photoresist (31 ')
Is formed using a photomask, and the source (5),
Boron was added by ion implantation at a dose of 1-2 × 10 ¹⁵ cm ^{−2 to} the region that would be the drain (6) and had a low oxygen concentration.

Next, as shown in FIG. 1D, a photoresist (31)
Was formed using a photomask. And for NTFT
-Phosphorus is applied to the region to be the source (5 ') and drain (6')
¹⁵cm ^-2Was added by ion implantation.

These steps were performed through the gate insulating film (3). However, in FIG. 1B, the silicon oxide on the silicon film is removed using the gate electrodes (4) and (4 ′) as a mask, and thereafter,
Boron and phosphorus may be directly implanted into the silicon film.

Next, after removing the photoresist (31), annealing was performed again at 630 ° C. for 10 to 50 hours. The PTFT source (5), drain (6), and NTFT source
(5 ′) and drain (6 ′) were formed as P ⁺ and N ⁺ regions by activating impurities.

Since this region has a small amount of oxygen and the like, the crystallinity is further improved even at the same temperature. As a result, the ionization rate (the number of acceptors or donors / the amount of implanted impurities) of impurities imparting a conductivity type such as boron and phosphorus could be varied to 50 to 90%.

Channel formation regions (7) and (7 ') are formed below the gate electrodes (4) and (4') as semi-amorphous semiconductors.

The end (4) of the region to which impurities such as oxygen are added
By passing 2) to the impurity region from the end (41) of the impurity region, the ionization rate of boron or phosphorus here is reduced, but at the same time, the crystal is formed on the surface where N ⁺ -I and P ⁺ -I exist. Grain boundaries do not easily exist, and as a result, the drain withstand voltage can be increased.

In this way, a C / TFT can be manufactured without applying a temperature of 700 ° C. or more in all steps, even though the method is a self-aligned method. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process that is extremely suitable for the large pixel liquid crystal display device of the present invention.

The thermal annealing was performed twice in FIGS. 1A and 1D.
However, the annealing in FIG.
Both may be combined by the thermal annealing of FIG. 1 (D) to shorten the manufacturing time. In FIG. 2A, the interlayer insulator
(8) was performed to form a silicon oxide film by the sputtering method described above. This silicon oxide film may be formed by using an LPCVD method or an optical CVD method. For example, it was formed to a thickness of 0.2 to 1.0 μm. Thereafter, as shown in FIG. 2A, a window (32) for an electrode was formed using a photomask.

Further, the total content of aluminum is 0.5 to
A lead (9), formed to a thickness of 1 μm by sputtering.
(9 ') and contacts (29) and (29') were fabricated using a photomask as shown in FIG. 2 (B).

The characteristics of such a TFT will be abbreviated. Mobility (
μ), threshold voltage, drain withstand voltage (V _BDV ), and photosensitivity (PS) are as shown in Table 1.

[0049]

[Table 1]

The above is a channel length of 10 μm and a channel width of 30 μm.
The case of m is shown. By using such a semiconductor, a large mobility can be obtained in a TFT which is generally impossible, and in addition, there is no photosensitivity and a large drain withstand voltage is obtained. Therefore, for the first time, the NTFT or C / TFT for the liquid crystal display device shown in FIGS. 3 and 4 could be configured.

This embodiment is an example of a liquid crystal display device. Further, in order to connect the output of this C / TFT to a pixel, FIG.
In (B), an organic resin (34) such as polyimide was formed. The window was opened again with a photomask. In order to connect the output terminals of the two TFTs to one of the transparent electrodes of the liquid crystal device, an ITO (indium tin oxide film) was formed by a sputtering method. It was etched using a photomask to form a transparent electrode (33). The ITO was deposited at room temperature to 150 DEG C. and was achieved with oxygen at 200 DEG to 300 DEG C. or in air.

In this way, the PTFT (21), the NTFT (11), and the transparent conductive film electrode (33) were formed on the same glass substrate (1).

Example 2 FIG. 5A shows an example corresponding to FIG.
An example is shown. V in X axis direction_DD(18), V_SS(19), V _DD'(1
8 ') in the X-axis direction (hereinafter also referred to as X-ray)
Done. Note that the Y axis is V_GG(22), V_GG'(23) and Y axis
Wiring (hereinafter also referred to as Y line). Drawing (A) is
FIG. 5 (B) is a plan view, and a longitudinal sectional view of AA 'is shown in FIG.
You. FIG. 5C shows a vertical cross-sectional view taken along the line BB ′.

Further, the PTFT (21) is_DD(18) and Y-line V_GG(2
2) at the intersection with_DD(18) and V _GGIntersection with '(23)
Similarly, PTFTs (21 ') for other pixels are provided similarly.
NTFT (11) is V_SS(19) and V_GGProvided at the intersection with (22)
Have been. V_SS(19) and V_GGThere is another under the intersection with (22)
An NTFT (11 ') for each pixel is provided. Using C / TFT
Matrix configuration. These PTFTs are source
(5) X-ray V through contact (32)_DDConnected to (18)
The gate (4) is a multilayered Y-line V_GG(22)
Is tied. The drain (6) is connected via the contact (29)
It is connected to the electrode (33) of the transparent conductive film.

The channel forming region of these NTFT and PTFT
Oxygen was intentionally added to (7) and (7 '), and was not added to the source and drain.

On the other hand, in the case of NTFT, the source (5 ') is
2 ') to the X-ray V _SS (19), and the gate (4')
To the line V _GG (22), the drain (6 ') is connected to the transparent conductive film (33) via a contact (29'). Thus two X-rays
Between the (18) and (19) (inside), one pixel was constituted by the transparent conductive film (33) as a pixel and the C / TFTs (21) and (11). By repeating such a structure left, right, up and down, it has become possible to produce one example of a 2 × 2 matrix or a large-screen liquid crystal display device such as 640 × 480 or 1280 × 960.

The feature here is that two TFTs are provided for one pixel.
Are provided in a complementary configuration, and the electrode (33) constitutes the liquid crystal potential V _LC , which means that the PTFT is on.
Whether NTFT is off, or PTFT is off and NTFT is on,
Is to be fixed at any level.

Even if light is irradiated from the glass substrate side, the C / TFT is not only a reflection type but also a transparent type because the channel forming region is insensitive to light, not to mention the source and drain. Even an optical liquid crystal display device can be operated without providing a shielding means.

As is apparent from FIG. 5, even when the control element Vss is newly increased, the aperture ratio (total area (34)
The ratio of the effective area (33) of the liquid crystal display actually displayed is the same as the conventional case where only one conductivity type TFT of FIG. 1 is connected to each pixel, and is not disadvantageous.

In FIG. 5, an alignment film and an alignment treatment are performed on these transparent conductive films, and a certain interval is provided between this substrate and the other substrate having a liquid crystal electrode (FIG. 5 (34)). The components were arranged with each other by a known method. In the meantime, liquid crystal was injected to complete a liquid crystal display device.

If a TN liquid crystal is used as the liquid crystal material, it is necessary to set the interval to about 10 μm and to form an alignment film on both transparent conductive films by rubbing.

When an FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is set to ± 20 V and the cell interval is set to
1.5 to 3.5 μm, for example 2.3 μm, opposite electrode (Fig. 5)
(34) An alignment film may be provided only on the rubbing treatment.

In the case of using a dispersion type liquid crystal or a polymer liquid crystal, an alignment film is unnecessary, and in order to increase the switching speed, the operating voltage is ± 10 to ± 15 V and the cell interval is 1
薄 く 10 μm.

In particular, when a dispersion type liquid crystal or a polymer liquid crystal is used, the amount of light can be increased both in a reflection type and in a transmission type since a polarizing plate is not required. Since the liquid crystal has no threshold, the C / TFT of the present invention is used.
As shown in the figure, by using a C / TFT type in which a clear threshold voltage is defined, it was possible to realize a large contrast and eliminate crosstalk (bad interference with adjacent pixels).

[0065] The second embodiment, the V _DD side in C / TFT
PTFT and NTFT were formed on the Vss side. Then the output is V
_A clear level can be determined to make _DD or Vss. But for the V _GG, V _LC is inverted - the data (reversed phase).

[0066] shown 2Tr / cell system when the the V _GG and V _LC is in phase (voltage of the same orientation) and (C / TFT method) in the following examples.

[Embodiment 3] In this embodiment, in FIGS. 4 and 5, NTFT (11) is reversed on the V _DD side and PTFT (2) is reversed on the Vss side.
It has a C / TFT configuration that connects 1). Then, (the output of the positive voltage when the V _GG positive voltage, the output of the negative voltage when the negative voltage) V _LC is V _GG phase with its output becomes, the output potential V _GG -Vthp and V _GG - Vthn. Vthp
When Vthn and Vthn are different, it is preferable to apply an offset bias to the other terminals (13) of the liquid crystal in FIG. 4 to make them equal.
Thus, although there is a disadvantage that V _GG must be made larger than V _DD , there is a feature that there is no need to care if there is some leakage between the gate electrode and V _LC .

In such a case, similarly in FIG.
And NTFT may be provided opposite to each other. Therefore, the manufacturing steps and the aperture ratios in the second embodiment and FIG. 5 can have exactly the same values. Others are the same as the second embodiment.

[Embodiment 4] In this embodiment, each pixel shown in FIG. 3 is provided with only 1T by connecting only NTFT to each pixel and the like.
It is of the r / cell type. Then, the level of _VLC becomes floating and varies, but the TFT shown in the present invention has a variation.
Since it is non-photosensitive, there is no need to provide light-blocking means for preventing light from being applied to the TFT in actual use, and an active-type liquid crystal display device can be manufactured more easily than before.
Others are the same as the first and third embodiments.

[0070]

According to the present invention, a non-photosensitive semi-amorphous semiconductor is obtained by adding impurities such as oxygen to a channel forming region by making it non-photosensitive to NTFT and PTFT. Thus, the ionization rate of the donor or the acceptor was improved without adding these impurities, so that the light shielding means became unnecessary. Further TF
By connecting to each pixel that is matrixed as T, especially C / TFT, 1) a liquid crystal display device that does not require shielding means can be manufactured. 2) reduction of the source and drain sheet resistance. 3) It has many features that the drain withstand voltage is improved by 3 to 10 V by passing oxygen to the source and drain side more than PI and NI.

The present invention has shown an example in which a non-photosensitive TFT is manufactured and applied to a liquid crystal display device as an application thereof. However, it can also be used as a load or a three-dimensional element in other semiconductor devices, for example, an image sensor, a monolithic integrated circuit.

In the present invention, a non-photosensitive semi-amorphous or semi-crystalline silicon-based material is used as the semiconductor for the C / TFT. However, semiconductors of other crystal structures may be used if possible for the same purpose. High-speed processing was performed by using a self-aligned C / TFT. However, it goes without saying that the TFT may be manufactured by a non-self-aligned method without using the ion implantation method.

[Brief description of the drawings]

FIG. 1 shows a P-channel type and an N-channel type of the present invention.
3A to 3D illustrate a method for manufacturing a TFT.

FIG. 2 shows a P-channel type and an N-channel type of the present invention.
3A to 3D illustrate a method for manufacturing a TFT.

FIG. 3 is a diagram showing a liquid crystal display device using a 1Tr / cell type active TFT.

FIG. 4 is a circuit diagram of a 2Tr / cell type active liquid crystal device using a complementary TFT of the present invention.

5 is a plan view (A), a longitudinal sectional view (B), and (C) of one substrate of the liquid crystal display device corresponding to FIG.

[Explanation of symbols]

(1) ・ ・ ・ ・ Glass substrate (2), (2 ′) ・ ・ Semiconductor thin film (3) ・ ・ ・ ・ Gate insulating film (4), (4 ′) ・ ・ Gate electrode (5), (5 ′)・ ・ Source (6), (6 ′) ・ ・ Drain (7), (7 ′) ・ ・ Channel forming region (10) ・ ・ ・ ・ Liquid crystal potential (V _LC ) (11) ・ ・ ・ ・N-channel type thin film transistor (NTFT) (12) · · · Liquid crystal (14), (15) · Resistors that cause leakage (16), (17) · Peripheral circuits (18), (18 ') · Vss ( (One of X-rays) (19), (19 ′) · V _DD (One of X-rays) (21) ··· P-channel thin film transistor (PTFT) (22), (23) · V _GG , V _GG '(Y line) (31), (31') ・ Photoresist (38) ・ ・ ・ ・ Blocking layer (33), (34) ・ Transparent electrode ・ ・ ・ ・ ・ ・ Process using photomask

Claims (4)

[Claims] 1. A thin film transistor formed over an insulating surface, wherein the thin film transistor includes a semiconductor having crystallinity including a source region, a drain region, and a channel formation region between the source region and the drain region. , A gate electrode, and a gate insulating film between the channel formation region and the gate electrode, wherein the total amount of oxygen, nitrogen and carbon in the channel formation region is 1 × 10 ²⁰ cm ^{−3 to} 20 A thin film transistor characterized by atomic%. 2. A thin film transistor formed on an insulating surface, wherein the thin film transistor includes a semiconductor having crystallinity including a source region, a drain region, and a channel formation region between the source region and the drain region. , A gate electrode, and a gate insulating film between the channel formation region and the gate electrode, wherein the total amount of oxygen, nitrogen and carbon in the channel formation region is 1 × 10 ²⁰ cm ^{−3 to} 20 Atomic%, and the concentration of boron in the channel forming region is 1 × 10 ^{15 to} 5
A thin film transistor having a size of × 10 ¹⁷ cm ³ . 3. An electro-optical device comprising: a substrate having an insulating surface; a plurality of pixel electrodes arranged in a matrix on the substrate; and a plurality of thin film transistors connected to each of the plurality of pixel electrodes. The thin film transistor includes a source region, a drain region, and a semiconductor having crystallinity including a channel formation region between the source region and the drain region; a gate electrode; and the channel formation region and the gate electrode. Wherein the total amount of oxygen, nitrogen and carbon in the channel forming region is 1 × 10 ²⁰ cm ^{−3 to} 20 at%. 4. An electro-optical device comprising: a substrate having an insulating surface; a plurality of pixel electrodes arranged in a matrix on the substrate; and a plurality of thin film transistors connected to each of the plurality of pixel electrodes. The thin film transistor includes a source region, a drain region, and a semiconductor having crystallinity including a channel formation region between the source region and the drain region; a gate electrode; and the channel formation region and the gate electrode. Wherein the total amount of oxygen, nitrogen and carbon in the channel forming region is 1 × 10 ²⁰ cm ^{−3 to} 20 at%, and the concentration of boron in the channel forming region is 1 × 10 ¹⁵ -5
An electro-optical device having a size of × 10 ¹⁷ cm ³ .