JP2000295863A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of an inverter device and, at the same time, to improve the reliability of the device. SOLUTION: When a load current Io is smaller than a threshold It at normal time, a self-extinguishing semiconductor element 2a is controlled to a turned-on state. When self-extinguishing semiconductor elements 2b and 2c become impossible to properly control a load current due to the abnormality of a current control system while the load current Io is smaller than the threshold It, a short-circuiting current Is may become larger than the threshold It. When the output Id of a current detecting circuit 9a exceeds the threshold It, the semiconductor element 2a is turned off and the overcurrent is interrupted by the element 2a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a plurality of self-extinguishing semiconductor devices and a freewheel diode connected in anti-parallel to the semiconductor devices, and has a predetermined number of inverter bridges connected to a DC voltage circuit. And an inverter device for supplying power to a load circuit.

[0002]

2. Description of the Related Art FIG.
JP, JP-A-5-137346, JP-A-6-3
FIG. 1 is a circuit diagram showing a configuration of a conventional inverter device described in Japanese Patent No. 03763.

In FIG. 1, reference numeral 1 denotes a DC voltage circuit for generating a predetermined voltage E between terminals P and N. 102a-10
Reference numeral 2e denotes a gate turn-off thyristor (hereinafter, referred to as GTO) which is a self-extinguishing type semiconductor element.
03e is a freewheel diode connected in anti-parallel to the GTOs 102a to 102e. 104a to 104
e is a snubber diode, 105a to 105e are snubber capacitors, 106a to 106e are snubber resistors, 107a to 107d are anode reactors, 108 is a fuse, 109 is a current detection circuit, and 10 is a current detection circuit. It is a load circuit.

Next, the operation will be described. Under normal conditions, the GTO 102e for short-circuit current interruption is in a conductive state, and the GTOs 102a to 102d are driven on / off according to the pulse width modulation signal to supply power to the load circuit 10.

As described in Japanese Patent Application Laid-Open No. 4-295227, when the current detecting circuit 109 detects a current equal to or more than a predetermined threshold value, the GTO 102a, 1
It is determined that a short circuit has occurred through the GTO 102b or the GTOs 102c and 102d, and the GTO 102e for short circuit current interruption is driven off to cut off the short circuit current. By doing so, the short-circuit current can be cut off by using only the snubber capacitor 105e connected to the short-circuit current cut-off GTO 102e as a capacitor having a large capacitance, so that the snubber connected to the GTOs 102a to 102d can be cut off. The capacitance of the capacitors 105a to 105d can be reduced.

Further, as described in Japanese Patent Application Laid-Open No. 5-137346, GTO 102a, 102c or GTO 1
G for short-circuit current cut-off at turn-on of 02b and 102d
A gate current larger than a normal gate current is supplied to the TO 102e to perform ON driving. By doing so, the duty of the current increase rate of the GTO 102e for interrupting the short-circuit current can be reduced.

Further, as described in JP-A-6-303763, a snubber circuit connected to the GTO 102e for interrupting short-circuit current is divided to reduce the capacitance of an expensive capacitor having a low inductance characteristic and dedicated to the snubber. Instead of increasing, an inexpensive capacitor with high inductance characteristics may be provided in order to suppress the overvoltage induced in the GTO 102e. By doing so, the cost of the snubber capacitor connected to the GTO 102e for interrupting the short-circuit current can be reduced.

[0008]

Since the conventional inverter device is configured as described above, there are the following three problems. FIG. 20 and FIG. 21 are diagrams showing problems with the conventional inverter device. FIG.
A problem with the conventional inverter device will be described with reference to FIG.

First, the first point will be described. In the circuit shown in FIG. 19, for example, when the GTO 102a is turned on, a surge current Ip for charging the snubber capacitor 105b flows from the DC voltage circuit 1 as shown in FIG. Assuming that the inductance of the anode reactors 107a and 107b is L and the capacitance of the snubber capacitor 105b is C, the maximum value Ipm of the surge current is expressed by the following equation (1).
become that way.

(Equation 1)

If the load current is Io, when only one GTO of the predetermined inverter bridge is turned on, the current that is conducted to the short-circuit current interrupting GTO 102e, that is, the current is detected by the current detection circuit 109. Current Id is the sum of Io and Ip. For example, assuming that the number of inverter bridges constituting the inverter device is m, there is a possibility that up to m GTOs may be turned on at the same time. Therefore, the maximum value Idm of the current flowing through the GTO 102e for short-circuit current interruption is Io and the value of m and Ipm. Sum of products (I
o + m × Ipm).

Therefore, the threshold value It, which is compared with the output Id of the current detection circuit 109, for determining that a DC short circuit has occurred, must be set to a value equal to or more than (Io + m × Ipm). The capacitance of the snubber capacitor 105e connected in parallel with the short-circuit current interrupting GTO 102e must be selected in consideration of current interruption equal to or larger than the threshold value It, and the snubber capacitor 105e having a large electrostatic capacitance is required. There is a problem. This causes the size and cost of the snubber capacitor 105e to increase, and it is difficult to reduce the size and cost of the inverter device.

Next, the second point will be described. In the circuit shown in FIG. 19, when the load circuit 10 is an inductive load (inductance component) such as a motor and a power transformer,
An operation mode in which the load current flows back through a path that does not pass through the DC voltage circuit 1 occurs. Return current Ic as shown in FIG.
Is GTO102a and freewheel diode 103c
When the GTO 102b is erroneously turned on for some reason in the case where it is conducting through the short circuit current, the short-circuit current Is shown in FIG. 20 flows from that moment.

Assuming that the inductances of the anode reactors 107a and 107b are L, the time Tt until the current value detected by the current detection circuit 109 reaches a threshold value It for determining that a DC short circuit has occurred is expressed by the following equation. It becomes like (2).

(Equation 2)

Therefore, the conduction current of the GTO 102a becomes the sum of the short-circuit current Is and the load current Io (= Ic) during the time Tt. That is, even if a DC short circuit occurs during the time Tt, the output Id of the current detection circuit 109 does not reach the threshold value It, so that a DC short circuit accident is not detected.
The GTO 102a may erroneously interrupt a current equal to or larger than the threshold value It. The capacitance of snubber capacitors 105a to 105d connected to GTOs 102a to 102d is designed to be smaller than the capacitance of snubber capacitor 105e connected to GTO 102e for short-circuit current cutoff.
When the TO 102a cuts off a current equal to or larger than the threshold current It, there is a problem that the turn-off fails and the element may be damaged. This impairs the reliability of the inverter device.

The third point is that the DC voltage circuit 1 is not arranged in a concentrated manner as shown in FIG. 19 but is constituted by a plurality of DC capacitors 111a to 111d as shown in FIG. When inverter bridge units 112a and 112b (GTOs 102a and 102b and their peripheral circuits or GTOs 102c and 102d and their peripheral circuits) are connected to DC capacitors 111a to 111d, respectively, they are equivalent to DC voltage circuit 1 as shown in FIG. So that the DC capacitors 111a to 111d
There is a problem that it is difficult to insert the GTO 102e for interrupting short-circuit current in common between the inverter and the inverter bridge units 112a and 112b.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a highly reliable inverter device that can be reduced in size.

[0017]

SUMMARY OF THE INVENTION An inverter device according to the present invention comprises a first closed circuit returning from a DC voltage circuit to a DC voltage circuit via an inverter bridge, and from the inverter bridge via a load circuit and another inverter bridge. A self-extinguishing semiconductor element for interrupting, which is inserted for each inverter bridge in a common path in the second closed circuit returning to the original inverter bridge and interrupts abnormal current, and an anti-parallel self-extinguishing semiconductor element for interrupting, A blocking freewheel diode connected thereto; and a gate control circuit for turning off the blocking self-extinguishing semiconductor device when a current conducted to the blocking self-extinguishing semiconductor device exceeds a predetermined threshold. It is provided.

An inverter device according to the present invention includes a voltage rise rate suppression circuit for suppressing a rise in voltage across a self-extinguishing semiconductor element for shutoff.

An inverter device according to the present invention includes first and second self-extinguishing semiconductor devices connected in series with each other and driven by a predetermined switching signal. First and second freewheel diodes respectively connected in anti-parallel to the semiconductor element, and first and second gates respectively supplying and driving gate signals to the first and second self-extinguishing semiconductor elements A drive circuit, a self-extinguishing semiconductor element for interrupting, which is connected in series to the first and second self-extinguishing semiconductor elements and interrupts abnormal current; and an anti-parallel connection to the self-extinguishing semiconductor element for interrupting A blocking free-wheel diode, a voltage rising rate suppressing circuit for suppressing a voltage rise across the blocking self-extinguishing semiconductor device, and a gate signal to the blocking self-extinguishing semiconductor device. A third gate drive circuit for supplying and driving the semiconductor device, and a third gate drive circuit for controlling the third gate drive circuit when the current conducted to the self-extinguishing type semiconductor element for interrupting becomes equal to or higher than a predetermined threshold value. And a gate control circuit for turning off the self-extinguishing type semiconductor element for each two-level inverter bridge.

In the inverter device according to the present invention, the shut-off self-extinguishing semiconductor device is turned on in synchronization with the timing at which the first and second self-extinguishing semiconductor devices are turned on.

In the inverter device according to the present invention, the predetermined threshold value is set to a period from a turn-on timing of the first self-turn-off semiconductor device to a turn-on timing of the second self-turn-off semiconductor device. And a threshold value changing circuit for changing the threshold value to a predetermined value during periods other than the above.

The inverter device according to the present invention includes a voltage clamp circuit that clamps a voltage applied to the first and second self-extinguishing type semiconductor elements during off driving to a predetermined voltage or less.

The inverter device according to the present invention clamps the voltage applied to the first and second self-extinguishing semiconductor elements and the self-extinguishing semiconductor element for shut-down to a predetermined voltage or less during off driving. It has a voltage clamp circuit.

In the inverter device according to the present invention, the switching state of the first and second self-extinguishing semiconductor devices when the shut-off self-extinguishing semiconductor device is turned off is maintained for a predetermined period. It has a gate control circuit.

An inverter device according to the present invention includes a current change rate suppression circuit for suppressing a change in current conducted to a self-extinguishing type semiconductor element for interruption.

An inverter device according to the present invention includes a third to a sixth self-extinguishing type semiconductor element connected in series with each other and driven by an inverter according to a predetermined switching signal; Third to sixth freewheel diodes respectively connected in anti-parallel to the semiconductor element, and third to sixth gates for supplying and driving gate signals to the third to sixth self-extinguishing semiconductor elements, respectively. A drive circuit, a first coupling diode connected between a connection point between the third self-extinguishing semiconductor device and the fourth self-extinguishing semiconductor device, and a neutral point of the DC voltage circuit; A second coupling diode connected between a connection point of the self-extinguishing semiconductor device of No. 5 and the sixth self-extinguishing semiconductor device and a neutral point of the DC voltage circuit; Abnormal when connected in series with the self-extinguishing semiconductor device A first interrupting self-extinguishing semiconductor device for interrupting a flow, a first interrupting freewheel diode connected in anti-parallel to the first interrupting self-extinguishing semiconductor device, A first voltage rise rate suppression circuit for suppressing a rise in voltage across the self-arc-extinguishing semiconductor device, and a second voltage-cutting semiconductor device connected in series to the fifth and sixth self-arc-extinguishing semiconductor devices for interrupting an abnormal current. A self-extinguishing semiconductor device for shut-off, a second freewheel diode for shut-off connected in antiparallel to the second self-extinguishing semiconductor device for shutting-off,
Supplying a gate signal to each of a second voltage rise rate suppressing circuit for suppressing a rise in voltage across the second self-turn-off semiconductor element for shutoff, and first and second self-turn-off semiconductor elements for shutoff. And an eighth gate drive circuit driven by the first gate drive circuit, and a seventh gate drive circuit when a current conducted to the first shut-off self-extinguishing type semiconductor element becomes equal to or more than a predetermined first threshold value. A third gate control circuit for controlling the circuit to turn off the first shut-off self-extinguishing semiconductor device; and a second threshold for applying a current flowing through the second shut-off self-extinguishing semiconductor device to a predetermined second threshold. And a fourth gate control circuit for controlling the eighth gate drive circuit to turn off the second shut-off self-extinguishing type semiconductor element when the value becomes equal to or more than the value, for each three-level inverter bridge.

The inverter device according to the present invention turns on the first shut-off self-extinguishing semiconductor device in synchronization with the timing at which the third and fifth self-extinguishing semiconductor devices turn on, respectively. The second self-extinguishing semiconductor element for blocking is turned on in synchronization with the timing at which the sixth self-extinguishing semiconductor element is turned on.

In the inverter device according to the present invention, the predetermined first threshold value is set between the turn-on timing of the third self-turn-off semiconductor device and the turn-on timing of the fifth self-turn-off semiconductor device. A first threshold value changing circuit for changing the threshold value to a predetermined value in each of the period and the other period, and a predetermined second threshold value in accordance with the fourth self-extinguishing type semiconductor device from the turn-on timing. And a second threshold value changing circuit for changing each of the self-extinguishing type semiconductor elements to a predetermined value in a period up to the turn-on timing and in other periods.

The inverter device according to the present invention includes a second voltage clamp circuit for clamping the voltage applied to the third and fifth self-extinguishing semiconductor elements at the time of off-driving to a predetermined voltage or less; And a third voltage clamp circuit for clamping a voltage applied to the fourth and sixth self-extinguishing semiconductor elements at the time of off driving to a predetermined voltage or less.

In the inverter device according to the present invention, the voltage applied to the third and fifth self-extinguishing semiconductor elements and the first shut-off self-extinguishing semiconductor element at the time of off driving is equal to or less than a predetermined voltage. And a second voltage clamping circuit for clamping the voltage applied to the fourth and sixth self-arc-extinguishing semiconductor devices and the second self-extinguishing semiconductor device for shut-off during off-operation to a predetermined voltage or less. 3rd clamp on
And a voltage clamp circuit.

In the inverter device according to the present invention, the switching state of the third to sixth self-extinguishing semiconductor elements when one of the first and second self-extinguishing semiconductor elements for shut-off is turned off is determined. And a fifth gate control circuit that keeps the state as it is during the period.

The inverter device according to the present invention comprises: a first current change rate suppressing circuit for suppressing a change in a current conducted to a first interrupting self-extinguishing type semiconductor element; and a second interrupting self-extinguishing type semiconductor device. A second method for suppressing a change in a current conducted to a semiconductor element.
And a current change rate suppressing circuit.

The inverter device according to the present invention comprises
A sixth embodiment employs a gate commutation type turn-off thyristor as the self-extinguishing semiconductor device, the self-extinguishing semiconductor device for shutting off, and the first and second self-extinguishing semiconductor devices for shutting off.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of an inverter device according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing an example of the gate drive circuit of the self-extinguishing type semiconductor device in FIG. 1 and its peripheral circuits.

In FIG. 1, reference numeral 1 denotes a DC voltage circuit for generating a predetermined voltage E between terminals P and N. 2a-2c
Are three self-extinguishing semiconductor elements connected to the DC voltage circuit 1 and connected in series with each other (a self-extinguishing semiconductor element for interrupting, a first self-extinguishing semiconductor element, and a second self-extinguishing semiconductor element). Semiconductor elements 2d to 2f are connected in parallel with the three self-arc-extinguishing semiconductor elements 2a, 2b, and 2c and connected in series with each other. A semiconductor element, a first self-arc-extinguishing semiconductor element, and a second self-arc-extinguishing semiconductor element).

3a to 3c are self-extinguishing type semiconductor elements 2a
2c to 2c are connected in anti-parallel to each other (a freewheel diode for blocking, a first freewheel diode and a second freewheel diode), and 3d to 3f are self-extinguishing type semiconductor elements 2d to 2c. 2f are freewheeling diodes (a freewheeling diode for disconnection, a first freewheeling diode, and a second freewheeling diode) connected in antiparallel to each other. Reference numerals 9a and 9b denote current detection circuits for detecting currents flowing through the self-extinguishing type semiconductor elements 2a and 2d, respectively. An output terminal 10 has one end connected to the output terminal 13a between the self-extinguishing semiconductor elements 2b and 2c, and the other end connected to the output terminal 1 between the self-extinguishing semiconductor elements 2e and 2f.
3b is a load circuit connected to 3b.

The self-turn-off semiconductor elements 2b and 2c driven by an inverter according to a predetermined switching signal and the freewheel diodes 3b and 3c connected in anti-parallel to each other constitute one two-level inverter bridge. Self-extinguishing type semiconductor elements 2e and 2f which are inverter-driven in accordance with a predetermined switching signal and freewheel diodes 3e and 3f respectively connected in anti-parallel to each other constitute one two-level inverter bridge.

The self-extinguishing type semiconductor elements 2a, 2d
Is a first closed circuit that returns from the DC voltage circuit 1 to the DC voltage circuit 1 via each inverter bridge, and, for example, as shown in FIG. (That is, a path common to the path in which the DC short-circuit current Is conducts and a path common to the path in which the return current Ic conducts).

In FIG. 2, reference numeral 14a denotes a predetermined threshold value I.
Reference numeral 15a denotes a gate control circuit which controls a gate signal to the self-extinguishing type semiconductor element 2a in accordance with the comparison result by the comparison circuit 14a. The self-extinguishing type semiconductor element 2
Similarly, for d, a comparison circuit (not shown) that compares a predetermined threshold value It with the output Id of the current detection circuit 9d, and a gate to the self-extinguishing type semiconductor element 2d according to the comparison result. A gate control circuit (not shown) for controlling a signal is provided.

As the self-extinguishing type semiconductor elements 2a to 2f in FIGS. 1 and 2, insulated gate bipolar transistors (hereinafter referred to as IGBTs) can be used. Note that another power device may be used as long as the switching state can be controlled by a gate signal.

Further, it goes without saying that the inverter device is provided with a gate control circuit (not shown) for supplying a switching signal (gate signal) to each inverter bridge.

Next, the operation will be described. Under normal conditions, the load current Io flowing through the load circuit 10 is equal to the self-extinguishing type semiconductor elements 2b, 2c, 2 of the two inverter bridges.
e, 2f. Note that the above-mentioned threshold value It
Is set in advance to a predetermined value larger than the maximum value of the load current Io in the normal state. The direction of the arrow in the drawing indicates the positive electrode of the current.

Hereinafter, the left inverter bridge (the one including the self-extinguishing type semiconductor elements 2b and 2c) in FIG. 1 will be described. Note that the other inverter bridges are the same, and a description thereof will be omitted.

Normally, when the load current Io is smaller than the threshold value It, the output of the comparison circuit 14a becomes positive, and the self-extinguishing type semiconductor element 2a is connected to the gate control circuit 15a.
Is turned on.

At this time, if the self-extinguishing type semiconductor elements 2b and 2c cannot properly control the load current due to an abnormality of a current control system (not shown), the load current Io becomes the threshold value It.
The self-arc-extinguishing type semiconductor elements 2b and 2c may be broken down, may be turned on at the same time due to an abnormal switching signal, or the free-wheeling diodes 3b and 3c may break down. May be short-circuited, and the short-circuit current Is may be equal to or larger than the threshold value It.

Once the output Id of the current detection circuit 9a is It
As described above, the output of the comparison circuit 14a is inverted to negative, the self-turn-off semiconductor element 2a is turned off by the gate control circuit 15a, and the overcurrent is cut off by the self-turn-off semiconductor element 2a.

As described above, when an abnormal operation of the inverter bridge occurs for some reason and an overcurrent flows,
The overcurrent is cut off by the self-extinguishing type semiconductor element 2a,
Remove. When the output of the comparison circuit 14a is once inverted to negative, it is preferable that the output be held negative for a predetermined time.

As the self-extinguishing type semiconductor element 2a, a self-extinguishing type semiconductor element having higher current interrupting capability than the self-extinguishing type semiconductor elements 2b and 2c is used. For example, the self-extinguishing type semiconductor element 2b,
A device having a rated current larger than 2c is used for the self-extinguishing type semiconductor device 2a. Since the rated current has a limit value, the maximum rated IGBT is connected to the self-extinguishing type semiconductor element 2b,
When used for 2c, the same one is used for the self-extinguishing type semiconductor element 2a in, for example, a parallel connection configuration.

The self-extinguishing type semiconductor elements 2b and 2c control the load current Io.
In b and 2c, turn-off loss, turn-on loss, and conduction loss occur. On the other hand, in the self-extinguishing type semiconductor element 2a, only conduction loss occurs during normal operation. Therefore, when the same cooling method is applied to each of the self-arc-extinguishing semiconductor elements 2a, 2b, and 2c, the junction temperature of the self-arc-extinguishing semiconductor element 2a is equal to the junction temperature of the self-arc-extinguishing semiconductor elements 2b and 2c. Lower. Due to the difference in the junction temperature, a high breaking current performance can be secured for the self-arc-extinguishing semiconductor element 2a by applying the IGBT having the same rated current to the self-arc-extinguishing semiconductor elements 2a to 2c.

In recent years, SiC has been used in place of silicon.
A new bipolar device by (silicon carbide) has been developed. For example, as described in the Institute of Electrical Engineers of Japan, Vol. 118, No. 5, the on-resistance of SiC is about 200 times lower than that of silicon. The bonding temperature of silicon is 1
Although it is about 30 ° C., it is considered that semiconductor operation is possible with SiC even at a high junction temperature of 400 ° C. or higher. Therefore, the self-arc-extinguishing semiconductor device made of SiC can be expected to ensure a low on-voltage and a high withstand voltage against a rise in the junction temperature when the overcurrent is interrupted.
It is suitable for a and 2d.

In the inverter device shown in FIG.
The current conducted to the self-extinguishing type semiconductor element 2a is directly detected by the current detecting circuit 9a. For example, an indirect current detecting method by detecting a generated voltage using a shunt resistor, a self-extinguishing type semiconductor An indirect current detection method for estimating a conduction current from an emitter-collector voltage or a gate-emitter voltage of the element 2a. An IGBT chip for current detection is provided in the self-extinguishing type semiconductor element 2a. Instead, an indirect current detection method such as a current detection method for estimating a conduction current from an emitter-collector voltage or the like may be used.

Further, in the inverter device shown in FIG.
The current detection circuit 9a is connected to the emitter terminal of the self-extinguishing type semiconductor element 2a, but may be provided at another location as long as the current flowing through the self-extinguishing type semiconductor element 2a can be detected.

As described above, since the load current Io cannot be detected together with the conventional inverter device, the GTOs 102a to 102 other than the GTO 102e for interrupting the DC short-circuit current are not provided.
In some cases, a high cut-off current performance was required for d as well. However, according to the first embodiment, self-extinguishing was performed on a common path between the path where the DC short-circuit current flows and the path where the load current returns. Since the mold semiconductor elements 2a and 2d are inserted, when an abnormality occurs in the inverter bridge for some reason and an overcurrent occurs, an effect is obtained that the overcurrent can be cut off and removed.

Further, in the conventional inverter shown in FIG. 19, since the surge-on current is superimposed and flows to the GTO 102e for interrupting the DC short-circuit current, the number of inverter bridges constituting the inverter is limited by the interrupting current performance of the GTO 102e. However, in the inverter device according to the first embodiment (FIG. 1), a self-extinguishing type semiconductor element for disconnection is provided for each inverter bridge, so the number of inverter bridges is particularly limited (for example, to two). Never.

Embodiment 2 The inverter device according to the second embodiment of the present invention is configured such that the self-extinguishing type semiconductor elements 2a and 2d in the inverter device according to the first embodiment are provided with snubber circuits.

FIG. 3 is a circuit diagram showing a configuration of an inverter device according to Embodiment 2 of the present invention. In the figure,
Reference numeral 4a denotes a snubber diode that forms a snubber circuit (voltage rise rate suppression circuit) connected to the self-extinguishing type semiconductor element 2a, and 5a forms a snubber circuit connected to the self-extinguishing type semiconductor element 2a. 6 is a snubber capacitor
a is a snubber resistor connected in parallel with the snubber diode 4a and constituting a snubber circuit connected to the self-extinguishing type semiconductor element 2a. 4d is a self-extinguishing type semiconductor element 2d
, A snubber diode that forms a snubber circuit (voltage rise rate suppression circuit) connected to, a snubber capacitor that forms a snubber circuit that is connected to the self-extinguishing semiconductor element 2d, and a snubber diode 6d that forms a snubber diode. A snubber resistor which is connected in parallel with 4d and constitutes a snubber circuit connected to the self-extinguishing type semiconductor element 2d.

The other components in FIG. 3 are the same as those in the first embodiment (FIG. 1), and therefore, description thereof will be omitted.

Next, the operation will be described. Embodiment 1
Self-extinguishing type semiconductor elements 2a and 2d cut off the overcurrent. This operation is a non-repetitive turn-off operation. Snubber circuit (snubber diode 4
a, the snubber capacitor 5a and the snubber resistor 6a, and the snubber diode 4d, the snubber capacitor 5d and the snubber resistor 6d) suppress the turn-off loss generated in the non-repetitive turn-off operation and suppress the junction temperature rise.

As described above, according to the second embodiment, the self-extinguishing type semiconductor elements 2a and 2d are provided with the snubber circuits. The junction temperature may be higher than the self-arc-extinguishing semiconductor elements 2b and 2c, and if the overcurrent interruption by the self-arc-extinguishing semiconductor element 2a fails, the other self-arc-extinguishing semiconductor elements 2b and 2c sound. Can be reduced and the reliability of the overcurrent interruption by the self-extinguishing type semiconductor elements 2a and 2d can be improved.

In the snubber circuit of the inverter device according to the second embodiment, current flows only during this non-repetitive turn-off operation, so that the allowable current value of snubber capacitor 5a and snubber resistor 6a can be designed to be small.

Further, it is of course possible to apply the gate control circuit shown in FIG. 2 to the inverter device according to the second embodiment.

Embodiment 3 FIG. 4 is a circuit diagram showing a configuration of an inverter device according to a third embodiment of the present invention. FIG. 5 is a diagram showing an example of a gate drive circuit of a self-extinguishing type semiconductor element and its peripheral circuits in FIG. is there.

In the first embodiment, IGBT is used for self-extinguishing type semiconductor elements 2a to 2f as an example. Since the impedance between the emitter and the collector can be controlled by controlling the gate voltage in the IGBT, it is well known from a description of various product catalogs, for example, that a relatively large overcurrent exceeding a rated current can be cut off.

As a self-extinguishing type semiconductor device having a larger capacity than the IGBT, there is a gate commutation type turn-off thyristor (hereinafter referred to as GCT). This GCT is a self-extinguishing type semiconductor device like GTO and the like. However, while the turn-off gain (ratio of the maximum gate off current to the maximum cutoff current) of the GTO is about 3 to 5, the turn-off gain of the GCT is 1 The gate drive circuit supplies a gate-off current of approximately the same value as the cut-off current by the gate drive circuit.
The GCT is turned off by diverting all the current conducted to the cathode of the CT to the gate drive circuit. Therefore, it is difficult to perform the same gate voltage control as that of the IGBT for the GCT, and therefore, an overcurrent cutoff method different from the case of using the IGBT is used. Hereinafter, an inverter device using the GCT will be described.

In FIG. 4, reference numerals 2a to 2f denote self-extinguishing semiconductor devices using GCT. The GCT and the diode are formed on the same semiconductor wafer, and the reverse conducting GCT housed in the same package is replaced with the self-extinguishing type semiconductor device 2.
a to 2f and free wheel diodes 3a to 3f.

Reference numeral 16a denotes a clamp diode which constitutes a voltage clamp circuit which suppresses a rise in voltage of the self-extinguishing type semiconductor elements 2b and 2c during off driving due to energy stored in the current change rate suppressing circuit 19a. Is a clamp capacitor that constitutes a voltage clamp circuit,
Reference numeral 18a is a discharge resistor similarly constituting a voltage clamp circuit. Reference numeral 16b denotes a clamp diode that constitutes a voltage clamp circuit that suppresses a voltage increase when the self-extinguishing type semiconductor elements 2e and 2f are driven off by the energy stored in the current change rate suppression circuit 19b. Similarly, 17b denotes a voltage clamp circuit. It is a clamp capacitor that constitutes a circuit.
“b” is a discharge resistor similarly constituting the voltage clamp circuit. Reference numerals 19a and 19b denote current change rate suppression circuits each having an inductance component for suppressing a change in a conducting current.

In the GCT, the safe operation area is expanded as compared with the GTO, so that the rated current can be cut off without using a snubber circuit, and the voltage rise rate tolerance and the current rise rate tolerance are large. If the current rise rate of the circuit increases during actual use, the reverse recovery current of the freewheeling diode in particular increases, and thus the reverse recovery loss increases, which may lead to damage depending on the degree of the loss value. . Therefore, in order to ensure low loss or high reliability of the inverter device, the current change rate suppression circuits 19a, 19
b is provided.

The current change rate suppression circuits 19a, 19b
Is constituted by a reactor, a wiring, a fuse and the like, and the fuse may be omitted as long as the reliability of the off driving operation of the self-extinguishing type semiconductor elements 2a and 2d is guaranteed.

The total inductance La of the current change rate suppression circuit 19a is designed as follows. The maximum interruptable current of the self-extinguishing type semiconductor element 2a,
a, a threshold value for detecting an abnormal current, It (set to a value equal to or less than the maximum cutoff current of the self-extinguishing type semiconductor elements 2b, 2c which are GCTs), a voltage by the DC voltage circuit 1 as E, a current detection circuit Assuming that the operation delay time from the detection of a current equal to or greater than the threshold current by the self-arc-extinguishing semiconductor element 2a, which is a GCT, to the interruption of the overcurrent is Tm, the total inductance La of the current change rate suppression circuit 19a is Tm. Is designed according to equation (3).

(Equation 3)

Therefore, if the operation delay time Tm can be reduced, the total inductance La can be reduced, and if the total inductance La is reduced, the capacitance of the clamp capacitor 17a can be reduced.

The capacitance C of the snubber capacitor 5a
s is designed as follows. When the self-extinguishing type semiconductor element 2a, which is a GCT, is turned off, all the energy stored in the current change rate suppression circuit 19a is absorbed by the snubber capacitor 5a. Then, the charging voltage of the snubber capacitor 5a is applied to the clamp diode 16a. Therefore, assuming that the withstand voltage of the clamp diode 16a is V, the maximum breakable current of the self-extinguishing type semiconductor element 2a of GCT is Ia, and the total inductance of the current change rate suppressing circuit 19a is La, the capacitance Cs of the snubber capacitor 5a is Cs. Is designed according to equation (4).

(Equation 4)

The other components in FIG. 4 are the same as those according to the first embodiment (FIG. 1) or the second embodiment (FIG. 3), and the description thereof will be omitted.

In FIG. 5, reference numeral 21a denotes a threshold value selecting circuit (threshold changing circuit) for selecting the magnitude of the threshold value It according to the output of the switching signal holding circuit 24a, and 22a denotes a switching signal holding circuit. This is a turn-on timing detection circuit that detects the timing at which the turn-on operation is performed in accordance with the output of the circuit 24a.

Reference numerals 23a to 23c denote gate drive circuits (third gate drive circuit, first gate drive circuit, and second gate drive circuit) for driving the self-extinguishing type semiconductor elements 2a to 2c, respectively. Is supplied with a switching signal to the self-extinguishing type semiconductor elements 2b and 2c generated by a switching signal generating circuit (not shown), and an off signal for driving the self-extinguishing type semiconductor element 2a off from the gate control circuit 26a. Is a switching signal holding circuit (second gate control circuit) that holds a switching signal to the self-extinguishing type semiconductor elements 2b and 2c when the signal is output, and continuously outputs the held signal for a predetermined period. . 2
5a is a comparison circuit for comparing the threshold value It with the output Id of the current detection circuit 9a, and 26a controls the gate drive circuit 23a according to the output of the comparison circuit 25a and the output of the turn-on timing detection circuit 22a, This is a gate control circuit that controls the switching state of the self-extinguishing type semiconductor element 2a.

A circuit (not shown) similar to the circuit shown in FIG. 5 is also provided in self-extinguishing type semiconductor elements 2d, 2e, 2f and current detecting circuit 9d.

Next, the operation will be described. FIG. 6 is a timing chart for explaining the operation of the inverter device shown in FIGS.

The switching signal holding circuit 24a shown in FIG.
Is supplied with a switching signal to the self-extinguishing type semiconductor elements 2b and 2c generated by a switching signal generating circuit (not shown), and an off signal for driving the self-extinguishing type semiconductor element 2a off by the gate control circuit 26a. Is output, the switching signal to the self-extinguishing type semiconductor elements 2b and 2c is held, and the held signal is continuously output for a predetermined period. The switching signal holding circuit 24a
Is, unless the gate control circuit 26a outputs an off signal.
The supplied switching signal is output as it is.

The threshold selection circuit 21a according to the signal
Selects the magnitude of the threshold value It, and detects the timing at which the turn-on timing detection circuit 22a executes the turn-on operation. On the other hand, the threshold I
t is compared with the output Id of the current detection circuit 9a, and the gate control circuit 26a controls the gate drive circuit 23a according to the comparison result and the output of the turn-on timing detection circuit 22a.
is controlled, and the switching state of the self-extinguishing type semiconductor element 2a is controlled.

The output of the switching signal holding circuit 24a is supplied to gate drive circuits 23b and 23c, and the switching states of the self-extinguishing type semiconductor elements 2b and 2c are controlled by the gate drive circuits 23b and 23c.

The detailed operation of each unit will be described below with reference to the timing chart of FIG. First, the current Id detected by the current detection circuit 9a when the switching operation of the self-extinguishing type semiconductor elements 2b and 2c is performed will be described.

In the switching operation of the self-extinguishing type semiconductor elements 2b and 2c, as shown in FIG. 6, when turning on, a period Td during which both the self-extinguishing type semiconductor elements 2b and 2c are driven off is provided. Can be This period Td is a time for preventing the self-extinguishing type semiconductor elements 2b and 2c from being simultaneously turned on in the transient state of the switching operation and short-circuiting the DC voltage circuit 1, and is called a short-circuit prevention time.

Thus, self-extinguishing type semiconductor element 2
When b and 2c are driven, the detection current Id by the current detection circuit 9a changes according to the polarity (direction) of the load current Io in FIG.
It becomes as shown in. That is, the load current is positive (see FIG. 4).
), The detected current becomes maximum immediately after time T2 at which the self-extinguishing type semiconductor element 2b performs the turn-on operation, and the maximum value is the load current Io and the reverse recovery current Irr of the freewheel diode 3c. The sum of on the other hand,
When the load current is negative (in the opposite direction to the direction shown in FIG. 4), the detected current becomes maximum immediately after time T4 when the self-extinguishing type semiconductor element 2c performs the turn-on operation, and the maximum value is the freewheeling diode. The reverse recovery current Irr of FIG.

Next, the turn-on timing detection circuit 22
A detailed operation when a gate signal is supplied to the self-extinguishing type semiconductor element 2a by a or the like will be described. In general,
Since the large-capacity GCT has a very large wafer diameter, when a high current rises at the time of turn-on, all the wafer surfaces are not turned on and the portion near the gate electrode is turned on first. Then, the current flows intensively at the part where the transistor is partially turned on, so that a local increase in the junction temperature occurs. The gate drive circuit 2 is used to increase the area that is partially turned on to suppress a local increase in junction temperature.
3a supplies a high gate-on current (a gate signal having a larger current than a normal gate signal).

The rise in the current flowing through the self-extinguishing type semiconductor element 2a is caused by the self-extinguishing type semiconductor element 2b,
Time T2 and time T, which are the turn-on timing of 2c
4, the turn-on timing detection circuit 22a is connected to the switching signal holding circuit 24a
The times T2 and T4 are detected from the two output values, and the detection signals are supplied to the gate control circuit 26a. The gate control circuit 26a controls the gate drive circuit 23a at that timing, and causes the gate drive circuit 23a to supply a high gate-on current to the self-extinguishing type semiconductor element 2a.

Note that the polarity of the load current Io is detected, and only one of the timings T2 and T4 is detected based on the polarity, and the gate drive circuit 23a supplies the high gate on current at that timing. It may be.

Next, the detailed operation of the threshold value selection circuit 21a will be described. In a normal time, the self-extinguishing type semiconductor element 2b is driven off during a period from the time T4 when the self-extinguishing type semiconductor element 2c is turned on to the time T2 when the self-extinguishing type semiconductor element 2b is turned on. Regardless of the polarity of the load current Io, a current having a positive polarity exceeding the reverse recovery current Irr of the freewheel diode 3b is not detected by the current detection circuit 9a. However, when an abnormality occurs in the self-extinguishing type semiconductor elements 2b, 2c or the freewheel diodes 3b, 3c,
A positive current exceeding the reverse recovery current Irr of the freewheel diode 3b may be detected.

The threshold selection circuit 21a provides the two outputs of the switching signal holding circuit 24a for a period from time T4 when the self-extinguishing type semiconductor element 2c is turned on to time T2 when the self-extinguishing type semiconductor element 2b is turned on. , A predetermined value (“L” in the figure) exceeding the maximum value of the reverse recovery current Irr of the freewheel diode 3b is selected as the threshold value It in the period, and is supplied to the comparison circuit 25a. . In other periods, the threshold value selection circuit 21a sets the load current I
A predetermined value ("H" in the figure) exceeding the sum of the maximum value of "o" and the maximum value of the reverse recovery current Irr of the freewheel diode 3c is selected and supplied to the comparison circuit 25a.

The comparison circuit 25a is connected to the current detection circuit 9a
Is compared with the supplied threshold value It, and the comparison result is supplied to the gate control circuit 26a. When the detected current Id is equal to or larger than the threshold value It, Determines that an abnormality has occurred,
The self-turn-off type semiconductor element 2a is turned off by controlling the gate drive circuit 23a.

When the gate control circuit 26a once supplies the off signal to the gate drive circuit 23a, it is preferable to continuously supply the off signal for a predetermined period. For example, the time when the detection current Id becomes equal to or greater than the threshold value It is held by the comparison circuit 25a, and the gate control circuit 26a continuously supplies the OFF signal for a predetermined period from that time.

At the same time as the gate control circuit 26a outputs the OFF signal, information to that effect is supplied to the switching signal holding circuit 24a and the switching signal holding circuit 2
4a holds the value of the switching signal irrespective of the change of the supplied switching signal. As described above, when an overcurrent flows through the self-arc-extinguishing semiconductor elements 2b and 2c and the self-arc-extinguishing semiconductor element 2a is driven off, the self-arc-extinguishing semiconductor elements 2b and 2c cut off the current. In this way, the possibility that the self-extinguishing type semiconductor elements 2b and 2c will cause turn-off damage is reduced.

The freewheel diodes 3b, 3
If the time during which the reverse recovery operation of c is performed can be specified in advance, after the reverse recovery operation of the freewheel diodes 3b and 3c, the H level of the threshold value It is changed to a predetermined value exceeding the maximum value of the load current Io. And the level of L may be changed to zero. In this case, there are four levels of the threshold value It.

In the circuit shown in FIG. 5, information indicating that the self-extinguishing type semiconductor element 2a is turned off is supplied from the gate control circuit 26a to the switching signal holding circuit 24a. As described above, the output of the comparison circuit 25a is directly supplied to the switching signal holding circuit 24a,
Based on the output, the gate control circuit 26a may detect that the self-extinguishing type semiconductor element 2a is turned off.

Next, a voltage clamp circuit composed of a clamp diode 16a, a clamp capacitor 17a and a discharge resistor 18a will be described.

The self-extinguishing type semiconductor element 2b, which is a GCT,
Current change rate suppression circuit 1 by switching operation of 2c
The energy stored in 9a is not so small as to be lost in the self-extinguishing semiconductor elements 2b and 2c as in the case of using an IGBT.

Therefore, the clamp diode 1 shown in FIG.
6a, clamp capacitor 17a and discharge resistor 18a
The energy stored in the current change rate suppression circuit 19a is temporarily absorbed by the clamp capacitor 17a.

By providing a voltage clamp circuit composed of a clamp diode 16a, a clamp capacitor 17a and a discharge resistor 18a at a location commonly applied to the self-extinguishing type semiconductor elements 2b and 2c, the self-extinguishing type semiconductor element 2b , 2c are protected by this voltage clamp circuit from the energy stored in the current change rate suppression circuit 19a.

Further, a self-extinguishing type semiconductor element 2a is turned off by a snubber circuit composed of a snubber diode 4a, a snubber capacitor 5a and a snubber resistor 6a connected to the self-extinguishing type semiconductor element 2a. Voltage rise is suppressed. The voltage rise may be suppressed by another method. If the voltage rise is suppressed, the turn-off loss of the self-extinguishing type semiconductor element 2a is suppressed, so that the self-extinguishing type semiconductor elements (GCT) 2b and 2c to which only the voltage clamp circuit is connected are self-extinguishing. The breaking performance of the type semiconductor device (GCT) 2a is relatively improved.

The inverter device shown in FIGS. 4 and 5 applies a high gate on current to the self-extinguishing type semiconductor element 2a which is a GCT in synchronization with the turn-on operation of the self-extinguishing type semiconductor elements 2b and 2c which are a GCT. Giving function, GCT
The function of changing the threshold value according to the switching state of the self-extinguishing type semiconductor elements 2b and 2c, the configuration in which a voltage clamp circuit is commonly connected to the self-extinguishing type semiconductor elements 2b and 2c as GCT, Although various functions and configurations for improving the reliability of the inverter device are adopted, such as a configuration in which the self-extinguishing type semiconductor element 2a is connected to the DC voltage circuit 1 via the rate suppression circuit 19a, not all of them are necessarily used. It is not necessary to adopt the function or configuration, and the function or configuration may be appropriately selected and adopted according to the characteristics of the self-extinguishing type semiconductor element used. For example, by omitting the turn-on timing detection circuit 22a and increasing the gate-on current of the gate drive circuit 23a, the circuit configuration shown in FIG. 5 may be simplified to improve reliability.

In the above description of the operation, the operation of a portion related to one inverter bridge has been described, but the same applies to the operation of a portion related to another inverter bridge.

As described above, according to the third embodiment, the two self-extinguishing semiconductor elements 2b and 2c (2e, 2f) of the two-level inverter bridge are replaced with the other self-extinguishing semiconductor elements 2a (2d). ) Are connected in series, and the self-extinguishing semiconductor element 2a (2d) is
Since the turn-off operation is enabled regardless of the switching state of b, 2c (2e, 2f), an abnormal current can be cut off without damaging the self-extinguishing type semiconductor element, and the accidental spread of the accident is suppressed. Therefore, the effect that the reliability of the inverter device can be improved can be obtained.

Further, according to the third embodiment, the gate control circuit 26a controls the self-extinguishing type semiconductor elements 2b, 2c (2
e, 2f), the self-extinguishing type semiconductor element 2a (2d) is turned on in synchronization with the turn-on operation of (e, 2f).
The self-extinguishing type semiconductor element 2a (2d) can be reliably turned on, the occurrence of element damage due to partial current concentration on the semiconductor wafer can be suppressed, and the reliability of the inverter device can be improved. The effect is obtained.

Further, according to the third embodiment, different values are used for the threshold value for detecting an abnormal current according to the switching state of self-extinguishing type semiconductor elements 2b and 2c (2e and 2f). As a result, an abnormal current can be detected and cut off at high speed in accordance with the switching state at that time, and the effect of improving the reliability of the inverter device can be obtained.

Further, according to the third embodiment, a common voltage clamp circuit is provided for two self-extinguishing type semiconductor elements 2b and 2c (2e, 2f). , 2c (2e, 2f) at the time of off-drive, the power loss in the two-level inverter bridge can be reduced, and the effect of reducing the inverter device loss can be obtained.

Further, according to the third embodiment, the switching state of self-extinguishing semiconductor elements 2b, 2c (2e, 2f) when self-extinguishing semiconductor element 2a (2d) is turned off is held and fixed. As a result, the self-extinguishing type semiconductor elements 2b and 2c (2e and 2f) can be prevented from being erroneously interrupted by an accident current and damaged, thereby improving the reliability of the inverter device. Can be

Further, according to the third embodiment, since the two-level inverter bridge is connected to DC voltage circuit 1 via current change rate suppressing circuit 19a (19b), self-extinguishing type semiconductor elements 2b, 2c The increase rate of the on-current flowing at the time of (2e, 2f) turn-on can be suppressed, the current detection delay at the time of detection of an abnormal current is compensated, and the effect that the reliability of the inverter device can be improved can be obtained. .

Embodiment 4 FIG. 7 is a circuit diagram showing a configuration of an inverter device according to Embodiment 4 of the present invention. Embodiment 4 An inverter device according to Embodiment 4 of the present invention
Self-turn-off semiconductor elements 2a and 2d, freewheel diodes 3a and 3d, and a snubber circuit (snubber diodes 4a, 4a) in the inverter device (FIG. 4) according to the third embodiment.
4d, snubber capacitors 5a and 5d and snubber resistor 6
a, 6d) is changed as shown in FIG.

The self-extinguishing type semiconductor elements 2b and 2c
The voltage clamp circuits (clamp diodes 16a, 16b, clamp capacitor 17) are commonly used for (2e, 2f).
a, 17b and discharge resistors 18a, 18b) are connected.

The other components of the inverter device according to the fourth embodiment are the same as those of the inverter device according to the third embodiment (FIGS. 4 and 5), and a description thereof will not be repeated.

Further, the installation position of the current detection circuit 9a (9d) is not particularly limited as long as the current flowing through the self-extinguishing type semiconductor element 2a (2d) can be equivalently detected.

Next, the operation will be described. In the inverter device according to the fourth embodiment, the current change rate suppression circuit 19a (19b) includes the clamp diode 16a (1
6b) and the discharge resistor 18a (18b) form a closed circuit, so that the self-extinguishing type semiconductor element 2a (2d) is not arranged in the closed circuit, and the self-extinguishing type semiconductor element 2a (2d) is turned off. In this case, all of the energy stored in the current change rate suppression circuit 19a is not absorbed by the snubber capacitor 5a (5d).

Therefore, the capacitance Cs of the snubber capacitors 5a (5d) is not limited to the condition of the expression (4).
Can be designed, and the capacitance is designed to be smaller than that of snubber capacitor 5a (5d) in the third embodiment.

The other operations of the inverter device according to the fourth embodiment are the same as those of the inverter device according to the third embodiment (FIGS. 4 and 5), and a description thereof will not be repeated.

As described above, according to the fourth embodiment, in addition to the effects of the third embodiment, the snubber capacitor 5
The effect that the capacitance of a (5d) can be designed to be small can be obtained.

Embodiment 5 FIG. FIG. 8 is a circuit diagram showing a configuration of an inverter device according to Embodiment 5 of the present invention. An inverter device according to Embodiment 5 of the present invention
The voltage clamp circuit (clamp diodes 16a, 16b) in the inverter device (FIG. 4) according to the third embodiment.
Clamp capacitors 17a, 17b and discharge resistor 18
a, 18b) are changed as shown in FIG.

In the inverter device according to the fifth embodiment (FIG. 8), clamp diode 16a (16
b), a voltage clamp circuit composed of a clamp capacitor 17a (17b) and a discharge resistor 18a (18b) is commonly connected to the self-extinguishing type semiconductor elements 2a to 2c (2d to 2f).

The other components of the inverter device according to the fifth embodiment are the same as those of the inverter device according to the third embodiment (FIGS. 4 and 5), and a description thereof will not be repeated.

Further, the installation position of the current detection circuit 9a (9d) is not particularly limited as long as the current flowing through the self-extinguishing type semiconductor element 2a (2d) can be equivalently detected.

Next, the operation will be described. When the self-extinguishing type semiconductor element 2a (2d) is turned off, the energy accumulated in the current change rate suppression circuit 19a (19d) is first absorbed by the snubber capacitor 5a (5d), but the snubber capacitor 5a (5d). Is higher than the voltage E of the DC voltage circuit 1, the snubber capacitor 5a
(5d) and absorbed by the clamp capacitors 17a (17b). Therefore, the snubber capacitor 5a (5
The capacitance d) can be designed to be small.

The other operations of the inverter device according to the fifth embodiment are the same as those of the inverter device according to the third embodiment (FIGS. 4 and 5), and thus description thereof will be omitted.

As described above, according to the fifth embodiment, a common voltage clamp circuit is provided for self-extinguishing semiconductor elements 2a to 2c (2d to 2f). The voltage at the time of off driving of 2a to 2c (2d to 2f) is suppressed, and the capacitance of snubber capacitor 5a (5d) connected to self-extinguishing type semiconductor element 2a (2d) for interrupting abnormal current is reduced. Thus, the effect that the inverter device can be downsized can be obtained.

Embodiment 6 FIG. FIG. 9 is a circuit diagram showing a configuration of an inverter device according to Embodiment 6 of the present invention. An inverter device according to Embodiment 6 of the present invention
The voltage clamp circuit (clamp diodes 16a, 16b,
Clamp capacitors 17a, 17b and discharge resistor 18
a, 18b) are changed as shown in FIG. 9, and the discharge resistors 18a, 18b are also used as snubber resistors.

In the inverter device according to the sixth embodiment (FIG. 9), snubber resistors 6a, 6
d is omitted, and the clamp diodes 16a,
The anode of 16b is connected to the cathode of snubber diodes 4a and 4d, respectively.

The other components of the inverter device according to the sixth embodiment are the same as those of the inverter device according to the fifth embodiment (FIG. 8), and a description thereof will not be repeated. Also, the operation is the same as that of the inverter device according to the fifth embodiment, and the description thereof is omitted.

Further, the installation position of the current detection circuit 9a (9d) is not particularly limited as long as the current flowing through the self-extinguishing type semiconductor element 2a (2d) can be equivalently detected.

As described above, according to the sixth embodiment, the anodes of the clamp diodes 16a and 16b are connected to the cathodes of the snubber diodes 4a and 4d, respectively, and the discharge resistor 18a (18b) of the voltage clamp circuit is connected to the snubber circuit. Since the snubber resistor 6a (6d) is also used as the snubber resistor 6a (6d), the number of parts is reduced, and the size and cost of the inverter device can be reduced. .

Embodiment 7 FIG. FIG. 10 is a circuit diagram showing a configuration of an inverter device according to Embodiment 7 of the present invention. FIG. 11 is a diagram showing an example of the gate drive circuit of the self-extinguishing type semiconductor device in FIG. 10 and its peripheral circuits.

In FIG. 10, reference numeral 51 denotes a DC voltage circuit for generating a voltage E between the terminals P and C and a voltage E between the terminals C and N with the terminal C as a neutral point. Reference numerals 52a and 52g denote self-extinguishing semiconductor devices such as GCTs for interrupting abnormal current (first interrupting self-extinguishing semiconductor devices), and 52f and 52m similarly denote self-extinguishing semiconductor devices such as GCT for interrupting abnormal current. Arc type semiconductor element (second self-extinguishing type semiconductor element for interrupting)
It is. 52b to 52e and 52h to 52k are self-extinguishing semiconductor devices (third to sixth self-extinguishing semiconductor devices) such as inverter-driven GCTs.

Self-extinguishing type semiconductor elements 52b to 52 driven by an inverter according to a predetermined switching signal
"e" constitutes one three-level inverter bridge, and self-extinguishing type semiconductor elements 52h to 52k, which are inverter-driven according to a predetermined switching signal, constitute one three-level inverter bridge.

53a and 53g are freewheel diodes (first breaking freewheel diodes) connected in anti-parallel to the self-extinguishing type semiconductor elements 52a and 52g, respectively. 53b to 53e and 53h are freewheel diodes (second blocking freewheel diodes) connected in antiparallel to the semiconductor elements 52f and 52m, respectively.
To 53k are self-extinguishing type semiconductor elements 52b to 52e, 5
Freewheel diodes (third to sixth freewheel diodes) connected in anti-parallel to 2h to 52k, respectively.

Numerals 54a and 54g are snubber diodes constituting snubber circuits (first voltage rise rate suppressing circuits) connected to self-extinguishing type semiconductor elements 52a and 52g, respectively. Snubber capacitors constituting snubber circuits connected to the respective type semiconductor elements 52a and 52g.
Are snubber resistors which are connected in parallel with the snubber diodes 54a and 54g, respectively, and form snubber circuits connected to the self-extinguishing semiconductor elements 52a and 52g, respectively.

54f and 54m are snubber diodes constituting snubber circuits (second voltage rise rate suppressing circuits) connected to the self-extinguishing type semiconductor elements 52f and 52m, respectively. Snubber capacitors constituting snubber circuits connected to the respective type semiconductor elements 52f and 52m.
Are snubber resistors which are connected in parallel to the snubber diodes 54f and 54m, respectively, and constitute a snubber circuit connected to the self-extinguishing semiconductor elements 52f and 52m, respectively.

Reference numerals 59a, 59b, 59c and 59d denote current detecting circuits for detecting currents conducted to the self-extinguishing type semiconductor elements 52a, 52f, 52g and 52m, respectively.

Reference numeral 66a denotes self-extinguishing type semiconductor elements 52b and 52 due to the energy stored in the current change rate suppressing circuit 69a.
c is a clamp diode that constitutes a second voltage clamp circuit that suppresses a voltage rise during off-drive of c.
Is a clamp capacitor that also forms the second voltage clamp circuit, and 68a is a discharge resistor that also forms the second voltage clamp circuit.

66b is a self-extinguishing type semiconductor element 52d, 52d by the energy stored in the current change rate suppressing circuit 69b.
67c is a clamp diode that constitutes a third voltage clamp circuit that suppresses a voltage rise during the OFF drive of e.
Is a clamp capacitor similarly constituting the third voltage clamp circuit, and 68b is a discharge resistor similarly constituting the third voltage clamp circuit.

Reference numeral 66c designates self-extinguishing type semiconductor elements 52h and 52c by the energy stored in the current change rate suppressing circuit 69c.
j is a clamp diode that constitutes a second voltage clamp circuit that suppresses a voltage rise at the time of off-drive of j.
Is a clamp capacitor similarly forming the second voltage clamp circuit, and 68c is a discharge resistor similarly forming the second voltage clamp circuit.

66d is a self-extinguishing type semiconductor element 52i, 52d by the energy stored in the current change rate suppressing circuit 69d.
k is a clamp diode that constitutes a third voltage clamp circuit that suppresses a voltage rise during the off drive of k.
Is a clamp capacitor similarly constituting the third voltage clamp circuit, and 68d is a discharge resistor similarly constituting the third voltage clamp circuit.

Reference numerals 69a and 69c denote current rate-of-change suppressing circuits (first current rate-of-change suppressing circuits) having an inductance component for suppressing a change in the conducting current. A current change rate suppression circuit having an inductance component for suppressing the change (second
Current change rate suppression circuit). One end of the reference numeral 60 is connected to the output terminal 63a between the self-extinguishing type semiconductor elements 52c and 52d, and the other end thereof is self-extinguishing type semiconductor elements 52i and 52j.
Is a load circuit connected to the output terminal 63b.

The GCT has a larger safe operation area than the GTO, can cut off the rated current without using a snubber circuit, and has a large withstand voltage increase rate and a high withstand current rate. If the current rise rate of the circuit during actual use increases, the reverse recovery current of the freewheel diode in particular increases, and consequently the reverse recovery loss increases,
Depending on the degree of the loss value, damage may occur.
Therefore, current rate-of-change suppression circuits 69a to 69d are provided to ensure low loss or high reliability of the inverter device.

Note that the current change rate suppression circuits 69a to 69d
Is constituted by a reactor, a wiring, a fuse and the like, and the fuse may be omitted as long as the reliability of the off driving operation of the self-extinguishing type semiconductor elements 52a, 52f, 52g and 52m is guaranteed.

Further, the total inductance La of the current change rate suppression circuit 69a is designed as follows. The maximum interruptable current of the self-extinguishing type semiconductor element 52a which is a GCT is set to Ia, the threshold value It is set to a value equal to or less than the maximum interrupting current of the self-extinguishing type semiconductor elements 52b to 52e which are GCTs, and the DC voltage The voltage between the terminals P and C or between the terminals C and N by the circuit 51 is E, and the self-extinguishing type semiconductor elements 52a and 52f which are GCT after the current detecting circuits 59a and 59b detect a current equal to or more than the threshold current. Assuming that the operation delay time until the overcurrent is cut off is Tm, the total inductance La of the current change rate suppression circuit 69a is designed according to the equation (3). Similarly, current change rate suppression circuits 69b-69
Design the total inductances Lb to Ld of d.

Therefore, if the operation delay time Tm can be reduced, the total inductances La to Ld can be reduced, and if the total inductances La to Ld are reduced, the capacitance of the clamp capacitors 67a to 67d can be reduced. Can also.

The capacitance Cs of the snubber capacitor 55a is designed as follows. When the self-extinguishing type semiconductor element 52a, which is a GCT, is turned off, all the energy stored in the current change rate suppression circuit 69a is absorbed by the snubber capacitor 55a. Then, the charging voltage of the snubber capacitor 55a is applied to the clamp diode 66a. Therefore, assuming that the withstand voltage of the clamp diode 66a is V, the maximum interruptable current of the self-extinguishing type semiconductor element 52a of GCT is Ia, and the total inductance of the current change rate suppressing circuit 69a is La, the snubber capacitor 5
The capacitance Cs of 5a is designed according to equation (4). Similarly, the capacitance Cs of the snubber capacitors 55f, 55g, and 55m is designed.

Reference numerals 76a and 76b denote coupling diodes (first and second coupling diodes) connected from terminal C of DC voltage circuit 51 to the anode of self-extinguishing semiconductor device 52c and the cathode of self-extinguishing semiconductor device 52d, respectively. ), And 76c and 76d are coupling diodes (first and second couplings) respectively connected from the terminal C of the DC voltage circuit 51 to the anode of the self-extinguishing type semiconductor element 52i and the cathode of the self-extinguishing type semiconductor element 52j. Diode).

Also, in FIG. 11, 71a and 71b
Is a threshold value selection circuit (first and second threshold value change circuits) for respectively selecting the magnitude of the threshold value It for detecting an abnormal current in accordance with the output of the switching signal holding circuit 74a; Reference numerals 72a and 72b denote turn-on timing detection circuits for detecting timings of executing the turn-on operations of the self-extinguishing semiconductor elements 52a and 52f in accordance with the output of the switching signal holding circuit 74a.

Reference numerals 73b to 73e denote gate drive circuits (third to sixth gate drive circuits) for driving inverter-driven self-extinguishing semiconductor elements 52b to 52e, respectively, and 73a and 73f denote abnormal current cutoffs. Drive circuits (seventh and eighth gate drive circuits) for driving the self-extinguishing type semiconductor elements 52a and 52f, respectively.
74a is supplied with a switching signal to the self-extinguishing type semiconductor elements 52b to 52e generated by a switching signal generating circuit (not shown), and is supplied from the gate control circuit 65a or the gate control circuit 65b to the self-extinguishing type semiconductor element 52a.
Alternatively, a switching signal holding circuit that holds a switching signal to the self-extinguishing semiconductor elements 52b to 52e when an off signal for driving the self-extinguishing semiconductor element 52f to be turned off, and outputs the held signal ( (Fifth gate control circuit).

64a and 64b are threshold value selection circuits 7
Threshold value It from 1a, 71b and current detection circuit 59
a comparison circuit for comparing the output Id of the gate drive circuits 73a and 73b with the outputs of the comparison circuits 64a and 64b and the outputs of the turn-on timing detection circuits 72a and 72b, respectively. Thus, a gate control circuit (third control) for controlling the switching states of the self-extinguishing semiconductor elements 52a and 52f, respectively
And a fourth gate control circuit).

A circuit (not shown) similar to the circuit shown in FIG. 11 is also provided in self-extinguishing type semiconductor elements 52g-52k, 52m and current detecting circuits 59c, 59d.

Next, the operation will be described. FIG. 12 shows FIG.
12 is a timing chart illustrating the operation of the inverter device shown in FIG.

Switching signal holding circuit 74a shown in FIG.
Are supplied with switching signals to the self-extinguishing type semiconductor elements 52b to 52e generated by a switching signal generating circuit (not shown), and are supplied from the gate control circuit 65a or the gate control circuit 65b to the self-extinguishing type semiconductor element 52a or the self-extinguishing type. When an off signal for driving off the arc-type semiconductor element 52f is output, the self-extinguishing type semiconductor element 52b
To 52e, and outputs the held signal continuously for a predetermined period. The switching signal holding circuit 74a outputs the supplied switching signal as it is, unless the gate control circuit 65a or 65b outputs an off signal.

Threshold value selecting circuit 71 according to the signal
a, 71b select the magnitude of the threshold value It, and detect the timing at which the turn-on timing detection circuits 72a, 72b execute the turn-on operation of the self-extinguishing type semiconductor elements 52a, 52f. On the other hand, the threshold value It and the output I of the current detection circuits 59a and 59b are determined by the comparison circuits 64a and 64b.
The gate driving circuits 73a and 73f are controlled by the gate control circuits 65a and 65b in accordance with the comparison result and the outputs of the turn-on timing detection circuits 72a and 72b, and the switching of the self-extinguishing type semiconductor elements 52a and 52f is performed. Each state is controlled.

The output of the switching signal holding circuit 74a is supplied to the gate driving circuits 73b to 73e, and the switching states of the self-extinguishing type semiconductor elements 52b to 52e are controlled by the gate driving circuits 73b to 73e, respectively.

The detailed operation of each unit will be described below with reference to the timing chart of FIG. First, the current I detected by the current detection circuits 59a, 59b when the switching operation of the self-extinguishing type semiconductor elements 52b to 52e is performed.
d will be described.

In the switching operation of the self-extinguishing type semiconductor elements 52b to 52e, a short-circuit prevention time Td is provided when the semiconductor device is turned on, as in the third embodiment.

Thus, the self-extinguishing type semiconductor element 52
When b-52e are driven, current detection circuits 59a, 59
FIG. 12 shows the detection current Id based on b according to the polarity (direction) of the load current Io. That is, when the load current has a positive polarity (the direction shown in FIG. 10), the detection current Id by the current detection circuit 59b becomes maximum immediately after the time T6 when the self-extinguishing type semiconductor element 52c performs the turn-on operation. The value is the reverse recovery current Irr of the freewheel diode 53e. In this case, the detection current Id by the current detection circuit 59a becomes maximum immediately after time T8 when the self-extinguishing type semiconductor element 52b performs the turn-on operation, and the maximum value is the load current Io and the coupling diode 76a.
With the reverse recovery current Irr.

On the other hand, when the load current has a negative polarity (in a direction opposite to the direction shown in FIG. 10), the self-extinguishing type semiconductor element 52d
Immediately after the time T10 at which the turn-on operation is performed, the detection current Id by the current detection circuit 59a becomes maximum, and the maximum value is the reverse recovery current Irr of the freewheel diode 53b.
become. In that case, the self-extinguishing type semiconductor element 52e
Immediately after the time T12 when the turn-on operation is performed, the detection current Id detected by the current detection circuit 59b becomes maximum, and the maximum value is the load current Io and the reverse recovery current Id of the coupling diode 76b.
rr.

Next, the turn-on timing detection circuit 72
self-extinguishing type semiconductor elements 52a, 52b
A detailed operation when the gate signal is supplied to 2f will be described. In general, since the large-capacity GCT has a very large wafer diameter, when a large current rise occurs at the time of turn-on, all the wafer surfaces are not turned on, and a portion near the gate electrode is turned on first. Then, the current flows intensively at the part where the transistor is partially turned on, so that a local increase in the junction temperature occurs. A high gate-on current is supplied by the gate drive circuits 73a and 73f in order to increase the area that is partially turned on and to suppress a local increase in the junction temperature.

The rise in the current flowing through the self-extinguishing type semiconductor element 52a is caused by the self-extinguishing type semiconductor element 52a.
Since the turn-on timings b and 52d are after the time T8 and the time T10, respectively, the turn-on timing detection circuit 72a
The self-extinguishing type semiconductor elements 52b and 52d of the output of a
Are detected at the times T8 and T10 from the values of the two outputs corresponding to, and the detection signals are supplied to the gate control circuit 65a.
The gate control circuit 65a controls the gate drive circuit 73a at that timing, and causes the gate drive circuit 73a to supply a high gate-on current to the self-extinguishing type semiconductor element 52a.

Similarly, a rise in the current conducted to self-extinguishing type semiconductor element 52f appears after time T6 and time T12, which are the turn-on timings of self-extinguishing type semiconductor elements 52c and 52e. Therefore, the turn-on timing detection circuit 72b outputs the self-extinguishing type semiconductor element 52 of the output of the switching signal holding circuit 74a.
From the two output values corresponding to c and 52e, time T6, T
12 and supplies the detection signal to the gate control circuit 65b. The gate control circuit 65b controls the gate drive circuit 73f at that timing, and controls the gate drive circuit 73f.
Then, a high gate on current is supplied to the self-extinguishing type semiconductor element 52f.

The polarity of the load current Io is detected, and only one of the timings T8 and T10 is detected based on the polarity, and the gate drive circuit 73a supplies the high gate on current at that timing. It may be. Similarly, based on the polarity, time T6
Alternatively, only one of the timings of the time T12 may be detected, and the high gate-on current may be supplied by the gate drive circuit 73f at that timing.

Next, detailed operations of threshold value selecting circuits 71a and 71b will be described. Normally, from time T10 when the self-extinguishing type semiconductor element 52d is turned on to time T8 when the self-extinguishing type semiconductor element 52b is turned on.
In the period until the self-extinguishing type semiconductor element 52b is turned off, the reverse recovery current Ir of the freewheel diode 53b is independent of the polarity of the load current Io.
The positive polarity current exceeding r is not detected by the current detection circuit 59a. However, the self-extinguishing type semiconductor device 52
b, 52d or freewheeling diodes 53b, 5
When an abnormality occurs in 3c, a positive current exceeding the reverse recovery current Irr of the freewheel diode 53b may be detected.

The threshold value selecting circuit 71a determines the period from the time T10 when the self-extinguishing type semiconductor element 52d is turned on to the time T8 when the self-extinguishing type semiconductor element 52b is turned on among the outputs of the switching signal holding circuit 74a. Are detected from two output values corresponding to the self-extinguishing type semiconductor elements 52b and 52d, and the threshold value It in that period is detected.
, A predetermined value (“L1” in the figure) exceeding the maximum value of the reverse recovery current Irr of the freewheel diode 53b is selected and supplied to the comparison circuit 64a. In other periods (the period from time T8 to time T10), the threshold value selection circuit 71a sets the maximum value of the load current Io and the reverse recovery current Ir of the coupling diode 76a as the threshold value It.
A predetermined value exceeding the sum of the maximum value of r ("H1" in the figure)
Is supplied to the comparison circuit 64a.

The comparison circuit 64a includes a current detection circuit 59
a, and compares the supplied threshold value It with the supplied threshold value It, and supplies the comparison result to the gate control circuit 65a. The gate control circuit 65a determines whether the detected current Id is equal to or greater than the threshold value It. Determines that an abnormality has occurred,
The gate driving circuit 73a is controlled to turn off the self-extinguishing type semiconductor element 52a.

When the gate control circuit 65a once supplies the off signal to the gate drive circuit 73a, it is preferable to continuously supply the off signal for a predetermined period. For example, the time when the detection current Id becomes equal to or more than the threshold value It is held by the comparison circuit 64a, and the OFF signal is continuously supplied to the gate control circuit 65a for a predetermined period from that time.

Similarly, the threshold value selecting circuit 71b changes the time from the time T6 when the self-extinguishing type semiconductor element 52c is turned on to the time T1 when the self-extinguishing type semiconductor element 52e is turned on.
The period up to 2 is detected from the two output values corresponding to the self-extinguishing type semiconductor elements 52c and 52e among the outputs of the switching signal holding circuit 74a, and is set as the threshold value It in that period as the freewheel diode 53e. A predetermined value exceeding the maximum value of the reverse recovery current Irr (“L” in FIG.
2 ") and supplies it to the comparison circuit 64b. In the other periods (the period from time T12 to time T6), the threshold value selection circuit 71b sets the threshold value It between the maximum value of the load current Io and the maximum value of the reverse recovery current Irr of the coupling diode 76b. A predetermined value exceeding the sum (“H” in the figure)
2 ") and supplies it to the comparison circuit 64b.

The comparison circuit 64b includes a current detection circuit 59
b, and compares the supplied threshold value It with the supplied threshold value It, and supplies the comparison result to the gate control circuit 65b. The gate control circuit 65b determines whether the detected current Id is equal to or greater than the threshold value It. Determines that an abnormality has occurred,
The gate driving circuit 73f is controlled to turn off the self-extinguishing type semiconductor element 52f.

When the gate control circuit 65b once supplies the off signal to the gate drive circuit 73f, it is preferable to continuously supply the off signal for a predetermined period. For example, the time when the detection current Id becomes equal to or more than the threshold value It is held by the comparison circuit 64b, and the OFF signal is continuously supplied to the gate control circuit 65b for a predetermined period from that time.

At the same time that the gate control circuits 65a and 65b output the OFF signal, information to that effect is supplied to the switching signal holding circuit 74a, and the switching signal holding circuit 74a operates regardless of the change in the supplied switching signal. , Hold the value of the switching signal. As described above, when an overcurrent flows through the self-extinguishing type semiconductor elements 52b to 52e and the self-extinguishing type semiconductor element 52a (52f) is turned off, the self-extinguishing type semiconductor elements 52b to 52e are turned off.
2e does not interrupt the current, reducing the likelihood of self-turn-off semiconductor elements 52b-52e leading to turn-off damage.

Freewheel diodes 53b and 53e
If the time during which the reverse recovery operation of the coupling diodes 76a and 76b is performed can be specified in advance, after the reverse recovery operation of those diodes, the levels of the thresholds H1 and H2 exceed the maximum value of the load current Io. May be changed to a predetermined value, and the levels of L1 and L2 may be changed to zero. In this case, there are four levels of the threshold value It.

In the circuit shown in FIG. 11, information for turning off self-extinguishing type semiconductor elements 52a and 52f is supplied from gate control circuits 65a and 65b to switching signal holding circuit 74a. As shown by the broken line, the outputs of the comparison circuits 64a and 64b are directly supplied to the switching signal holding circuit 74a, and based on the output,
The gate control circuits 65a and 65b may detect that the self-extinguishing type semiconductor elements 52a and 52f are turned off.

Next, the clamp diodes 66a, 66b,
Clamp capacitors 67a, 67b and discharge resistor 68
Two voltage clamp circuits constituted by a and 68b will be described.

Self-extinguishing type semiconductor element 52b which is a GCT
The energy stored in the current change rate suppression circuits 69a and 69b by the switching operations of
As in the case of using the self-extinguishing type semiconductor element 52b
Not as small as can be lost at ~ 52e.

Therefore, a clamp diode 66a, a clamp capacitor 67a and a discharge resistor 68 shown in FIG.
a, the energy stored in the current change rate suppressing circuit 69a is temporarily absorbed by the clamp capacitor 67a, and the second voltage clamp circuit is configured by the clamp diode 66b, the clamp capacitor 67b, and the discharge resistor 68b. The energy accumulated in the current change rate suppression circuit 69b is temporarily absorbed by the clamp capacitor 67b by the voltage clamp circuit 3.

By providing the second voltage clamp circuit at a location commonly applied to the self-extinguishing type semiconductor elements 52b and 52d, the self-extinguishing type semiconductor elements 52b and 52d can be
It protects from the energy stored in the current change rate suppression circuit 69a. Further, by providing the third voltage clamp circuit at a location commonly applied to the self-extinguishing semiconductor elements 52c and 52e, the self-extinguishing semiconductor elements 52c and 52e are provided.
From the energy stored in the current change rate suppression circuit 69b.

The snubber diode 54a and the snubber capacitor 5 connected to the self-extinguishing type semiconductor element 52a
The snubber circuit composed of the snubber resistor 5a and the snubber resistor 56a suppresses a voltage rise that occurs when the self-extinguishing type semiconductor element 52a is turned off. Similarly, the snubber diode 54 connected to the self-extinguishing type semiconductor element 52f
f, a snubber capacitor 55f and a snubber resistor 56f to form a self-extinguishing type semiconductor element 5
The voltage rise that occurs when 2f turns off is suppressed. The voltage rise may be suppressed by another method. If the rise in voltage is suppressed, the turn-off loss of the self-extinguishing type semiconductor elements 52a and 52f is suppressed, so that the self-extinguishing type semiconductor elements (GCT) 52b to 52e to which only the voltage clamp circuit is connected are self-extinguishing. The breaking performance of the arc-extinguishing type semiconductor devices (GCT) 52a and 52f is relatively improved.

The inverter device shown in FIGS. 10 and 11 has a self-extinguishing type semiconductor element 52b-
A function of applying a high gate-on current to the self-extinguishing type semiconductor elements 52a and 52f which are GCTs in synchronization with the turn-on operation of 52e, and a self-extinguishing type semiconductor element 52b which is a GCT
Function to change the threshold value according to the switching state of the self-extinguishing type semiconductor device 52b
Improvement of the reliability of the inverter device, such as a configuration in which a voltage clamp circuit is commonly connected to 52e and a configuration in which self-extinguishing type semiconductor elements 52a, 52f are connected to DC voltage circuit 51 via current change rate suppression circuits 69a, 69b. Various functions and configurations are provided, but it is not necessary to employ all the functions and configurations, and the functions and configurations are appropriately selected and adopted according to the characteristics of the self-extinguishing semiconductor device to be used. You may make it. For example, the turn-on timing detection circuits 72a, 72b are omitted, and the gate drive circuits 73a,
By increasing the gate-on current of 73f, it is possible to simplify the circuit configuration shown in FIG. 11 and improve the reliability.

In the above description of the operation, the operation of a portion related to one inverter bridge is described, but the same applies to the operation of a portion related to another inverter bridge.

As described above, according to the seventh embodiment, the four self-extinguishing semiconductor elements 52b to 52e (52h to 52k) of the three-level inverter bridge are replaced with the other self-extinguishing semiconductor elements 52a and 52f. (52g, 52m) are connected in series, and the self-extinguishing type semiconductor elements 52a, 52f
(52g, 52m) is replaced with two self-extinguishing type semiconductor elements 52.
Since the turn-off operation is enabled irrespective of the switching state of b to 52e (52h to 52k), the abnormal current can be cut off without damaging the self-extinguishing type semiconductor element, and the occurrence of an accident is suppressed. Therefore, the effect that the reliability of the inverter device can be improved can be obtained.

According to the seventh embodiment, gate control circuits 65a and 65b are provided with self-extinguishing type semiconductor element 52b.
To 52e (52h to 52k) in synchronism with the turn-on operation of the self-extinguishing type semiconductor elements 52a and 52f (52g, 52k).
m), the self-extinguishing type semiconductor elements 52a, 52f (52g, 52m) can be reliably turned on, and element damage occurs due to partial current concentration on the semiconductor wafer. Is suppressed and the reliability of the inverter device can be improved.

Further, according to the seventh embodiment, different values are used for the threshold value for detecting an abnormal current according to the switching state of self-extinguishing type semiconductor elements 52b to 52e (52h to 52k). As a result, an abnormal current can be detected and cut off at high speed in accordance with the switching state at that time, and the effect of improving the reliability of the inverter device can be obtained.

Further, according to the seventh embodiment, two self-extinguishing type semiconductor elements 52b, 52d (52c, 52
e) Since a common voltage clamp circuit is provided for (52h, 52j) (52i, 52k), the self-extinguishing type semiconductor elements 52b, 52d (52c, 52e) (52h, 52)
j) The voltage during off driving of (52i, 52k) is suppressed, the power loss in the three-level inverter bridge can be reduced, and the effect of reducing the loss of the inverter device can be obtained.

Further, according to the seventh embodiment, the self-extinguishing semiconductor elements 52b to 52 at the time of the turn-off operation of the self-extinguishing semiconductor elements 52a and 52f (52g, 52m).
e (52h-52k) are held and fixed, so that the self-extinguishing type semiconductor elements 52b-5
2e (52h to 52k) can be prevented from being erroneously interrupted and damaged, thereby improving the reliability of the inverter device.

Further, according to the seventh embodiment, since the three-level inverter bridge is connected to the DC voltage circuit via current change rate suppressing circuits 69a, 69b (69c, 69d), the self-extinguishing type semiconductor element 52b to 52e (5
The increase rate of the on-current flowing at the time of turn-on from 2h to 52k) can be suppressed, and the current detection delay at the time of detecting an abnormal current is compensated, so that the effect of improving the reliability of the inverter device can be obtained.

Embodiment 8 FIG. FIG. 13 is a circuit diagram showing a configuration of an inverter device according to Embodiment 8 of the present invention. An inverter device according to Embodiment 8 of the present invention
Self-extinguishing type semiconductor elements 52a, 52f, 52g, 52 in the inverter device (FIG. 10) according to the seventh embodiment.
m, freewheeling diodes 53a, 53f, 53
g, 53m, a snubber circuit (snubber diodes 54a, 5
4f, 54g, 54m, snubber capacitors 55a, 55
f, 55g, 55m and snubber resistors 56a, 56f,
56g, 56m) are changed as shown in FIG.

The self-extinguishing type semiconductor elements 52b, 52
d (52c, 52e) (52h, 52j) (52i, 5
2k) includes a common voltage clamp circuit (clamp diodes 66a to 66d, clamp capacitors 67a to 67d).
d, discharge resistors 68a to 68d) are connected.

The other components of the inverter device according to the eighth embodiment are the same as those of the inverter device according to the seventh embodiment (FIGS. 10 and 11), and a description thereof will not be repeated.

The positions of the current detection circuits 59a to 59d are determined by the self-extinguishing type semiconductor elements 52a, 52f, 52g,
Any position can be used as long as the current flowing through 52 m can be equivalently detected, and there is no particular limitation.

Next, the operation will be described. In the inverter device according to the eighth embodiment, current change rate suppression circuits 69a to 69d are provided with clamp diodes 66a to 66d.
d and the discharge resistors 68a to 68d, respectively, constitute a closed circuit, so that the self-extinguishing type semiconductor elements 52a, 52f, 52g, 52m, etc. are not arranged in each closed circuit, and the self-extinguishing type semiconductor elements 52a, 52f , 52g, 5
When the 2m is turned off, the current change rate suppression circuit 69a
All of the energy stored in .about.69d is not absorbed by snubber capacitors 55a, 55f, 55g, and 55m.

Therefore, the snubber capacitors 55a, 55f, 55g, and 5 are not limited to the condition of the expression (4).
A capacitance Cs of 5 m can be designed, and the snubber capacitors 55a, 55f, 55g,
The capacitance is designed to be smaller than 55 m.

The other operations of the inverter device according to the eighth embodiment are the same as those of the inverter device according to the seventh embodiment (FIGS. 10 and 11), and a description thereof will not be repeated.

As described above, according to the eighth embodiment, in addition to the effects of the seventh embodiment, the snubber capacitor 5
The effect that the capacitance of 5a, 55f, 55g, and 55m can be designed to be small can be obtained.

Embodiment 9 FIG. FIG. 14 is a circuit diagram showing a configuration of an inverter device according to Embodiment 9 of the present invention. Embodiment 9 An inverter device according to Embodiment 9 of the present invention includes:
Voltage clamp circuit (clamp diodes 66a-66) in the inverter device (FIG. 10) according to the seventh embodiment.
d, the installation positions of the clamp capacitors 67a to 67d and the discharge resistors 68a to 68d) are changed as shown in FIG.

In the inverter device according to the ninth embodiment (FIG. 14), the second voltage clamp circuit composed of clamp diode 66a, clamp capacitor 67a and discharge resistor 68a is a self-extinguishing type semiconductor device.
A third voltage clamp circuit, which is commonly connected to 2a, 52b, 52d and includes a clamp diode 66b, a clamp capacitor 67b, and a discharge resistor 68b, is commonly connected to the self-extinguishing type semiconductor elements 52c, 52e, 52f. .

Similarly, the clamp diode 66c,
A second voltage clamp circuit including a clamp capacitor 67c and a discharge resistor 68c is commonly connected to the self-extinguishing semiconductor elements 52g, 52h, and 52j, and includes a clamp diode 66d, a clamp capacitor 67d, and a discharge resistor 68d. A third voltage clamp circuit is commonly connected to the self-extinguishing type semiconductor elements 52i, 52k, 52m.

The other components of the inverter device according to the ninth embodiment are the same as those of the inverter device according to the seventh embodiment (FIGS. 10 and 11), and a description thereof will not be repeated.

The current detection circuits 59a to 59d are installed at self-extinguishing type semiconductor elements 52a, 52f, 52g,
Any position can be used as long as the current flowing through 52 m can be equivalently detected, and there is no particular limitation.

Next, the operation will be described. When the self-extinguishing type semiconductor element 52a is turned off, the energy stored in the current change rate suppressing circuit 69a is first absorbed by the snubber capacitor 55a.
When the charging voltage of the DC voltage a becomes equal to or higher than the voltage E of the DC voltage circuit 51, the snubber capacitor 55a and the clamp
a.

Similarly, self-extinguishing type semiconductor elements 52f and 5f
When the 2g and 52m are turned off, the energy stored in the current change rate suppression circuits 69f, 69g and 69m is first absorbed by the snubber capacitors 55f, 55g and 55m, respectively.
The charging voltage of 55 g and 55 m is the voltage E of the DC voltage circuit 51.
Then, the snubber capacitors 55b, 55c, 55
d and the clamp capacitors 67b, 67c, 67d.

Therefore, snubber capacitors 55a, 55a
The capacitance of 5f, 55g, and 55m can be designed to be small.

The other operations of the inverter device according to the ninth embodiment are the same as those of the inverter device according to the seventh embodiment (FIGS. 10 and 11), and thus the description thereof will be omitted.

As described above, according to the ninth embodiment, self-extinguishing type semiconductor elements 52a, 52b, 52d (5
2c, 52e, 52f) (52g, 52h, 52j)
Since a common voltage clamp circuit is provided for (52i, 52k, 52m), self-extinguishing type semiconductor elements 52a, 52
2b, 52d (52c, 52e, 52f) (52g, 5
2h, 52j) (52i, 52k, 52m), the voltage at the time of off driving is suppressed, and snubber capacitors 55a connected to self-extinguishing semiconductor elements 52a, 52f, 52g, 52m for interrupting abnormal current, respectively. 55f, 55
g, 55 m of capacitance can be reduced and the inverter device can be downsized.

Embodiment 10 FIG. FIG. 15 is a circuit diagram showing a configuration of an inverter device according to Embodiment 10 of the present invention. The inverter device according to the tenth embodiment of the present invention is different from the inverter device according to the ninth embodiment (FIG. 14) in the second and third voltage clamp circuits (clamp diodes 66a to 66d, clamp capacitors 67a to 67d).
FIG. 1 shows the installation positions of 67d and discharge resistors 68a to 68d.
5 and the discharge resistors 68a to 68a
8d is also used as a snubber resistor.

In the inverter device according to the tenth embodiment (FIG. 15), snubber resistor 56 of the snubber circuit is used.
a, 56f, 56g, and 56m are omitted, and the anodes of the clamp diodes 66a to 66d are connected to the cathodes of the snubber diodes 54a, 54f, 54g, and 54m, respectively.

The other components of the inverter device according to the tenth embodiment are the same as those of the inverter device according to the ninth embodiment (FIG. 14), and therefore description thereof is omitted. Also, the operation is the same as that of the inverter device according to the ninth embodiment, and the description thereof is omitted.

The positions of the current detecting circuits 69a to 69d are determined by the self-extinguishing type semiconductor elements 52a, 52f, 52g,
Any position can be used as long as the current flowing through 52 m can be equivalently detected, and there is no particular limitation.

As described above, according to the tenth embodiment, the anodes of the clamp diodes 66a to 66d are connected to the cathodes of the snubber diodes 54a, 54f, 54g, 54m, respectively, and the discharge resistor 6 of the voltage clamp circuit is connected.
8a to 68d are connected to snubber resistors 56a and 56 of the snubber circuit.
Since the snubber resistors 56a, 56f, 56g, and 56m are omitted because they are also used as f, 56g, and 56m, the number of parts is reduced, and the size and cost of the inverter device can be reduced. Can be

Embodiment 11 FIG. In the inverter devices according to the third to tenth embodiments described above, power loss occurs in the voltage clamp circuit and the discharge resistors 18a, 18b, 68a to 68d of the second and third voltage clamp circuits. In the inverter device according to the eleventh aspect, a circuit for regenerating power is provided instead of the discharge resistor to reduce power loss.

FIG. 16 is a circuit diagram showing an example of a power regeneration circuit provided in a two-level inverter bridge instead of a discharge resistor according to the eleventh embodiment of the present invention. FIG.
FIG. 26 is a circuit diagram showing an example of a power regeneration circuit provided in a three-level inverter bridge instead of a discharge resistor according to Embodiment 11 of the present invention.

In the figure, reference numerals 87, 87a and 87b denote recovery capacitors for temporarily storing surplus electric charges generated at the time of voltage clamping, and reference numerals 88, 88a and 88b denote surplus electric charges generated at the time of voltage clamping.
7a and 87b are recovery diodes which conduct to the recovery capacitors 87, 89a and 89b, respectively.
The electric charges accumulated in 87a and 87b are transferred to DC voltage circuits 1 and 5
This is a power regeneration circuit that regenerates power to one.

The other components in FIG. 16 are the same as those in the third embodiment (FIG. 4), and the other components in FIG. 17 are the same as those in the seventh embodiment (FIG. 10). Therefore, their description is omitted.

Next, the operation will be described. The recovery diodes 88, 88a, and 88b conduct excess charges generated during voltage clamping to the recovery capacitors 87, 87a, and 87b, respectively, and the recovery capacitors 87, 87a, and 87b store the charges. The power regeneration circuits 89, 89a,
Reference numeral 89b regenerates the electric charges stored in the recovery capacitors 87, 87a, 87b to the DC voltage circuits 1, 51. As a result, the surplus charge at the time of voltage clamping is reused.

The other operations are the same as those in the third and seventh embodiments, respectively, and the description thereof is omitted.

The apparatus shown in FIG. 16 is similar to that of the third embodiment.
Although the power regeneration circuit is provided in the device according to the present invention, it is also possible to similarly provide the power regeneration circuit in the devices according to the fourth to sixth embodiments. Although the device of FIG. 17 is provided with a power regeneration circuit in the device of the seventh embodiment, the devices of the eighth to tenth embodiments are similarly provided.
It is also possible to provide a power regeneration circuit in the device according to the above.

As described above, according to the eleventh embodiment, since a circuit for regenerating power is provided instead of the discharge resistor of the voltage clamp circuit, the effect that power loss can be reduced can be obtained. Can be

For example, in the device shown in FIG. 4, the current detection circuit 9a is inserted on the cathode side of the self-extinguishing type semiconductor element 2a, but there is no problem if it is inserted on the anode side.

Further, instead of directly detecting the current flowing through the self-extinguishing type semiconductor element 2a, the current may be obtained by calculation from the current flowing through the self-extinguishing type semiconductor element 2c and the load current.

Further, in the apparatus shown in FIG.
8a is also used as a snubber resistor,
For example, the snubber resistor may be omitted as shown in FIG. In this case, an auxiliary clamp diode 91a is used.

Note that the present invention is not limited to the devices and the like described in the above embodiments, and various modifications and variations can be made to the devices according to the embodiments.

[0218]

As described above, according to the present invention, the first closed circuit returning from the DC voltage circuit to the DC voltage circuit via the inverter bridge, and the original circuit from the inverter bridge via the load circuit and another inverter bridge. A self-extinguishing semiconductor element for interrupting, which is inserted for each inverter bridge in the second closed circuit returning to the inverter bridge for each inverter bridge and interrupts abnormal current, and is connected in anti-parallel to the self-extinguishing semiconductor element for interrupting And a gate control circuit for turning off the self-extinguishing semiconductor element for shut-off when the current conducted to the self-extinguishing semiconductor element for interrupting becomes equal to or more than a predetermined threshold value. In the event that an abnormality occurs in the inverter bridge for some reason and an overcurrent occurs, the overcurrent is cut off and removed. That there is an effect that it is. Eventually, the self-extinguishing type semiconductor element connected to the common path of the short-circuit path and the return path cuts off the abnormal current, thereby suppressing the occurrence of accidental accidents and improving the reliability of the inverter device. There is an effect that can be.

According to the present invention, since the current change rate suppressing circuit for suppressing the rise of the voltage across the self-extinguishing type semiconductor element for cutoff is provided, the turn-off loss generated at the time of abnormal current cutoff is reduced. There is an effect that the cutoff limit is increased, the reliability of the abnormal current cutoff operation is improved, and the reliability of the inverter device can be improved.

According to the present invention, the first and second self-extinguishing semiconductor devices, which are connected in series with each other and are inverter-driven in accordance with a predetermined switching signal, and the first and second self-extinguishing semiconductor devices First and second freewheeling diodes connected in anti-parallel to each other, and first and second gate driving circuits for supplying and driving gate signals to the first and second self-extinguishing semiconductor elements, respectively. Are connected in series to the first and second self-extinguishing semiconductor elements and are connected in anti-parallel to the shut-off self-extinguishing semiconductor element for interrupting the abnormal current, and to the interrupting self-extinguishing semiconductor element. A free-wheeling diode for cut-off, a current change rate suppression circuit for suppressing a rise in voltage across the self-turn-off semiconductor device for cut-off, and a gate signal supplied to the self-turn-off semiconductor device for cut-off. A third gate driving circuit,
A gate control circuit for controlling a third gate drive circuit to turn off the self-extinguishing semiconductor device for shut-off when the current conducted to the self-extinguishing semiconductor device for shutting-off becomes equal to or more than a predetermined threshold value; Since it is provided for each two-level inverter bridge, the abnormal current is cut off by turning off the first and second self-turn-off semiconductor elements by the turning-off self-turn-off semiconductor element regardless of the switching state of the first and second self-turn-off semiconductor elements.
There is an effect that it is possible to suppress the occurrence of an unexpected accident and improve the reliability of the inverter device.

According to the present invention, the shut-off self-extinguishing semiconductor element is turned on in synchronization with the timing at which the first and second self-extinguishing semiconductor elements are turned on. The arc-extinguishing type semiconductor element can be reliably turned on, the element damage due to partial current concentration on the semiconductor wafer can be suppressed, and the reliability of the inverter device can be improved. There is.

According to the present invention, the predetermined threshold value is set to the period from the turn-on timing of the first self-turn-off semiconductor device to the turn-on timing of the second self-turn-off semiconductor device, And the threshold change circuit that changes each value to a predetermined value during the period of time, an abnormal current can be detected and cut off at a high speed according to the switching state at that time, and the reliability of the inverter device is improved. There is an effect that it can be improved.

According to the present invention, since the voltage clamping circuit for clamping the voltage applied to the first and second self-extinguishing semiconductor elements at the time of off-driving to a predetermined voltage or less is provided. Voltages at the time of off-drive of the first and second self-extinguishing semiconductor elements are suppressed, so that power loss in the two-level inverter bridge can be reduced, and the inverter device can be reduced in loss. .

According to the present invention, the voltage clamp for clamping the voltage applied to the first and second self-arc-extinguishing semiconductor elements and the self-extinguishing semiconductor element for shut-off to a predetermined voltage or less during off-driving is provided. Since the first and second self-extinguishing semiconductor elements are configured to have a circuit, the voltage at the time of off-drive of the first and second self-extinguishing semiconductor elements can be suppressed, the power loss in the two-level inverter bridge can be reduced, and It is possible to reduce the loss and reduce the capacitance of the snubber capacitor connected to the self-extinguishing type semiconductor element for shutting off, thereby reducing the size of the inverter device.

According to the present invention, the second gate control for maintaining the switching state of the first and second self-extinguishing semiconductor elements when the self-extinguishing semiconductor element for shutting off is turned off for a predetermined period of time. Since the circuit is provided, the first and second self-extinguishing type semiconductor elements can be prevented from being erroneously interrupted and damaged by an accident current, thereby improving the reliability of the inverter device. is there.

According to the present invention, the first and second self-extinguishing type semiconductor elements are provided with the voltage rise rate suppressing circuit for suppressing the change in the current conducted to the self-extinguishing type semiconductor element for interruption. Thus, the increase rate of the ON current flowing at the time of turn-on can be suppressed, the current detection delay at the time of detection of an abnormal current is compensated, and the reliability of the inverter device can be improved.

According to the present invention, the third to sixth self-extinguishing semiconductor elements which are connected in series with each other and driven by an inverter according to a predetermined switching signal, and the third to sixth self-extinguishing semiconductor elements which are respectively connected in anti-parallel to each other A sixth freewheeling diode, third to sixth gate drive circuits for supplying and driving gate signals to the third to sixth self-turn-off semiconductor elements, and a third self-turn-off semiconductor element A first coupling diode connected between a connection point between the first self-extinguishing semiconductor device and a neutral point of the DC voltage circuit, a fifth self-extinguishing semiconductor device and a sixth self-extinguishing semiconductor device. A second terminal connected between a connection point with the arc-extinguishing type semiconductor element and a neutral point of the DC voltage circuit;
A first switching self-extinguishing semiconductor element connected in series to the third and fourth self-extinguishing semiconductor elements for interrupting an abnormal current; A first blocking freewheel diode connected in anti-parallel to the semiconductor element, a first voltage rise rate suppressing circuit for suppressing a rise in voltage across the first self-turn-off semiconductor element for blocking, A second self-extinguishing semiconductor element for interrupting, which is connected in series to the fifth and sixth self-extinguishing semiconductor elements and interrupts abnormal current; and an anti-parallel to the second self-extinguishing semiconductor element for interrupting. A second cut-off freewheel diode connected thereto, a second voltage rise rate suppressing circuit for suppressing a rise in voltage across the second cut-off self-extinguishing semiconductor device,
A seventh and an eighth gate drive circuit for supplying a gate signal to each of the first and second self-extinguishing semiconductor devices for shutting off to drive the semiconductor device; If the threshold value is equal to or greater than the first threshold value,
A third gate control circuit for controlling the first gate drive circuit to turn off the first shut-off self-extinguishing semiconductor device;
An eighth gate drive circuit is controlled when the current conducted to the second shut-off self-arc-extinguishing semiconductor element becomes equal to or more than a predetermined second threshold value, and the second shut-off self-arc-extinguishing semiconductor is controlled. Since a fourth gate control circuit for turning off the element is provided for each three-level inverter bridge, the third and sixth self-turn-off semiconductor elements for interrupting are provided by the first and second shut-off self-extinguishing semiconductor elements.
The self-extinguishing type semiconductor device is turned off regardless of the switching state and the abnormal current is interrupted, so that the abnormal current can be interrupted without damaging the self-extinguishing type semiconductor device, and the accidental spread of accidents Thus, there is an effect that the reliability of the inverter device can be improved.

According to the present invention, the first shut-off self-extinguishing type semiconductor element is turned on in synchronization with the timing at which the third and fifth self-extinguishing type semiconductor elements are turned on. Is configured to turn on the second self-extinguishing semiconductor element for shut-off in synchronization with the timing at which each of the self-extinguishing semiconductor elements of (1) and (2) is turned on. Can be reliably turned on, the occurrence of element damage due to partial current concentration on the semiconductor wafer can be suppressed, and the reliability of the inverter device can be improved.

According to the present invention, the predetermined first threshold value is set to the period from the turn-on timing of the third self-turn-off semiconductor device to the turn-on timing of the fifth self-turn-off semiconductor device. A first threshold value changing circuit for changing to a predetermined value in each of the other periods, and a predetermined second threshold value, which is changed from the turn-on timing of the fourth self-arc-extinguishing type semiconductor device to the sixth value. And a second threshold value changing circuit for changing to a predetermined value in each of the period up to the turn-on timing of the self-extinguishing type semiconductor element and the other period. Accordingly, an abnormal current can be detected and cut off at a high speed in accordance with the above, and there is an effect that the reliability of the inverter device can be improved.

According to the present invention, the second voltage clamp circuit for clamping the voltage applied to the third and fifth self-extinguishing semiconductor elements at the time of off driving to a predetermined voltage or less, A third voltage clamping circuit for clamping the voltage applied to the sixth self-extinguishing type semiconductor element at the time of off driving to a predetermined voltage or less, so that the third and fifth self-extinguishing arcs are provided. The voltage at the time of off-drive of the semiconductor element and the voltage at the time of off-drive of the fourth and sixth self-extinguishing semiconductor elements can be suppressed, and the power loss in the three-level inverter bridge can be reduced. There is an effect that the loss can be reduced.

According to the present invention, the voltage applied to the third and fifth self-arc-extinguishing semiconductor elements and the first shut-off self-arc-extinguishing semiconductor element during off driving is clamped to a predetermined voltage or less. And a second voltage clamping circuit for clamping the voltage applied to the fourth and sixth self-extinguishing semiconductor devices and the second self-extinguishing semiconductor device for shutting off to a predetermined voltage or less during off driving. And a third voltage clamp circuit that performs the off-driving of the third and fifth self-turn-off semiconductor devices and the off-drive of the fourth and sixth self-turn-off semiconductor devices. Voltage at the time of power supply can be suppressed, power loss in the three-level inverter bridge can be reduced, the inverter device can be reduced in loss, and the first and second self-extinguishing semiconductor elements for shutting off can be connected. Is the possible to reduce the capacitance of the snubber capacitor, there is an effect that an inverter apparatus can be miniaturized.

According to the present invention, the switching state of the third to sixth self-extinguishing semiconductor elements when one of the first and second shut-off self-extinguishing semiconductor elements is turned off for a predetermined period. , The third to sixth self-extinguishing type semiconductor elements are prevented from being erroneously interrupted by an accident current and damaged, and the reliability of the inverter device is reduced. There is an effect that the performance can be improved.

According to the present invention, the first current change rate suppressing circuit for suppressing a change in the current conducted to the first self-extinguishing semiconductor device for interruption, and the second self-extinguishing semiconductor device for interrupting And a second current change rate suppression circuit for suppressing a change in current conducted to the third self-extinguishing type semiconductor element. Therefore, the current detection delay at the time of detection of an abnormal current is compensated, and the reliability of the inverter device can be improved.

According to the present invention, the first to sixth self-extinguishing semiconductor devices, the shut-off self-extinguishing semiconductor device, and the first
In addition, since the gate commutation type turn-off thyristor is used for the second self-extinguishing semiconductor device for shutoff, there is an effect that a large-capacity inverter bridge can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an inverter device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing an example of a gate drive circuit of the self-extinguishing semiconductor device in FIG. 1 and peripheral circuits thereof.

FIG. 3 is a circuit diagram showing a configuration of an inverter device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of an inverter device according to Embodiment 3 of the present invention.

5 is a diagram showing an example of a gate drive circuit of the self-extinguishing type semiconductor device in FIG. 4 and peripheral circuits thereof.

FIG. 6 is a timing chart for explaining the operation of the inverter device shown in FIGS. 4 and 5;

FIG. 7 is a circuit diagram showing a configuration of an inverter device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of an inverter device according to a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of an inverter device according to Embodiment 6 of the present invention.

FIG. 10 is a circuit diagram showing a configuration of an inverter device according to a seventh embodiment of the present invention.

11 is a diagram showing an example of a gate drive circuit of the self-extinguishing type semiconductor element in FIG. 10 and its peripheral circuits.

FIG. 12 is a timing chart illustrating the operation of the inverter device shown in FIGS. 10 and 11;

FIG. 13 is a circuit diagram showing a configuration of an inverter device according to an eighth embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of an inverter device according to Embodiment 9 of the present invention.

FIG. 15 is a circuit diagram showing a configuration of an inverter device according to a tenth embodiment of the present invention.

FIG. 16 is a circuit diagram showing an example of a power regeneration circuit provided in a two-level inverter bridge instead of a discharge resistor according to Embodiment 11 of the present invention.

FIG. 17 is a circuit diagram showing an example of a power regeneration circuit provided in a three-level inverter bridge instead of a discharge resistor according to Embodiment 11 of the present invention.

FIG. 18 is a circuit diagram showing a modification of the inverter device of FIG. 9;

FIG. 19 is a circuit diagram showing a configuration of a conventional inverter device.

FIG. 20 is a diagram showing a problem with a conventional inverter device.

FIG. 21 is a diagram showing a problem with a conventional inverter device.

[Explanation of symbols]

1,51 DC voltage circuit, 2a, 2d Self-extinguishing type semiconductor element (self-extinguishing type semiconductor element for cutoff), 2b, 2e
Self-extinguishing type semiconductor element (first self-extinguishing type semiconductor element), 2c, 2f Self-extinguishing type semiconductor element (second self-extinguishing type semiconductor element), 3a, 3d Freewheel diode (freewheel for breaking) Diode), 3b, 3
e Freewheel diode (first freewheel diode), 3c, 3f Freewheel diode (second freewheel diode), 4a, 4d Snubber diode (voltage rise rate suppression circuit), 5a, 5d
Snubber capacitor (voltage rise rate suppression circuit), 6a, 6d
Snubber resistance (voltage rise rate suppression circuit), 10, 60 load circuit, 15a, 26a Gate control circuit, 16a, 1
6b Clamp diode (voltage clamp circuit), 17
a, 17b Clamp capacitor (voltage clamp circuit), 18a, 18b Discharge resistor (voltage clamp circuit), 19a, 19b Current change rate suppression circuit, 21a
Threshold selection circuit (threshold change circuit), 23a Gate drive circuit (third gate drive circuit), 23b Gate drive circuit (first gate drive circuit), 23c Gate drive circuit (second gate drive circuit) ), 24a switching signal holding circuit (second gate control circuit), 52a, 5
2g Self-extinguishing semiconductor device (first self-extinguishing semiconductor device for interrupting), 52b, 52h Self-extinguishing semiconductor device (third self-extinguishing semiconductor device), 52c, 52i Self-extinguishing semiconductor Device (fourth self-extinguishing semiconductor device),
52d, 52j Self-extinguishing type semiconductor element (fifth self-extinguishing type semiconductor element), 52e, 52k Self-extinguishing type semiconductor element (sixth self-extinguishing type semiconductor element), 52f, 52m
Self-arc-extinguishing type semiconductor element (second shut-off self-extinguishing type semiconductor element), 53a, 53g Freewheel diode (first interrupting freewheel diode), 53b,
53h freewheel diode (third freewheel diode), 53c, 53i freewheel diode (fourth freewheel diode), 53
d, 53j freewheel diode (fifth freewheel diode), 53e, 53k freewheel diode (sixth freewheel diode), 5
3f, 53m freewheel diode (second blocking freewheel diode), 54a, 54g snubber diode (first voltage rise rate suppression circuit), 54f,
54m snubber diode (second voltage rise rate suppression circuit), 55a, 55g snubber capacitor (first voltage rise rate suppression circuit), 55f, 55m snubber capacitor (second voltage rise rate suppression circuit), 56a, 56g snubber Resistance (first voltage rise rate suppression circuit), 56f, 56m
Snubber resistance (second voltage rise rate suppression circuit), 65a Gate control circuit (third gate control circuit), 65b Gate control circuit (fourth gate control circuit), 66a, 66c
Clamp diode (second voltage clamp circuit), 6
6b, 66d Clamp diode (third voltage clamp circuit), 67a, 67c Clamp capacitor (second
Voltage clamp circuit), 67b, 67d Clamp capacitors (third voltage clamp circuit), 68a, 68c
Discharge resistance (second voltage clamp circuit), 68b, 68d
Discharge resistance (third voltage clamp circuit), 69a, 69
c current change rate suppression circuit (first current change rate suppression circuit), 69b, 69d current change rate suppression circuit (second current change rate suppression circuit), 71a threshold value selection circuit (first
Threshold change circuit), 71b threshold select circuit (second threshold change circuit), 73a gate drive circuit (seventh gate drive circuit), 73b gate drive circuit (third change circuit)
Gate drive circuit (fourth gate drive circuit), 73d gate drive circuit (fifth gate drive circuit), 73e gate drive circuit (sixth gate drive circuit), 73f gate drive circuit ( Eighth gate drive circuit), 74a Switching signal holding circuit (fifth
Gate control circuit), 76a, 76c coupling diode (first coupling diode), 76b, 76d coupling diode (second coupling diode).

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroaki Yamaguchi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5H007 AA06 AA17 CA05 CB04 CB05 CC04 CC23 DA05 DB01 DC02 EA02 FA03 FA08 FA13 FA19 FA20 GA08

Claims (17)

[Claims] 1. A semiconductor device comprising: a plurality of self-extinguishing type semiconductor elements; and a freewheel diode connected in anti-parallel to the plurality of self-extinguishing type semiconductor elements. An inverter device for supplying power to a load circuit, the first closed circuit returning from the DC voltage circuit to the DC voltage circuit via the inverter bridge, and the load circuit and another inverter bridge from the inverter bridge. A self-extinguishing semiconductor element for interrupting, which is inserted for each inverter bridge and interrupts an abnormal current, in a common path in a second closed circuit returning to the original inverter bridge via A blocking freewheel diode connected in antiparallel to the semiconductor element; and a self-turn-off semiconductor element for blocking. An inverter device, comprising: a gate control circuit that turns off the self-extinguishing semiconductor element for shutting off when a current flowing through the semiconductor element exceeds a predetermined threshold value. 2. The inverter device according to claim 1, further comprising a voltage rise rate suppression circuit that suppresses a rise in voltage across both ends of the self-extinguishing type semiconductor element for cutoff. 3. A two-level inverter bridge having a plurality of self-arc-extinguishing semiconductor elements and a freewheel diode connected in anti-parallel to the plurality of self-arc-extinguishing semiconductor elements and connected to a DC voltage circuit. An inverter device that is provided with a predetermined number and supplies power to a load circuit; a first and a second self-extinguishing type semiconductor element that are connected in series with each other and are inverter-driven according to a predetermined switching signal; A first and a second freewheeling diode connected in anti-parallel to the second self-turn-off semiconductor element, and a gate signal supplied to each of the first and second self-turn-off semiconductor elements for driving First and second gate drive circuits, which are connected in series with the first and second self-extinguishing semiconductor elements, and a shutoff circuit for shutting off an abnormal current. An arc-extinguishing type semiconductor element; a blocking freewheel diode connected in anti-parallel to the blocking self-extinguishing type semiconductor element; and a voltage rise that suppresses a rise in voltage across the blocking self-extinguishing type semiconductor element. Rate suppressing circuit; a third gate drive circuit that supplies a gate signal to the self-extinguishing semiconductor element for interrupting to drive the semiconductor element; An inverter device comprising, for each of the two-level inverter bridges, a gate control circuit for controlling the third gate drive circuit to turn off the self-turn-off semiconductor element for shutting down in the case described above. 4. The semiconductor device according to claim 3, wherein the gate control circuit turns on the shut-off self-extinguishing semiconductor device in synchronization with a timing at which the first and second self-extinguishing semiconductor devices are turned on. The inverter device as described. 5. A method according to claim 1, wherein the predetermined threshold value is a period from a turn-on timing of the first self-turn-off semiconductor device to a turn-on timing of the second self-turn-off semiconductor device.
5. The inverter device according to claim 3, further comprising a threshold value changing circuit for changing the threshold value to a predetermined value during other periods. 6. The semiconductor device according to claim 3, further comprising a voltage clamp circuit for clamping a voltage applied to the first and second self-extinguishing type semiconductor elements during off driving to a predetermined voltage or less. Item 6. The inverter device according to any one of Items 5. 7. A voltage clamp circuit for clamping a voltage applied to the first and second self-arc-extinguishing semiconductor elements and the shut-off self-extinguishing semiconductor element during off-drive to a predetermined voltage or less. The inverter device according to any one of claims 3 to 5, wherein: 8. A semiconductor device comprising a second gate control circuit for maintaining a switching state of the first and second self-arc-extinguishing semiconductor devices when the self-extinguishing semiconductor device for shut-off is turned off for a predetermined period. Claim 3 characterized by the following:
The inverter device according to any one of claims 1 to 7. 9. The semiconductor device according to claim 3, further comprising a current change rate suppression circuit for suppressing a change in a current flowing through the self-extinguishing type semiconductor element for interruption.
The inverter device according to the item. 10. A three-level inverter bridge having a plurality of self-arc-extinguishing semiconductor elements and a freewheel diode connected in anti-parallel to the plurality of self-arc-extinguishing semiconductor elements and connected to a DC voltage circuit. An inverter device that is provided with a predetermined number and supplies power to a load circuit; a third to a sixth self-extinguishing type semiconductor elements that are connected in series with each other and are inverter-driven according to a predetermined switching signal; A third to a sixth freewheeling diode connected in anti-parallel to the sixth self-turn-off semiconductor element, and a gate signal supplied to the third to sixth self-turn-off semiconductor element for driving A third to a sixth gate drive circuit, between a connection point between the third self-extinguishing type semiconductor element and the fourth self-extinguishing type semiconductor element and a neutral point of the DC voltage circuit. A first coupling diode connected to the fifth self-extinguishing semiconductor device and a sixth self-extinguishing semiconductor device and a neutral point of the DC voltage circuit. A second coupling diode, a first self-extinguishing semiconductor device for interrupting, which is connected in series to the third and fourth self-extinguishing semiconductor devices, and interrupts an abnormal current; A first blocking freewheel diode connected in anti-parallel to the self-turn-off semiconductor element, and a first voltage rising rate for suppressing a rise in voltage across the first blocking self-turn-off semiconductor element A suppression circuit, a second self-extinguishing semiconductor device for interrupting, which is connected in series to the fifth and sixth self-extinguishing semiconductor devices, and interrupts an abnormal current; Blocking freewheel connected in anti-parallel to the semiconductor device A diode; a second voltage rise rate suppression circuit for suppressing a rise in voltage across the second self-extinguishing semiconductor element for interruption; and a first and second self-extinguishing semiconductor element for interruption. A seventh and an eighth gate drive circuit for respectively supplying and driving a gate signal; and a case where a current conducted to the first shut-off self-turn-off semiconductor element becomes equal to or more than a predetermined first threshold value. A third gate control circuit for controlling the seventh gate drive circuit to turn off the first shut-off self-extinguishing semiconductor device; and conducting to the second shut-off self-extinguishing semiconductor device. And a fourth gate control circuit for controlling the eighth gate drive circuit to turn off the second shut-off self-extinguishing type semiconductor element when the current exceeds a predetermined second threshold value. Provided for each of the three-level inverter bridges An inverter device characterized by the following. 11. The third gate control circuit turns on the first shut-off self-extinguishing semiconductor device in synchronization with the timing at which the third and fifth self-extinguishing semiconductor devices turn on, respectively. 11. The gate control circuit according to claim 4, wherein the second shut-off self-extinguishing semiconductor element is turned on in synchronization with a timing at which the fourth and sixth self-extinguishing semiconductor elements are turned on.
3. The inverter device according to claim 1. 12. The method according to claim 11, wherein the predetermined first threshold value is a period between a turn-on timing of the third self-turn-off semiconductor device and a turn-on timing of the fifth self-turn-off semiconductor device, and A first threshold value changing circuit for changing to a predetermined value in each of the periods, and a sixth self-extinguishing method for changing the predetermined second threshold value from the turn-on timing of the fourth self-extinguishing type semiconductor element. 12. The semiconductor device according to claim 10, further comprising a second threshold value changing circuit that changes a value to a predetermined value during a period until the turn-on timing of the type semiconductor element and during the other periods. Inverter device. 13. A second voltage clamp circuit for clamping a voltage applied to a third and a fifth self-extinguishing type semiconductor element at the time of off driving to a predetermined voltage or less, and a fourth and a sixth self-extinguishing semiconductor element. 11. The semiconductor device according to claim 10, further comprising: a third voltage clamp circuit that clamps a voltage applied to the arc-extinguishing type semiconductor element at the time of off driving to a predetermined voltage or less.
The inverter device according to any one of claims 1 to 12. 14. A second clamper for clamping a voltage applied to the third and fifth self-extinguishing semiconductor devices and the first shut-off self-extinguishing semiconductor device during off driving to a predetermined voltage or less. A voltage clamping circuit, and a third circuit for clamping a voltage applied to the fourth and sixth self-extinguishing semiconductor devices and the second self-extinguishing semiconductor device for shut-off to a predetermined voltage or less during off driving. The inverter device according to any one of claims 10 to 12, further comprising a voltage clamp circuit. 15. A third to sixth semiconductor device when one of the first and second self-turn-off semiconductor devices for shut-off is turned off.
The inverter device according to any one of claims 10 to 14, further comprising a fifth gate control circuit that keeps a switching state of the self-extinguishing type semiconductor element as it is for a predetermined period. 16. A first current change rate suppressing circuit for suppressing a change in a current conducted to a first interrupting self-extinguishing semiconductor device, and a current conducting to a second interrupting self-extinguishing semiconductor device. The inverter device according to any one of claims 10 to 15, further comprising: a second current change rate suppression circuit that suppresses a change in the current. 17. A first to sixth self-extinguishing type semiconductor device,
17. The semiconductor device according to claim 3, wherein the self-extinguishing semiconductor device for interrupting and the first and second self-extinguishing semiconductor devices for interrupting are gate commutation type turn-off thyristors. 2. The inverter device according to claim 1.