JP2000294625A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress the occurrence of crystal defect in a semiconductor substrate even if heat treatment is conducted after a groove for isolating elements is formed in the semiconductor substrate and which can obtain a high reliability. SOLUTION: In a semiconductor substrate in which an Si substrate l with elements isolated by the STI method is used, in the case where it is provided with a part in which active areas cross each other at 90 deg. or less, the active area 4 adjacent to the crossing part is bent at 90 deg. or more. In addition, the crossing part in the active area 4 is removed, and the active areas 4 on both ends of the removed part may be connected with each other by an upper-layer wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a highly integrated semiconductor device in which element isolation in a semiconductor substrate is performed by a trench element isolation method.

[0002]

2. Description of the Related Art As an element isolation technique for a silicon (Si) substrate, conventionally, an oxidation resistant mask is selectively formed on a Si substrate, and then, an element isolation region is selectively formed by performing thermal oxidation. LOCOS (Local Oxi
dation of Silicon) method is known.

However, in this LOCOS method, S
When the i-substrate is thermally oxidized, the oxidation reaction spreads in the lateral direction,
Because of the so-called bird's beak, the growth of the field insulating film in the lateral direction exists, the semiconductor device can be miniaturized,
As the degree of integration increases, it becomes difficult to secure an active region.

Therefore, as a new element isolation technique to cope with this problem, a trench element isolation (Shallow Trench Isolation) has been proposed.
lation, hereinafter referred to as STI) method. S
In the TI method, as shown in FIGS.
1. A groove 102 is formed in a region where element isolation is to be performed, and a field insulating film 103 is formed by embedding an insulating film such as silicon dioxide (SiO ₂ ) in the groove 102, thereby forming an element isolation region. Technology.

A method for separating an element from a Si substrate by the STI method will be specifically described. First, as shown in FIG. 10A, one main surface of a Si substrate 101 is formed by thermal oxidation.
A pad oxide film 111 made of O ₂ is formed. Next, a silicon nitride (Si ₃ N ₄ ) film 112 is formed on the pad oxide film 111 by a low pressure chemical vapor deposition (LPCVD) method.

Next, as shown in FIG. 10B, a resist pattern 113 having an opening at a portion corresponding to an element isolation region is formed on the Si ₃ N ₄ film 112 by lithography.
Is formed, the Si ₃ N ₄ film 112 and the pad oxide film 111 are etched by dry etching using the resist pattern 113 as a mask. As a result, an opening 112a is formed in the Si ₃ N ₄ film 112 and the pad oxide film 111 in a portion corresponding to the element isolation region. After that, the resist pattern 113 used as the etching mask is removed.

Next, as shown in FIG. 10C, Si ₃ N ₄
Using the film 112 and the pad oxide film 111 as a mask, the Si substrate 101 is etched to a predetermined depth by a dry etching method. As a result, a groove 102 is formed in a portion of the Si substrate 101 corresponding to the element isolation region.

Next, an SiO ₂ film (thermal oxide film) is formed on the inner wall of the groove 102 by a thermal oxidation method. Due to the formation of the thermal oxide film, the corners (trench corners) of the trench 102 are rounded, and the concentration of the electric field on this corner can be reduced. Next, as shown in FIG.
By a method D, an SiO ₂ film 114 is formed on the entire surface so as to fill the groove 102 and the opening 112a. next,
By heat treatment under a predetermined condition in an atmosphere containing atmosphere or a nitrogen containing oxygen of the SiO ₂ film 114, to densify the SiO ₂ film 114. Next, as shown in FIG. 11B, S is formed only inside the groove 102 and the opening 112a.
The SiO ₂ film 114 existing on the Si ₃ N ₄ film 112 is polished and removed by a chemical mechanical polishing (CMP) method so as to leave the iO ₂ film 114.

Next, the Si ₃ N ₄ film 112 is removed by a wet etching method using hot phosphoric acid. next,
The pad oxide film 111 is removed by a wet etching method using hydrofluoric acid. As a result, as shown in FIG. 11C, an element isolation region having a structure in which the field insulating film 103 made of SiO ₂ is embedded inside the groove 102 is formed. Reference numeral 104 denotes an active region surrounded by the field insulating film 103.

According to the above-mentioned STI method, the Si substrate 10
Since the field insulating film 103 is formed by burying the SiO ₂ film 114 in the groove 102 formed in the first step, a bird's beak does not occur in the field insulating film unlike the LOCOS method. After the SiO ₂ film 114 is deposited so as to fill the inside of the groove 102, the surface is flattened by the CMP method. Therefore, there is an advantage that the surface flatness required for high precision lithography can be secured. Can be

[0011]

However, according to the knowledge of the present inventor, according to the knowledge of the present inventor, the Si substrate 10 is formed by the STI method described above.
In the case where the element isolation is performed, when the SiO ₂ film is formed on the inner wall of the groove 102 by the thermal oxidation method, the Si substrate 1
It has been confirmed that a crystal defect occurs locally at No. 01. This crystal defect is likely to occur when the SiO ₂ film is oxidized at a temperature of about 900 ° C. or less, at which the SiO ₂ film does not have viscous fluidity, and tends to occur as the thickness of the SiO ₂ film increases. Also, when heat treatment is performed after the SiO ₂ film 114 is buried in the groove 102, crystal defects locally occur in the Si substrate 101, particularly when this heat treatment is performed in an oxidizing gas atmosphere. Easy to do. When such a crystal defect exists in the Si substrate 101, metal contaminants gather at the defective portion, causing an increase in leak current, and a problem that reliability of the completed semiconductor device is reduced. Therefore, the advantage of forming the thermal oxide film on the inner wall of the groove 102 is lost.

This problem will be specifically described with reference to the drawings. That is, FIG. 12 is a plan view of a conventional semiconductor device in which the element isolation of the Si substrate is performed by the STI method. Here, FIG. 12A shows the vicinity of a bent portion (right-angle bent portion) of the active region obtained by bending the active region 104 at a right angle,
FIG. 12B and FIG. 12C show the vicinity of the intersection (right-angle intersection) of the active regions in which the active regions 104 intersect at right angles. According to the findings of the present inventor, it has been confirmed that the above-described crystal defects are particularly likely to occur in the Si substrate 101 in the vicinity of a right-angle bent portion or a right-angle intersection of an active region as shown in FIGS. 12A to 12C. ing. 12A to 12C are regions where the active regions 104 intersect at an angle of 90 ° with each other, and the angle of the trench corner around the intersection is 90 °. Therefore, it is considered that stress is concentrated on that portion during the heat treatment, so that crystal defects are likely to occur.

The above-mentioned crystal defects are not limited to the thermal oxidation step for forming a thermal oxide film on the inner wall of the trench 102 and the heat treatment step after the formation of the SiO ₂ film 114 serving as a filling material.
This is a problem that can also occur when heat treatment is performed after forming the groove 102 in the substrate 101. According to the findings of the present inventor, it has been confirmed that similar crystal defects occur in the Si substrate 101 even during the heat treatment step performed to activate the impurities introduced into the Si substrate 101.

Therefore, an object of the present invention is to suppress generation of crystal defects in a semiconductor substrate even if heat treatment is performed after forming a groove for element isolation in a semiconductor substrate, and high reliability can be achieved. To provide a semiconductor device capable of obtaining the above.

[0015]

In order to achieve the above object, a first aspect of the present invention is directed to a structure in which a groove for element isolation is provided on one main surface, and an insulating film is buried inside the groove. In a semiconductor device using a semiconductor substrate having an element isolation region and having an active region in a portion surrounded by the element isolation region, if the active regions have portions that intersect at an angle of 90 degrees or less, they intersect The active region near the portion is bent at an angle larger than 90 degrees.

According to the first aspect of the present invention, from the viewpoint of more effectively suppressing the occurrence of crystal defects in the semiconductor substrate, when the active regions have portions that cross each other at an angle of 90 degrees or less, The active region near the intersection is preferably bent at an angle of 100 degrees or more, more preferably at an angle of 135 degrees or more.

According to a second aspect of the present invention, there is provided an element isolation region having a structure in which an element isolation groove is provided on one principal surface, and an insulating film is embedded in the groove, and is surrounded by the element isolation region. In a semiconductor device using a semiconductor substrate having an active region in a portion where the active region has a portion intersecting with each other at an angle of 90 degrees or less, the intersecting portion of the active region is removed. The active regions at both ends are interconnected by wiring.

In the second aspect of the present invention, the wiring interconnecting the active regions is typically provided on the semiconductor substrate via an interlayer insulating film. When an upper layer wiring is provided on the interlayer insulating film, it is preferable that the wiring for connecting the active regions to each other be made of the same material as the upper layer wiring.

In the present invention, the semiconductor substrate includes:
Typically, a silicon substrate is used. In this case, the silicon substrate may be the silicon substrate itself, or may be a substrate such as a silicon substrate provided with a silicon film formed by epitaxial growth. In the present invention, when a silicon substrate is used as a semiconductor substrate, silicon oxide is typically used as a material of an insulating film embedded in the trench. In the present invention, when a silicon substrate is used as a semiconductor substrate, a trench for element isolation is typically formed by sequentially forming a silicon oxide film and a silicon nitride film on a silicon substrate, and forming a silicon nitride film and a silicon oxide film. Is patterned into a predetermined shape, and then formed by etching the silicon substrate using the silicon nitride film and the silicon oxide film as a mask.

In the present invention, a semiconductor device is typically manufactured through a heat treatment step after forming a groove in a semiconductor substrate. As such a heat treatment step, for example,
A heat treatment step performed to form an oxide film on the inner wall of the groove by thermally oxidizing the semiconductor substrate, and after forming an insulating film on the semiconductor substrate so as to fill the inside of the groove, to densify the insulating film. There are a heat treatment step performed, a heat treatment step performed to activate impurities introduced into the semiconductor substrate, and the like.

The first invention and the second invention of the present invention can be used in appropriate combinations.

According to the first aspect of the present invention configured as described above, when the active regions have portions that cross each other at an angle of 90 degrees or less, the active regions in the vicinity of the crossing portions are shifted by 90 degrees. By bending at a larger angle and cutting off the corners of the groove around the intersection, the stress applied to the vicinity of the intersection of the active region during the heat treatment after the formation of the groove is reduced compared to the conventional method. Can be. Therefore, even if the heat treatment is performed after the groove is formed in the semiconductor substrate, generation of crystal defects in the semiconductor substrate due to the heat treatment can be suppressed.

According to the second aspect of the present invention configured as described above, when the active regions have portions that cross each other at an angle of 90 degrees or less, the crossing portion of the active regions is removed. After the trenches are formed in the semiconductor substrate, the active regions at both ends of the removed portion are interconnected by wiring, and a portion where the active regions cross each other at an angle of 90 degrees or less is removed from the semiconductor substrate. Even if heat treatment is performed, generation of crystal defects in the semiconductor substrate due to the heat treatment can be suppressed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

First, a first embodiment of the present invention will be described. FIG. 1 is a plan view of the semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 1, in the semiconductor device according to the first embodiment, an element isolation groove 2 provided in a portion of an Si substrate 1 corresponding to an element isolation region has
For example, a field insulating film 3 made of SiO ₂ is buried, thereby performing element isolation. Symbol 4 is
4 shows an active region surrounded by a field insulating film 3.
Here, in the semiconductor device according to the first embodiment, when the active regions 4 have portions that intersect with each other at an angle of 90 ° or less, the active regions 4 near the intersections are formed at an angle larger than 90 °. It is characteristic of being bent.

For example, FIG. 1A shows a portion of the semiconductor device according to the first embodiment shown in FIG. 12A of the conventional semiconductor device, that is, a right-angle bent portion of the active region 104 in which the active region 104 is bent by 90 °. The vicinity of the corresponding part is shown.
In FIG. 1A, an active region 4a extending in a vertical direction and an active region 4b extending in a horizontal direction extend in directions perpendicular to each other, and the widths of the active regions 4a and 4b are, for example, 0. It is about several μm to several μm.

As shown in FIG. 1A, in the semiconductor device according to the first embodiment, the portion corresponding to the right-angled bent portion of the L-shaped active region is formed by extending the active region 4a extending in the vertical direction. Near the intersection of the line and the extension of the laterally extending active region 4b, the active region 4 is oriented at an angle greater than 90 °, preferably at an angle of 100 ° or more, more preferably 135 °. The active region 4a extending in the vertical direction and the active region 4b extending in the horizontal direction are connected by bending at two angles at the above angle. In the example shown in FIG. 1A, the active region 4 is bent at substantially equal angles in two stages. In this case, the bending angle of the active region 4 at each bending portion is 135 °. Comparing the semiconductor device according to the first embodiment with the conventional semiconductor device, in the conventional semiconductor device in which the active region 104 is bent by 90 ° as shown in FIG. 12A, the corner portion of the groove 102 around the bent portion is obtained. 1A, the corners of the active region 104 are at right angles, while the active region 4 is bent at an angle greater than 90 ° in two stages as shown in FIG. 1A. The semiconductor device has a structure in which the corner of the groove 2 around the bent portion and the corner of the active region 4 are cut (chamfered) in a tapered shape.

FIGS. 1B and 1C show the semiconductor device according to the first embodiment in which the portion shown in FIGS. 12B and 12C of the conventional semiconductor device, that is, the active region 104 is formed at an angle of 90 ° with respect to each other. The vicinity of a portion corresponding to a right-angle intersection of the crossed active regions is shown. 1B and 1C, the active region 4a extending in the vertical direction and the active region 4b extending in the horizontal direction extend in a direction perpendicular to each other, and the width of the active regions 4a and 4b is, for example, 0.1 mm. It is about several μm to several μm.

As shown in FIGS. 1B and 1C, in the semiconductor device according to the first embodiment, a portion corresponding to a right-angled intersection of the cross-shaped and T-shaped active regions extends in the vertical direction. In the vicinity of the intersection of the active region 4a and the laterally extending active region 4b, the active region 4
Of the edge at an angle greater than 90 °, preferably 100 °
At the above angle, more preferably at an angle of 135 ° or more, it is bent in two stages. In the example shown in FIGS. 1B and 1C, the edge of the active region 4 is bent at substantially equal angles in two stages. In this case, the bending angle of the edge of the active region 4 at each bending portion is 135 °. In the example shown in FIGS. 1B and 1C, when the edge of the active region 4 is bent, the edges on both sides are connected to the active regions 4a and 4b.
Are bent substantially symmetrically with respect to the center line of This first
When the semiconductor device according to the embodiment is compared with the conventional semiconductor device, in the conventional semiconductor device in which the edge of the active region 104 is bent by 90 ° as shown in FIGS. 12B and 12C, the corner of the groove 102 around the intersection is formed. In the semiconductor device according to the first embodiment, the active region 4 is bent at an angle larger than 90 ° in two stages as shown in FIGS. 1B and 1C, whereas the portion is a right angle. The corner portion of the groove 2 around the intersection is cut (chamfered) in a tapered shape.

Here, in the example shown in FIGS. 1A to 1C, the vicinity of a portion where the active region 4a and the active region 4b intersect,
Although the active region 4 or its edges are bent at substantially equal angles, this may mean that the active region 4 or its edges may be bent at different angles. In addition, in the example shown in FIGS. 1A to 1C, the active region 4 or the edge thereof is bent in almost two steps near the intersection of the active region 4 a and the active region 4 b. The active region 4 or its edge may be bent in three or more steps. At this time, by increasing the number of steps of bending of the active region 4 or the edge thereof, a radius may be formed at the corner of the groove 2 around the bent portion and the intersection. FIG.
In the example shown in FIG. 1B and FIG. 1C, when the edge of the active region 4 is bent, the edges on both sides are bent substantially symmetrically with respect to the center line of the active region 4, but this is not necessarily symmetric. No need.

Although not shown, in the semiconductor device according to the first embodiment, a portion corresponding to a portion where the active regions 104 cross each other at an angle smaller than 90 ° in the conventional semiconductor device also corresponds to the above-described portion. 1A to 1C, the active region 4 near the intersection is bent at an angle larger than 90 °.

Next, the detailed structure of the semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 2 is a cross-sectional view for explaining the structure of the semiconductor device according to the first embodiment.

As shown in FIGS. 1 and 2, in the semiconductor device according to the first embodiment, a trench 2 for element isolation is provided on one main surface of a Si substrate 1. The width of the groove 2 in one direction is, for example, about 0.25 μm for a narrow one and about several μm for a wide one, and the depth of the groove 2 is, for example, about 400 nm. Although not shown, the inner wall of the groove 2 is covered with a SiO ₂ film (thermal oxide film). Groove 2
The field insulating film 3 buried in the inside is densified by, for example, heat treatment. The width in one direction of the active region 4 surrounded by the field insulating film 3 is narrow, for example, 0.1 mm. About several μm, for example, a few μm wide
It is about.

Although not shown, in the Si substrate 1, for example, in a MOSFET formation region, a p-well is provided in the active region 4, and a gate insulating film made of SiO ₂ is provided on the active region 4 via a gate insulating film. For example, a gate electrode (lower layer wiring) made of polycrystalline Si is provided. A sidewall spacer made of, for example, SiO ₂ is provided on a side surface of the gate electrode. In the active region 4, a source region and a drain region composed of an n ⁺ type diffusion layer are provided in a self-aligned manner with respect to the gate electrode. Each of the source region and the drain region has an n ⁻ -type low impurity concentration portion in a portion below the sidewall spacer. The gate insulating film, the gate electrode, the n ⁺ -type source region and the n ⁺ -type drain region constitute an n-channel MOSFET having an LDD structure. The Si substrate 1 is provided with various elements such as capacitors in addition to the MOSFET. The Si substrate 1 (active region 4)
The impurities introduced therein are activated by the heat treatment.

On the Si substrate 1, for example, SiO ₂ is formed so as to cover elements such as MOSFETs provided on the surface thereof.
Is provided. Although not shown, a predetermined portion of the interlayer insulating film 5 is provided with a connection hole which reaches a diffusion layer provided on the Si substrate 1 and a lower wiring. Inside the connection hole, for example, a W plug is buried using, for example, a TiN / Ti film as an adhesion layer (underlying barrier metal). An upper wiring 6 made of, for example, Al or an Al alloy is provided on the interlayer insulating film 5. The upper wiring 6 is connected to a diffusion layer, a lower wiring, and the like provided on the Si substrate 1 through a connection hole of the insulating film 5 in a region not shown in FIGS. The upper wiring 6 may be a groove wiring. Further, the inside of the connection hole provided in the interlayer insulating film 5 is replaced with a W plug to form an upper wiring 6.
May be embedded. Further, as the material of the upper wiring 6, Cu or Cu alloy may be used instead of Al or Al alloy.

Next, the method for fabricating the semiconductor device according to the first embodiment will be explained. 3 to 6 are sectional views for explaining the method for manufacturing the semiconductor device according to the first embodiment.

In order to manufacture the semiconductor device according to the first embodiment, first, the element isolation of the Si substrate 1 is performed by the STI method. Specifically, as shown in FIG. 3A, a pad oxide film 11 made of SiO ₂ is formed on one main surface of the Si substrate 1 by, for example, a thermal oxidation method. Next, the pad oxide film 11 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.
An Si ₃ N ₄ film 12 is formed thereon. As an example of conditions for forming the Si ₃ N ₄ film 12 by the LPCVD method, a mixed gas of dichlorosilane (SiH ₂ Cl ₂ ), ammonia (NH ₃ ), and nitrogen (N ₂ ) is used as a raw material gas. 50sccm the flow rate of ₂ Cl ₂ gas, NH ₃
The gas flow rate was 200 sccm and the N ₂ gas flow rate was 200
sccm, the growth pressure is 70 Pa, and the substrate temperature is 760.
° C.

Next, as shown in FIG. 3B, a resist pattern 13 having an opening at a portion corresponding to an element isolation region is formed on the Si ₃ N ₄ film 12 by, for example, lithography.
To form Next, using the resist pattern 13 as a mask, the Si ₃ N ₄ film 12 and the pad oxide film 11 are etched by, for example, a dry etching method, specifically, for example, a dry etching method using a parallel plate plasma etching apparatus. As an example of the etching conditions at this time, a mixed gas of CF ₄ and Ar is used as the process gas, the flow rate of the CF ₄ gas is 75 sccm, and A
The flow rate of the r gas was 25 sccm, the pressure was 5.3 Pa,
The high frequency output is set to 600W. Thereby, an opening 12a is formed in the Si ₃ N ₄ film 12 and the pad oxide film 11 in a portion corresponding to the element isolation region. After that, the resist pattern 13 used as the etching mask is removed. In the first embodiment, when forming the groove 2 in the Si substrate 1, after patterning the Si ₃ N ₄ film 12 and the pad oxide film 11, the resist pattern 13 used as an etching mask is removed. And then S
The Si substrate 1 is etched using the i ₃ N ₄ film 12 as a mask. This is performed by patterning the Si ₃ N ₄ film 12 and the pad oxide film 11 and leaving a resist pattern 13 used as an etching mask. The Si substrate 1 may be etched using the resist pattern 13 as a mask.

Next, as shown in FIG. 4A, a Si ₃ N ₄ having an opening 12a formed in a portion corresponding to the element isolation region.
Using the film 12 and the pad oxide film 11 as a mask, the Si substrate 1 is brought to a predetermined depth by, for example, a dry etching method, specifically, a dry etching method using a high-density plasma etching apparatus such as an ECR plasma etching apparatus. Etch. As an example of etching conditions at this time, Cl ₂ and O _{2 are used} as process gases.
Using a mixed gas of, the flow rate of Cl ₂ gas is 60 sccm,
The flow rate of O ₂ gas is 10 sccm, and the pressure is 1.3 P
a, microwave power 850 W, high frequency power 150 W
And As a result, a trench 2 for element isolation is formed in the Si substrate 1.

Next, although not shown, an SiO ₂ film (thermal oxide film) is formed on the inner wall of the groove 2 formed in the Si substrate 1 by a thermal oxidation method. In forming this thermal oxide film, from the viewpoint of minimizing the occurrence of crystal defects, thermal oxidation is performed, for example, at a substrate temperature of 1000 ° C., and the thickness of the thermal oxide film is about 20 nm. The groove 2 is formed by the formation of this thermal oxide film.
Is rounded, and the electric field concentration on this portion can be reduced. Further, by forming the thermal oxide film on the inner wall of the groove 2 in this manner, compared with the case where the SiO ₂ film as the filling material is directly buried in the groove 2,
The trap density at the i / SiO ₂ interface can be reduced, and a semiconductor device with better characteristics can be manufactured.

Next, as shown in FIG.
Method, preferably high density plasma CV with good embedding characteristics
By the method D, an SiO ₂ film 14 is formed on the entire surface so as to fill the inside of the groove 2 and the opening 12a. As an example of the conditions for forming the SiO ₂ film 14 by the high-density plasma CVD method at this time, silane (SiH
₄ ) Using a mixed gas of O ₂ and Ar, the flow rate of SiH ₄ gas is 300 sccm, and the flow rate of O ₂ gas is 700 sc
cm, the flow rate of Ar gas is 300 sccm, the pressure is 0.1 Pa, the microwave power is 3000 W, and the high frequency power is 2000 W. When the SiO ₂ film 14 is formed by the high-density plasma CVD method, since the etching and the deposition proceed simultaneously, the SiO ₂ film 14 is deposited flat on the groove 2 and the Si ₃ N ₄ film is formed. On top of 12 is a SiO ₂ film 14
Accumulate while forming a slope inclined at, for example, 45 ° inward from the edge portion. At this time, in the portion corresponding to the narrow active region, the S deposited on the Si ₃ N ₄
The slopes extending from both sides of the iO ₂ film 14 intersect at the center,
In the portion corresponding to the wide active region, the Si ₃ N ₄ film 1
The slopes on both sides of the SiO ₂ film 14 deposited on the substrate ₂ do not intersect, and a flat portion is formed at the center.

Next, the SiO ₂ film 14 is densified by heat-treating the SiO ₂ film 14 in an atmosphere containing an oxidizing gas such as oxygen. The heat treatment at this time is
For example, it is performed at a temperature of 900 ° C. or more in an O ₂ gas atmosphere.
This heat treatment may be performed in an atmosphere of an inert gas such as N ₂ .

Next, as shown in FIG. 5A, a resist pattern 15 having a predetermined shape is formed on the SiO ₂ film 14 by lithography. This resist pattern 15 includes
An opening 15a is provided so as to surround a flat portion formed in the SiO ₂ film 14.

Next, as shown in FIG. 5B, using the resist pattern 15 as a mask, for example, by a dry etching method, specifically, for example, by a dry etching method using a magnetron etching apparatus, the SiO ₂ film in the opening 15a is formed. 14 is etched until the surface of the underlying Si ₃ N ₄ film 12 is exposed. As an example of the etching conditions in this case, C ₄ F as a process gas
₈ , a mixed gas of CO and Ar, a flow rate of C ₄ F ₈ gas of 5 sccm, a flow rate of CO gas of 4 sccm, Ar
The gas flow rate was 100 sccm, the pressure was 2.7 Pa,
The high frequency power is 800 W. As a result, the flat portion formed on the SiO ₂ film 14 is removed, and a protrusion 14a is formed around the flat portion. After that, the resist pattern 15 used as the etching mask is removed.

Next, as shown in FIG. 6A, by CMP, as the polishing stopper and the Si ₃ N ₄ film 12, so as to leave the SiO ₂ film 14 only in the trench 2 and the opening 12a, Si ₃ N _{4 The} SiO ₂ film 14 deposited on the film 12 is polished and removed. An example of the CMP conditions at this time is as follows. Silica particles (14
wt%), the polishing plate rotation speed was 20 rpm, and the wafer holding sample stage rotation speed was 20.
rpm and the polishing pressure is 500 gf / cm ² .

Next, as shown in FIG. 6B, the Si ₃ N ₄ film 12 is wet-etched using hot phosphoric acid.
Is removed. Next, the pad oxide film 11 is removed by a wet etching method using hydrofluoric acid. Thereby, S
A field insulating film 3 made of SiO ₂ is formed inside a groove 2 formed in the i-substrate 1, and an active region 4 is exposed on the surface. As described above, element isolation of the Si substrate 1 is performed.

Next, the MOSFE is formed by a conventionally known method.
Various elements such as T and capacitors are formed. here,
In the case of forming an n-channel MOSFET having an LDD structure, after sacrifice oxidation of the surface of the active region 4, a p-type material such as boron (B) is formed in the active region 4 by, for example, ion implantation.
A p-type well is formed by doping a type impurity. Next, the sacrificial oxide film is removed by, for example, a wet etching method using hydrofluoric acid. For example, a gate insulating film such as a SiO ₂ film is formed on the surface of the active region 4 by a thermal oxidation method. Next, after forming a polycrystalline Si film as a gate electrode material on the entire surface by, for example, the CVD method, the gate electrode is formed on the gate insulating film by patterning the polycrystalline Si film into a predetermined shape by, for example, the RIE method. Form.

Next, using the gate electrode as a mask, for example, phosphorus (P)
Is doped at a low concentration. As a result, in the active region 4, n is self-aligned with respect to the gate electrode.
^-A mold region is formed. Next, for example, by a CVD method,
After forming a SiO ₂ film of a predetermined thickness on the entire surface,
The O ₂ film is etched back in a direction perpendicular to the surface of the Si substrate 1 by, eg, RIE to form a sidewall spacer on the side surface of the gate electrode. Next, an n-type impurity such as arsenic (As) is heavily doped into the active region 4 by, for example, an ion implantation method using the gate electrode and the sidewall spacer as a mask. Next, heat treatment is performed as necessary to electrically activate the implanted impurities. This heat treatment is performed, for example, at 800 ° C. for 10 minutes. Thus, n ⁺ -type source and drain regions are formed in the active region 4 in a self-aligned manner with respect to the sidewall spacer. Thereby, the n-channel M having the LDD structure
An OSFET is formed.

After the various elements are formed on the Si substrate 1 as described above, as shown in FIG. 2, the Si substrate 1 is covered by, for example, a CVD method so as to cover the elements formed on the Si substrate 1.
An interlayer insulating film 5 such as a SiO ₂ film is formed thereon. Next, the surface of the interlayer insulating film 5 is planarized by, for example, a CMP method. Next, a resist pattern (not shown) having a predetermined shape is formed on the interlayer insulating film 5 by a lithography method.
By etching the interlayer insulating film 5 by the E method,
Form a connection hole. Next, a Ti film and a TiN film are sequentially formed on the entire surface including the inner wall of the connection hole by, for example, a sputtering method to form a TiN / Ti film. Next, a W film is formed on the entire surface by, for example, a CVD method to fill the connection holes. Next, the W film and the TiN / Ti film formed in portions other than the insides of the connection holes are removed by, for example, RIE. As a result, a W plug is formed in the connection hole using the TiN / Ti film as an adhesion layer. Next, an Al alloy film is formed on the entire surface by, for example, a sputtering method.
After a resist pattern (not shown) having a predetermined shape is formed on the l film, a predetermined portion of the Al film is etched and patterned by using the resist pattern as a mask, for example, by a dry etching method. Thus, the upper wiring 6 made of the Al alloy is formed. Thereafter, the resist pattern used for the etching mask is removed.

As described above, the intended semiconductor device is completed.

According to the first embodiment configured as described above, when the active regions 4 have portions that intersect at an angle of 90 ° with each other, the active regions 4 near the intersections are shifted by 90 °. Since it is bent at a larger angle and the corners of the groove 2 around the intersection are cut off, a thermal oxidation step for forming a thermal oxide film on the inner wall of the groove 2, and SiO as the field insulating film 3 ₂ During the heat treatment performed after forming the groove 2 in the Si substrate 1, such as a heat treatment step for densifying the film 14 and a heat treatment step for activating impurities introduced into the Si substrate 1, Stress applied to the vicinity of the intersection can be reduced as compared with the related art. Therefore, even if the heat treatment is performed after forming the groove 2 in the Si substrate 1, the heat treatment
Since it is possible to suppress the occurrence of crystal defects that cause an increase in leakage current in the Si substrate 1, a highly reliable semiconductor device can be obtained.

Next, a second embodiment of the present invention will be described. FIG. 7 is a plan view of the semiconductor device according to the first embodiment of the present invention.

In the semiconductor device according to the second embodiment, when the active regions 4 have portions that cross each other at an angle of 90 ° or less, the crossing portions of the active regions 4 are removed, and the removed portions are removed. Are connected to each other by an upper wiring 6.

For example, FIG. 7A shows a portion of the semiconductor device according to the second embodiment shown in FIG. 12A of the conventional semiconductor device, that is, a right angle bent portion of the active region 104 in which the active region 104 is bent by 90 °. The vicinity of the corresponding part is shown.
In FIG. 7A, the active region 4a extending in the vertical direction and the active region 4b extending in the horizontal direction extend in the directions perpendicular to each other, and the width of the active regions 4a and 4b is, for example, 0.1 mm. Several μm
〜About several μm.

As shown in FIG. 7A, in the semiconductor device according to the second embodiment, in the portion corresponding to the right-angle bent portion of the active region, the active region 4a extending in the vertical direction in the active region 4 is used. The vicinity of the intersection between the active region 4b and the laterally extending active region 4b is removed, and the field insulating film 3 is provided in the removed portion. In the example illustrated in FIG. 7A, the vicinity of the portion corresponding to the L-shaped corner of the active region 4 is removed, and the portion that should originally intersect (bend) into the L-shape is divided by the field insulating film 3. Active region 4a and active region 4b. An active region 4a and an active region 4b separated by a field insulating film 3 provided in a removed portion of the active region 4 are connected to an upper wiring provided on an interlayer insulating film 5 (not shown in FIG. 7A). 6 are interconnected. 7A, reference numeral 7 denotes a connection hole provided in the interlayer insulating film 5.

FIGS. 7B and 7C show a portion of the semiconductor device according to the second embodiment shown in FIGS. 12B and 12C of the conventional semiconductor device, that is, the active region 104 at an angle of 90 ° to each other. The vicinity of a portion corresponding to a right-angle intersection of the crossed active regions is shown. 7B and 7C, the center line of the active region 4a 'extending in the vertical direction coincides with the center line of the active region 4a'', and the center line of the active region 4b' extending in the horizontal direction corresponds to the active line. The center line of the region 4b ″ coincides with the center line. Further, the active regions 4a ', 4
The center line of a ″ is orthogonal to the center lines of the active regions 4b ′ and 4b ″. Active regions 4a ', 4a ", 4b
, 4b '' have a width of, for example, 0. It is about several μm to several μm.

As shown in FIGS. 7B and 7C, in the semiconductor device according to the second embodiment, the portion corresponding to the right-angled bent portion of the active region similarly extends in the vertical direction of the active region 4. The vicinity of a portion where the existing active region 4a intersects with the laterally extending active region 4b is removed, and the field insulating film 3 is provided in the removed portion. FIG.
In the example shown in FIG. 3B, the active region 4a ', 4a' in which the vicinity of the portion corresponding to the cross-shaped intersection of the active region 4 is removed, and the portion that should originally cross the cross-shaped portion is separated by the field insulating film 3 is shown. ′ And active regions 4b ′, 4b ″. In the example shown in FIG. 7C, the vicinity of the portion corresponding to the T-shaped intersection of the active region 4 is removed, and the portion that should originally intersect the T-shape is separated from the active region 4a by the field insulating film 3. And active area 4
b ′ and 4b ″. Then, the active regions 4 a ′, 4 a ″, 4 b ′, and 4 b ″ separated by the field insulating film 3 provided in the removed portion of the active region 4.
And the active regions 4a, 4b ', 4b''
They are interconnected by an upper wiring 6 provided on an interlayer insulating film 5 (not shown in FIGS. 7B and 7C).

As shown in FIG. 8, the upper wiring 6 for connecting the divided active regions 4 to each other has a W plug 9 and a TiN /
The active region 4 is in contact via the Ti film 8.

FIG. 9 shows a modification of the second embodiment of the present invention. Here, FIGS. 9A to 9C show portions corresponding to FIGS. 7A to 7C, respectively. FIG.
9 is compared with the modified example shown in FIG. 9, in the example shown in FIG. 7, a portion corresponding to a corner portion of the active region 4 or a portion corresponding to an intersection of the active region 4 is removed. In the modification shown in FIG. 9, a portion adjacent to the corner of the active region 4 or a portion adjacent to the intersection of the active region 4 is removed. Specifically, in the example shown in FIG. 9A, a portion of the active region 4 adjacent to the L-shaped corner portion on the side of the active region 4b extending in the lateral direction is removed, and the portion is originally L-shaped. The portion to be bent is formed into an active region 4a and an active region 4b separated by the field insulating film 3. In the example shown in FIG. 9B,
Of the portion of the active region 4 adjacent to the cross-shaped intersection,
The portion on the side of the active region 4b is removed, and the portion that should originally cross in a cross shape is constituted by the active region 4a separated by the field insulating film 3 and the active regions 4b 'and 4b ". In the example shown in FIG. 9C, of the portion adjacent to the T-shaped intersection of the active region 4, the portion on the active region 4 a side is removed, and the portion that should originally cross the T-shape is divided by the field insulating film 3. The active region 4a and the active region 4b are formed.

Although not shown, in the semiconductor device according to the second embodiment, a portion corresponding to a portion where the active regions 104 cross each other at an angle smaller than 90 ° in the conventional semiconductor device also corresponds to the above-described portion. 7A to 7C or 9A to 9C, the crossing portion of the active region 4 is removed, and the active regions 4 at both ends of the removed portion are connected to each other by the upper wiring 6. .

The configuration of the semiconductor device according to the second embodiment other than the above is the same as that of the semiconductor device according to the first embodiment, and a description thereof will be omitted.

In the method for fabricating a semiconductor device according to the second embodiment, as shown in FIG. 8, an interlayer insulating film 5 is formed so that active regions 4 separated by removing intersections are connected to each other. The method is the same as the method of manufacturing the semiconductor device according to the first embodiment, except that a connection hole 7 is formed in the semiconductor device 1 and the upper wiring 6 is formed on the interlayer insulating film 5, and thus the description is omitted.

According to the second embodiment configured as described above, when the active regions 4 have portions that cross each other at an angle of 90 ° or less, the crossing portions of the active regions 4 are removed. Then, the active regions 4 at both ends of the removed portion are connected to each other by an upper wiring 6, so that the active regions 4
By removing a portion that intersects at an angle of 0 ° or less from the Si substrate 1, the same advantage as in the first embodiment can be obtained. In the second embodiment, when the upper wiring 6 is formed on the interlayer insulating film 5, the active regions 4 separated by using the material of the upper wiring 6 are connected to each other. However, the number of steps for manufacturing a semiconductor device does not increase.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible. For example, the shapes, numerical values, structures, materials, processes, and the like described in the first and second embodiments are merely examples, and different shapes, numerical values, structures, materials, processes, and the like may be used as necessary. May be used.

Further, the above-described first embodiment and second embodiment may be appropriately combined. Specifically, for example, in the semiconductor device, a portion corresponding to a right-angle bent portion of the active region is configured in the same manner as in the first embodiment, and a portion corresponding to a right-angle intersection of the active region is defined in the second embodiment. The configuration may be the same as in the above. Further, in the semiconductor device, part of a portion corresponding to a right-angle bent portion (or right-angle intersection) of the active region is configured in the same manner as in the first embodiment, and the rest is configured in the same manner as in the second embodiment. May be.

[0067]

As described above, according to the first aspect of the present invention, when the active regions have portions which cross each other at an angle of 90 degrees or less, the active regions in the vicinity of the crossing portions are reduced by 90%. By bending at an angle greater than the degree and cutting off the corners of the groove around the intersection, the stress applied to the vicinity of the intersection of the active region during the heat treatment after the formation of the groove is reduced as compared with the conventional method be able to. Therefore, even if the heat treatment is performed after the groove is formed in the semiconductor substrate, generation of crystal defects in the semiconductor substrate due to the heat treatment can be suppressed. Thus, a highly reliable semiconductor device with reduced leakage current can be obtained.

According to the second aspect of the present invention, when the active regions have portions crossing each other at an angle of 90 degrees or less, the crossing portion of the active region is removed, and both ends of the removed portion are removed. Since the active regions are connected to each other by wiring, and a portion where the active regions cross each other at an angle of 90 degrees or less is removed from the semiconductor substrate, heat treatment may be performed after forming a groove in the semiconductor substrate. Further, generation of crystal defects in the semiconductor substrate due to the heat treatment can be suppressed. Thus, a highly reliable semiconductor device with reduced leakage current can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a plan view of a semiconductor device according to a modification of the second embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining an element isolation method for a Si substrate by the STI method.

FIG. 11 is a cross-sectional view for describing a method of isolating a Si substrate by an STI method.

FIG. 12 is a plan view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Si substrate, 2 ... groove, 3 ... field insulating film, 4, 4a, 4a ', 4a ", 4b, 4b', 4
b ″: active region, 11: pad oxide film, 12
... Si ₃ N ₄ film, 14 ... SiO ₂ film

Claims (17)

[Claims] An element isolation groove having a structure in which an element isolation groove is provided on one main surface and an insulating film is buried inside the groove, and an active region is formed in a portion surrounded by the element isolation region. In the semiconductor device using the semiconductor substrate having the above, when the active regions have portions crossing each other at an angle of 90 degrees or less, the active region near the crossing portions is bent at an angle larger than 90 degrees. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said semiconductor device is manufactured through a heat treatment step after forming said groove in said semiconductor substrate. 3. The semiconductor device according to claim 1, wherein an oxide film formed by thermally oxidizing the semiconductor substrate is provided on an inner wall of the groove. 4. The semiconductor device according to claim 1, wherein said insulating film is densified by a heat treatment. 5. The semiconductor device according to claim 1, wherein impurities are introduced into said semiconductor substrate and said impurities are activated by heat treatment. 6. The semiconductor device according to claim 1, wherein said semiconductor substrate is a silicon substrate. 7. The semiconductor device according to claim 6, wherein said insulating film is made of silicon oxide. 8. The groove is formed by sequentially forming a silicon oxide film and a silicon nitride film on the silicon substrate, patterning the silicon nitride film and the silicon oxide film into a predetermined shape, and then forming the silicon nitride film and the oxide film on the silicon substrate. 7. The semiconductor device according to claim 6, wherein the semiconductor device is formed by etching the silicon substrate using a silicon film as a mask. 9. An element isolation region having a structure in which an element isolation groove is provided on one main surface and an insulating film is buried inside the groove, and an active region is formed in a portion surrounded by the element isolation region. In the semiconductor device using the semiconductor substrate having the above, when the active regions have portions crossing each other at an angle of 90 degrees or less, the crossing portions of the active region are removed, and both ends of the removed portion are removed. A semiconductor device, wherein the active regions are interconnected by wiring. 10. The semiconductor device according to claim 9, wherein the wiring is provided on the semiconductor substrate via an interlayer insulating film.
13. The semiconductor device according to claim 1. 11. The semiconductor device according to claim 9, wherein said semiconductor device is manufactured through a heat treatment step after forming said groove in said semiconductor substrate. 12. The semiconductor device according to claim 9, wherein an oxide film formed by thermally oxidizing the semiconductor substrate is provided on an inner wall of the groove. 13. The semiconductor device according to claim 9, wherein said insulating film is densified by heat treatment. 14. The semiconductor device according to claim 9, wherein impurities are introduced into said semiconductor substrate and said impurities are activated by heat treatment. 15. The semiconductor device according to claim 9, wherein said semiconductor substrate is a silicon substrate. 16. The semiconductor device according to claim 15, wherein said insulating film is made of silicon oxide. 17. The groove is formed by sequentially forming a silicon oxide film and a silicon nitride film on the silicon substrate, patterning the silicon nitride film and the silicon oxide film into a predetermined shape, and then forming the silicon nitride film and the oxide 16. The semiconductor device according to claim 15, wherein the semiconductor device is formed by etching the silicon substrate using a silicon film as a mask.