JP2004152965A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for reducing the micro roughness on the surface of a silicon substrate. <P>SOLUTION: A manufacturing method of a semiconductor device has a process (a) for preparing a silicon substrate provided with a crystal face having high symmetry or a surface following vicinity of it, a hydrogen annealing process (b) for annealing the silicon substrate in an atmosphere containing hydrogen and removing a natural oxide film, an inert gas annealing process (c) for annealing the silicon substrate in an inert gas atmosphere after the process (b) and generating migration of a silicon atom, and a process (d) for forming a gate insulating film on a surface of the silicon substrate after the process (c). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a shallow carrier transport region and a semiconductor device.
[0002]
[Related technology]
Various semiconductor devices are formed by forming various semiconductor elements on a silicon substrate. Representative semiconductor elements are n-channel and p-channel MOS transistors.
[0003]
2. Description of the Related Art In recent years, as the degree of integration has been improved, semiconductor elements constituting a semiconductor integrated circuit device have been miniaturized. With miniaturization, the gate length of the MOS transistor becomes shorter, and the junction depth of the source / drain region becomes shallower. Carriers such as electrons and holes flowing through the channel region below the gate electrode are transported closer to the surface of the semiconductor substrate. If there are irregularities on the surface of the semiconductor substrate, these irregularities will form scattering centers for the carriers. If there are many scattering centers, the mobility will decrease. In this respect, the surface of the channel region is preferably flat.
[0004]
For a high-end product of a MOS type semiconductor integrated circuit device, an epitaxial substrate having a high resistivity epitaxial layer with few crystal defects formed on a low resistivity base silicon substrate is used. A silicon wafer for a MOS semiconductor integrated circuit device is usually cut in the (100) plane direction.
[0005]
On a silicon substrate having a surface strictly aligned with the (100) plane, epitaxial growth is difficult to occur, abnormal growth occurs, and surface haze (roughness) tends to occur. The surface haze may be counted as particles by a particle counter or the like, which makes it difficult to increase the yield.
[0006]
For this reason, as the (100) epitaxial substrate, a substrate having a surface that is intentionally off-angled by about 0.3 to 0.5 degrees from the (100) plane is used. Epitaxial growth is easy on a base substrate provided with an off angle, and surface haze hardly occurs. Usually, an off angle is provided in the x direction and the y direction from the (100) plane.
[0007]
In a manufacturing process of a semiconductor integrated circuit device, a chemical solution treatment for dissolving a silicon surface layer after epitaxial growth is performed for the purpose of removing particles, removing metal contamination, and the like. As a result, the micro-roughness of the active region surface layer of the semiconductor integrated circuit device is never good. Therefore, it is expected that carrier scattering is caused by surface irregularities.
[0008]
In addition, the gate insulating film is becoming thinner with miniaturization. A gate insulating film formed on the surface of a substrate having high micro-roughness tends to have low withstand voltage. In order to form a thin gate oxide film, it is preferable that an incomplete oxide film such as a natural oxide film does not exist on the surface of the active region. In this specification, an incomplete chemical oxide film generated by a chemical solution treatment or the like is also called a natural oxide film.
[0009]
In order to improve the flatness of the surface of the silicon substrate or to improve the breakdown voltage of the gate insulating film, it has been proposed to perform high-temperature annealing in a vacuum, in a hydrogen gas, or in an Ar gas.
[0010]
[Patent Document 1]
JP-A-9-51097 [Patent Document 2]
Japanese Patent Application Laid-Open No. Hei 8-322443 [Patent Document 3]
JP-A-5-347256
[Problems to be solved by the invention]
An object of the present invention is to provide a technique for reducing micro roughness on the surface of a silicon substrate.
[0012]
It is another object of the present invention to provide a method for performing a process for restoring the shape of steps and terraces on a silicon substrate surface.
Still another object of the present invention is to provide a semiconductor device with improved surface flatness and improved electronic characteristics.
[0013]
[Means for Solving the Problems]
According to one aspect of the present invention, (a) a step of preparing a silicon substrate having a crystal plane with high symmetry or a surface along the vicinity thereof; and (b) annealing the silicon substrate in an atmosphere containing hydrogen. A hydrogen annealing step of removing a natural oxide film on the silicon surface; and (c) after the step (b), annealing the silicon substrate in an inert gas atmosphere to cause migration of silicon atoms. There is provided a method of manufacturing a semiconductor device, comprising: an annealing step; and (d), after the step (c), a step of forming a gate insulating film on the surface of the silicon substrate.
[0014]
Here, the vicinity of a highly symmetric crystal plane refers to a plane having an off angle of about 0.2 degrees or less from a highly symmetric crystal plane such as a (100) plane.
According to another aspect of the present invention, (a) a step of preparing a silicon substrate having a crystal plane having high symmetry or a surface along the vicinity thereof; and (b) forming the silicon substrate at 900 ° C. to 1050 ° C. A hydrogen annealing step of annealing in a hydrogen-containing atmosphere for a finite time of 60 seconds or less to remove a natural oxide film, and (c) forming a gate insulating film on the surface of the silicon substrate after the step (b) And a method of manufacturing a semiconductor device including:
[0015]
Here, the vicinity of a highly symmetric crystal plane refers to a plane having an off angle of about 0.2 degrees or less from a highly symmetric crystal plane such as a (100) plane.
According to still another aspect of the present invention, a low-resistivity silicon base substrate having a surface having an off angle from a highly symmetric crystal plane of 0.02 degrees or less, and a low resistance silicon base substrate formed on the silicon base substrate, An epitaxial silicon layer having a high resistivity and having a surface with exposed terraces and steps; a shallow trench isolation region formed in the epitaxial silicon layer to define an active region; and formed on the active region surface. A gate insulating film, a gate electrode formed on the gate insulating film, and a source / drain impurity-added region with a junction depth of 0.1 μm or less formed in an active region on both sides of the gate electrode. A semiconductor device is provided.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a flowchart showing main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. A method of manufacturing a semiconductor device will be described with reference to the cross-sectional views of FIGS. First, in step S1, initial oxidation is performed on the surface of the silicon substrate, and then a mask layer of a silicon nitride film is formed.
[0017]
As shown in FIG. 2A, a buffer silicon oxide film 2 having a thickness of, for example, about 10 nm is thermally coated on the surface of an epitaxial silicon substrate 1 on which a high resistivity epitaxial layer 101 is grown on a low resistivity base silicon substrate 100. It is formed by oxidation. This silicon oxide film functions as a buffer layer for the silicon nitride film formed thereon, and alleviates the stress applied by the silicon nitride film.
[0018]
The underlying silicon substrate 100 has a crystal plane with high symmetry or a surface along the vicinity thereof, for example, a surface that is 0.2 degrees or less from the (100) plane.
As shown in FIG. 2B, micro-roughness is present on the surface of the silicon substrate 1, and a crystal plane such as a (100) plane is not evident. The thermal oxide film 2 grows reflecting the surface irregularities.
[0019]
As shown in FIG. 2C, a silicon nitride film 3 having a thickness of, for example, about 100 to 150 nm is deposited on the buffer silicon oxide film 2 by chemical vapor deposition (CVD). The silicon nitride film 3 functions as a mask layer in a later etching step.
[0020]
Returning to FIG. 1, in step S2 following step S1, an element isolation groove is formed.
As shown in FIG. 2C, in order to form an element isolation groove, a photoresist layer is applied on the silicon nitride film 3 and exposed and developed to form a resist pattern 4 for forming an element isolation region. The resist pattern 4 has an opening corresponding to the element isolation groove.
[0021]
Using the resist pattern 4 as a mask, the silicon nitride film 3 and the silicon oxide film 2 are etched, and the silicon substrate 1 is further etched to form a trench 6 having a depth of, for example, 500 nm. The silicon nitride film 3 functions as a mask when etching the trench, and keeps the shape of the trench accurately.
[0022]
Note that a mixed gas of CF ₄ , CHF ₃ , and Ar is used as an etching gas for etching the silicon nitride film and the silicon oxide film. For etching the silicon substrate, for example, a mixed gas of HBr and O ₂ is used as an etching gas. After that, the resist pattern 4 is removed. Thus, an element isolation groove is formed.
[0023]
Returning to FIG. 1, step S3 is performed after step S2 to form an element isolation layer.
As shown in FIG. 2D, first, a silicon oxide film 7 having a thickness of, for example, about 10 nm is formed on the surface of the silicon substrate 1 exposed in the trench 6 by thermal oxidation. A silicon oxide film 9 is deposited to a thickness of, for example, 500 nm by, for example, high-density plasma (HDP) chemical vapor deposition (CVD) so as to fill the trench 6 in which the silicon oxide film 7 is formed. The silicon oxide film 9 forms an uneven surface according to the unevenness of the underlying surface.
[0024]
In FIG. 1, after step S3, step S4 is performed to remove unnecessary portions of the formed film.
As shown in FIG. 3E, the silicon oxide film 9 on the surface of the silicon nitride film 3 is polished by, for example, chemical mechanical polishing (CMP) to form a flat surface. The CMP is stopped at the silicon nitride film 3. Thereafter, it is preferable to perform annealing in a nitrogen (N ₂ ) atmosphere, for example, at 1000 ° C. to densify the buried silicon oxide film 9.
[0025]
As shown in FIG. 3F, the silicon nitride film 3 used as a mask for forming the isolation trench is removed by wet etching with hot phosphoric acid. The buried silicon oxide film 9 is also slightly etched.
[0026]
In FIG. 1, following step S4, in step S5, ion implantation for forming a well, a chemical solution treatment for removing the buffer silicon oxide film after the ion implantation, and the like are performed.
As shown in FIG. 3G, the n-channel region and the p-channel region are individually exposed with a resist mask, and ions are implanted through the silicon oxide film 2 to form a p-type well 10p and an n-type well 10n. I do.
[0027]
Thereafter, the buffer silicon oxide film 2 is removed by, for example, wet etching using diluted hydrofluoric acid. The silicon surface of the active region is exposed. Chemical solution treatment such as particle removal and metal removal may be performed together. As a by-product of the chemical treatment, a natural oxide film called a chemical oxide is formed on the silicon surface.
[0028]
In FIG. 1, after exposing the surface of the active region and before oxidizing the gate, hydrogen annealing and inert gas annealing in steps S6 and S7 are performed.
FIG. 4H shows hydrogen annealing. For example, the silicon substrate 1 is heated to 900 ° C. to 1050 ° C. in a hydrogen atmosphere of 150 torr or less, and annealing is performed for a finite time of 60 seconds or less. The natural oxide film formed on the surface of the silicon substrate 1 by the chemical treatment is etched and removed by the hydrogen annealing. It is considered that terraces and steps of crystal planes are exposed on the surface of the silicon substrate 1.
[0029]
FIG. 4I shows an inert gas anneal following the hydrogen anneal. For example, the silicon substrate 1 is annealed at 500 ° C. to 1050 ° C. for a finite time of 60 seconds or less in a He atmosphere at normal pressure or reduced pressure. It is considered that this inert gas annealing causes migration of silicon atoms on the surface of the silicon substrate 1 and migrates the separated silicon atoms and the like on the terrace to the end of the terrace and the like, thereby reducing micro roughness. Local island-like areas are reduced, surface flatness is improved, and average terrace length is increased.
[0030]
The inert gas annealing may be performed in another inert gas atmosphere such as Ar, in addition to the He atmosphere. It may be performed under reduced pressure, normal pressure, or in a pressurized atmosphere. Note that the inert gas annealing is not always an essential step and may be omitted.
[0031]
FIG. 4 (J) schematically shows the structure of the terraces and steps when the macroscopic surface is flat. Assuming that the step height h is 2.7 A corresponding to a monoatomic layer, the length L of the terrace depends on the off-angle of the silicon substrate 1. When the off angle from the (100) plane is θ = 0.4 °, the average terrace length L is ideally 37 nm.
[0032]
When the off angle from the (100) plane is reduced to 0.05 °, the terrace length L increases to 311 nm. As described above, if the off angle is set low, a wide terrace length can be realized. When the surface of the silicon substrate 1 is just the (100) plane, the terrace length L is ideally infinite. From the viewpoint of widening the terrace length, it is preferable to adopt a small off angle of 0.2 ° or less instead of the conventional off angle of 0.3 ° to 0.5 °.
[0033]
Since the accuracy of the X-ray measurement performed for cutting out the wafer is one minute, an off-angle of about ± 0.02 ° or less can be generated even when the wafer is cut just by the (100) plane. A direction aiming at a crystal plane with high symmetry is expressed as an off angle of 0.02 ° or less.
[0034]
Subsequent to the annealing, gate oxidation in step S8 in FIG. 1 is performed.
As shown in FIG. 5K, thermal oxidation is performed on the exposed silicon surface of the active region to form a gate oxide film 11 having a thickness of, for example, about 2 nm. In the case where the structure of the terrace and the step as shown in FIG. 4J is exposed, the oxidation proceeds almost uniformly, so that a gate oxide film is formed reflecting the shape of the terrace and the step.
[0035]
FIG. 6 shows that a silicon substrate provided with a 0.4 ° off-angle from the (100) plane was subjected to hydrogen annealing at 1000 ° C. for 3 seconds and then subjected to gate oxidation without performing inert gas annealing. 3 shows an atomic force microscope (AFM) image. Irregular irregularities are distributed on the surface, and terraces and steps have not yet been revealed. Rms indicating the surface roughness was about 0.12 nm.
[0036]
FIG. 7 shows a case in which a silicon substrate provided with an off angle of 0.02 ° or less from the (100) plane is subjected to hydrogen annealing at 1000 ° C. for 3 seconds, without performing inert gas annealing, and performing gate oxidation. 3 shows an AFM image of the surface of FIG. A flat terrace and a step shape at the end of the terrace are observed, but the shape of the terrace is quite irregular.
In FIG. 7, Rms indicating the surface roughness was about 0.14 nm. However, within one step, Rms was extremely small at about 0.049 nm.
[0037]
FIG. 8 shows that a silicon substrate provided with an off angle of 0.02 ° or less from the (100) plane is subjected to hydrogen annealing at 1000 ° C. for 3 seconds, followed by He annealing at 1000 ° C. for 10 seconds. An AFM image of the surface after gate oxidation has been shown. Clearly, large terraces and steps are exposed. The steps are observed in a direction substantially orthogonal to the <110> direction.
[0038]
In FIG. 8, Rms indicating the surface roughness was about 0.13 nm. In each terrace, Rms was extremely small at about 0.034 nm.
If the terrace width is long, it becomes easy to form the channel of the MOS transistor in one terrace or in a small number of adjacent terraces. For example, if the <110> direction is defined as the gate length direction, a MOS transistor having a wide gate width can be formed in a limited terrace. If a MOS transistor having a narrow gate width is formed with the gate width direction being <110>, it is easy to connect the source and the drain with one or a small number of terraces. A semiconductor element in which carrier scattering due to steps is suppressed can be realized.
[0039]
The following can be inferred from the results of FIGS. It can be seen that the surface roughness can be reduced by performing hydrogen annealing even when the off angle is 0.3 to 0.5 ° as in the conventional case. When the off angle is reduced to 0.02 ° or less, the terrace and the step structure can be easily exposed only by hydrogen annealing.
[0040]
The natural oxide film on the surface of the silicon substrate is removed by the annealing treatment, and the crystal plane structure of the terrace and the step becomes apparent. The off-angle is preferably set to 0.2 ° or less.
[0041]
If the inert gas annealing is performed after the hydrogen annealing, the structure of the terrace and the step is more easily exposed. When hydrogen annealing and inert gas annealing are performed on a substrate with a reduced off-angle, a wide terrace can be realized. If such a substrate is used, it is possible to realize high carrier mobility with little unevenness on the surface.
[0042]
After the gate oxidation, the process proceeds to step S9 in FIG. 1 to form a gate electrode. Thereafter, source / drain regions are formed in step S10, and wiring is formed in step S11.
[0043]
FIG. 5 (L) shows that a polycrystalline silicon layer 12 is formed on the surface of the silicon substrate on which the gate insulating film 11 is formed by low-pressure (LP) CVD at a temperature of, for example, about 600 ° C. to form a gate electrode. This shows a state where about 100 nm is formed. The polycrystalline silicon layer 12 may be a non-doped silicon film or a silicon film doped with impurities. In the case of a silicon film doped with impurities, a region for forming an n-channel MOS transistor is doped with phosphorus (P), and a region for forming a p-channel MOS transistor is doped with boron (B).
[0044]
As shown in FIG. 5M, the polycrystalline silicon layer 12 is patterned using a resist mask to form a gate electrode 12. By performing ion implantation, LDD (lightly doped drain) regions 15 are formed on both sides of the gate electrode 12.
[0045]
Thereafter, a silicon oxide film 16 having a thickness of, for example, 10 nm is deposited by LPCVD at a substrate temperature of 600 ° C., and a silicon nitride film 17 having a thickness of, for example, 90 nm is deposited thereon by LPCVD at a substrate temperature of about 600 ° C. Thereafter, by performing anisotropic etching, the sidewall spacers 16 and 17 are left only on the side walls of the gate electrode 12. By performing ion implantation for forming source / drain regions, high-concentration source / drain regions 19 having a junction depth of 0.1 μm or less are formed.
[0046]
Further, a metal capable of being silicided, such as Co, is deposited on the surface as needed, and an oxygen shielding layer, such as TiN, is formed thereon as needed, and heated to cause a silicidation reaction, thereby exposing the silicon. A silicide layer 20 is formed on the surface of the silicon. The unreacted metal layer and the oxygen shielding layer are removed.
[0047]
Thereafter, the gate electrode is buried with an insulating film by a known method, necessary W plugs and the like are formed, an insulating layer is further formed, and a wiring layer is formed. An arbitrary number of wiring layers is provided as needed. Thus, a semiconductor integrated circuit device can be formed.
[0048]
In the embodiment described above, the natural oxide film and the like on the silicon substrate surface are removed by etching by hydrogen gas annealing, and migration of silicon atoms is caused by He gas annealing. Similar effects can be expected by using another inert gas instead of He gas. For example, Ar gas could be used.
[0049]
The semiconductor element to be formed is not limited to a MOS transistor. The crystal plane having high symmetry may be the (100) plane or the (111) plane. It will be apparent to those skilled in the art that various other modifications, improvements, and combinations are possible.
[0050]
【The invention's effect】
As described above, according to the present invention, the flatness of the surface of the silicon substrate can be improved.
[0051]
Carrier scattering can be reduced, and high mobility can be realized.
From the above embodiments, the inventions described in the following supplementary notes are derived.
(Supplementary Note 1) (a) a step of preparing a silicon substrate having a highly symmetric crystal plane or a surface along the vicinity thereof;
(B) a hydrogen annealing step of annealing the silicon substrate in an atmosphere containing hydrogen to remove a natural oxide film on the silicon surface;
(C) after the step (b), annealing the silicon substrate in an inert gas atmosphere to cause migration of silicon atoms;
(D) after the step (c), forming a gate insulating film on the surface of the silicon substrate;
A method for manufacturing a semiconductor device including:
[0052]
(Supplementary Note 2) The method of Supplementary Note 1, wherein the step (b) is performed at 900 ° C. to 1050 ° C. for a finite time of 60 seconds or less.
(Supplementary Note 3) The method for manufacturing a semiconductor device according to Supplementary Note 1 or 2, wherein the step (b) is performed under reduced pressure lower than normal pressure.
[0053]
(Supplementary Note 4) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the step (c) is performed at 500 ° C. to 1050 ° C. for a finite time length of 60 seconds or less.
(Supplementary Note 5) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the step (c) is performed in a He atmosphere.
[0054]
(Supplementary Note 6) The silicon substrate is an epitaxial substrate obtained by growing epitaxial layer silicon on a silicon base substrate having a surface whose off angle from the (100) plane is 0.2 degrees or less, and (e) the gate 6. The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 5, further comprising a step of forming a gate electrode on the insulating film.
[0055]
(Supplementary Note 7) (a) a step of preparing a silicon substrate having a highly symmetric crystal plane or a surface along the vicinity thereof;
(B) a hydrogen annealing step of annealing the silicon substrate at 900 ° C. to 1050 ° C. for a finite time of 60 seconds or less in an atmosphere containing hydrogen to remove a natural oxide film;
(C) after the step (b), forming a gate insulating film on the surface of the silicon substrate;
A method for manufacturing a semiconductor device including:
[0056]
(Appendix 8)
(D) before the step (c), an annealing step of annealing the silicon substrate in an inert gas atmosphere to cause migration of silicon atoms.
8. The method for manufacturing a semiconductor device according to supplementary note 7, comprising:
[0057]
(Supplementary Note 9) The silicon substrate is an epitaxial substrate having a high resistivity epitaxial layer grown on a low resistivity silicon base substrate, and
(X) forming a shallow trench element isolation region before the step (b);
(Y) after the step (x), performing a chemical treatment on the substrate surface to expose the silicon surface;
(E) after the step (c), forming a gate electrode on the gate insulating film;
(F) forming source / drain impurity-added regions having a junction depth of 0.1 μm or less on both sides of the gate electrode;
9. The method for manufacturing a semiconductor device according to supplementary note 8, comprising:
[0058]
(Supplementary Note 10) A silicon base substrate having a surface whose off angle from a crystal plane having high symmetry is 0.02 degrees or less,
An epitaxial silicon layer formed on the silicon base substrate and having a surface on which terraces and steps have become apparent;
A shallow trench isolation region formed in the epitaxial silicon layer and defining an active region;
A gate insulating film formed on the active region surface;
A gate electrode formed on the gate insulating film;
A source / drain impurity-added region having a junction depth of 0.1 μm or less formed in the active region on both sides of the gate electrode;
A semiconductor device having:
[0059]
(Supplementary Note 11) The method for manufacturing a semiconductor device according to Supplementary Note 6 or 9, wherein the silicon base substrate has a lower resistivity than the epitaxial silicon layer.
(Supplementary Note 12) The semiconductor device according to supplementary note 10, wherein the silicon base substrate has a lower resistivity than the epitaxial silicon layer.
[Brief description of the drawings]
FIG. 1 is a flowchart showing main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view for explaining main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view for explaining main steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view for explaining main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is an AFM image of a surface of a silicon substrate prepared according to an example of the present invention.
FIG. 7 is an AFM image of a surface of a silicon substrate prepared according to an example of the present invention.
FIG. 8 is an AFM image of a surface of a silicon substrate prepared according to an example of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Buffer silicon oxide film 3 Silicon nitride film 4 Resist pattern 6 Trench 7 Silicon oxide film 9 Silicon oxide film 10 Well 11 Gate oxide film 12 Polycrystalline silicon film 15 LDD region 16 Silicon oxide film 17 Silicon nitride film 19 High concentration Source / drain region 20 silicide region

Claims (10)

(A) preparing a silicon substrate having a highly symmetric crystal plane or a surface along the vicinity thereof;
(B) a hydrogen annealing step of annealing the silicon substrate in an atmosphere containing hydrogen to remove a natural oxide film on the silicon surface;
(C) after the step (b), annealing the silicon substrate in an inert gas atmosphere to cause migration of silicon atoms;
(D) after the step (c), forming a gate insulating film on the surface of the silicon substrate;
A method for manufacturing a semiconductor device including: The method according to claim 1, wherein the step (b) is performed at 900 ° C. to 1050 ° C. for a finite time of 60 seconds or less. 3. The method according to claim 1, wherein the step (b) is performed under reduced pressure lower than normal pressure. 4. The method according to claim 1, wherein the step (c) is performed at a temperature of 500 ° C. to 1050 ° C. for a finite time of 60 seconds or less. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) is performed in a He atmosphere. The silicon substrate is an epitaxial substrate obtained by growing an epitaxial layer silicon on a silicon base substrate having a surface having an angle of 0.2 degrees or less from the (100) plane. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a gate electrode. (A) preparing a silicon substrate having a highly symmetric crystal plane or a surface along the vicinity thereof;
(B) a hydrogen annealing step of annealing the silicon substrate at 900 ° C. to 1050 ° C. for a finite time of 60 seconds or less in an atmosphere containing hydrogen to remove a natural oxide film;
(C) after the step (b), forming a gate insulating film on the surface of the silicon substrate;
A method for manufacturing a semiconductor device including: further,
(D) before the step (c), an annealing step of annealing the silicon substrate in an inert gas atmosphere to cause migration of silicon atoms.
8. The method for manufacturing a semiconductor device according to claim 7, comprising: The silicon substrate is an epitaxial substrate having a high resistivity epitaxial layer grown on a low resistivity silicon base substrate;
(X) forming a shallow trench element isolation region before the step (b);
(Y) after the step (x), performing a chemical treatment on the substrate surface to expose the silicon surface;
(E) after the step (c), forming a gate electrode on the gate insulating film;
(F) forming source / drain impurity-added regions having a junction depth of 0.1 μm or less on both sides of the gate electrode;
9. The method for manufacturing a semiconductor device according to claim 8, comprising: A silicon base substrate having a surface whose off angle from a crystal plane having high symmetry is 0.02 degrees or less;
An epitaxial silicon layer formed on the silicon base substrate and having a surface on which terraces and steps are exposed;
A shallow trench isolation region formed in the epitaxial silicon layer and defining an active region;
A gate insulating film formed on the active region surface;
A gate electrode formed on the gate insulating film;
Source / drain impurity doped regions having a junction depth of 0.1 μm or less formed in the active region on both sides of the gate electrode;
A semiconductor device having:

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