JP2000293987A - Read-out method and read-out circuit for ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide read-out method for a ferroelectric memory that a lifetime is long and noise margin can be made large. SOLUTION: Three capacitors C11-C13 having the same value are prepared, an electric field having a negative direction is applied to a ferroelectric capacitor Ca of a memory cell, and data are read out to the first capacitor C11. Next, an electric field having an opposite positive direction is applied. Next, an electric field having a negative direction is applied, electric charges are read out to the second capacitor C12. Next, an electric field having a negative direction is applied, electric charges are read out to the third capacitor C13. And a potential obtained by connecting the second and the third capacitors in parallel is used as a threshold value, and it is compared with a potential read out to the first capacitor, that is, VB1 or VB0 corresponding to a stored value of the ferroelectric capacitor. As VB1 is stored in the second capacitor, VB0 is stored in the third capacitor, by connecting in parallel, as a threshold value is always an intermediate value between VB1 and VB0, a lifetime is prolonged and noise margin is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for accurately reading data stored in a ferroelectric memory.

[0002]

2. Description of the Related Art A ferroelectric memory is a memory using a ferroelectric capacitor as a memory element. The ferroelectric capacitor charges and discharges a ferroelectric capacitor, and stores the state of polarization due to the discharge as storage contents. However, when the ferroelectric capacitor is repeatedly charged and discharged, the polarization gradually weakens and the output decreases. Therefore, if the threshold value for reading out the stored contents is fixed, it is not possible to cope with the fluctuation of the output, and there is a problem that the life is shortened. In order to address this problem, as a readout circuit of a ferroelectric memory of the type in which the threshold value is automatically changed according to the output value, "" Self-reference type readout type 1T / 1C FeRAM "" Junichi Yamada et al., Electronics IEICE Technical Report SDM98-107,
ICD98-106, July 1998 pp. 101-
106 "is disclosed.

FIG. 7 is a circuit diagram of a read circuit of a ferroelectric memory described in the above-mentioned document. One memory cell is composed of one ferroelectric capacitor and one transistor. 1 shows a transistor / one-capacitor type ferroelectric memory. FIG. 8 is a polarization / electric field curve of a ferroelectric for explaining the operation in the circuit of FIG.

In FIG. 7, a cell CE1 and a cell CE2 are memory cells each including one ferroelectric capacitor Ca and one transistor T. Also, B
1, B2 is a bit line, W1, W2 are word lines, PL is a plate line, T1 to T4 are transistors, and SA is a sense amplifier. Further, the capacitances C0 and C1 indicated by broken lines
Is mainly the junction capacitance (source,
It is a stray capacitance composed of the drain junction capacitance) and the input capacitance of the sense amplifier SA, and is designed so that C0 is larger than C1.

In order to read the data of the cell CE1, the charge of the bit lines B1 and B2 is first removed (connected to a predetermined potential, for example, ground) using a precharge means (not shown). Next, the transistor T2 is turned on, the transistors T1, T3, T4 are turned off, and the potentials of the word line W1 and the plate line PL are increased. As a result, the transistor T of the cell CE1 is turned on, and the potential of the plate line PL of the ferroelectric capacitor Ca becomes high, so that a negative electric field is applied to the ferroelectric capacitor Ca (broken line in FIG. 8). In this state, if the data stored in the ferroelectric capacitor Ca is "0", no polarization inversion occurs even when a negative electric field is applied, and the potential rise VB0 of the bit line B1 is small. On the other hand, the ferroelectric capacitor Ca
Is "1", polarization inversion occurs, and the potential rise VB1 of the bit line B1 is large.

Next, after turning off the transistor T2, the potential of the plate line PL is lowered, and the ferroelectric capacitor Ca
Remove the negative electric field applied to. Then, regardless of the data initially stored in the ferroelectric capacitor Ca, "0"
Is written to the ferroelectric capacitor Ca. Next, the transistor T3 is turned on to increase the potential of the plate line PL again. At this time, since no polarization inversion occurs, the bit line B2
Is small. However, at this time, the stray capacitance C1 of the bit line B2 is equal to the stray capacitance C0 of the bit line B1.
Less than. Therefore, Vref is larger than VB0.
Therefore, if the potential of the bit line B1 is higher than the potential of the bit line B2 (VB1> Vref), the data of the cell CE1 is "1", and if the potential of the bit line B1 is lower than the potential of the bit line B2 (Vref> VB0). It can be seen that the data of CE1 was “0”. That is, Vref becomes the threshold value, and VB1 or VB0 is compared with the threshold value. Lastly, the transistor T3 is turned off, the transistor T2 is turned on, and then the potential of the plate line PL is lowered, so that the data initially stored in the cell CE1 is written again to the ferroelectric capacitor Ca of the cell CE1 to recover the data. To complete the data reading.

A broken line in FIG. 8 shows a state transition by application of an electric field. This read circuit has a feature that data can be read without using a dummy cell. In the case of a circuit using a dummy cell, the number of accesses to the dummy cell is larger than that of the memory cell, and as a result, the dummy cell deteriorates quickly. Therefore, a circuit that does not use a dummy cell as described above has a longer life than a circuit that uses a dummy cell.

[0008]

However, the following problem remains in the read circuit of the ferroelectric memory shown in FIG. FIG. 9 is a diagram showing the state of the potentials of the bit lines B1 and B2 of the circuit shown in FIG. The horizontal axis in FIG. 9 indicates the number of read / write cycles, and the vertical axis indicates the potential of the bit line. As can be seen from FIG. 9, Vref is larger than VB0 by a fixed value determined by the stray capacitances C0 and C1, regardless of VB1, and this is the threshold value. Therefore, the ferroelectric capacitor deteriorates in accordance with the repetition of reading and writing, and VB1 gradually decreases to Vref
Is the life of the ferroelectric memory. Also, the difference between Vref and VB1 or VB0 becomes a noise margin when reading data, and if the noise margin is small, the judgment is likely to be erroneous due to noise. As described above, in the conventional example shown in FIG. 7, the life can be made longer than the fixed threshold value, but the life cannot be made long enough to fully utilize the characteristics of the ferroelectric capacitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and further provides a method and circuit for reading out a ferroelectric memory which can have a long life and a large noise margin. With the goal.

[0010]

In order to achieve the above object, the present invention is structured as described in the appended claims. That is, in the first aspect of the present invention, three capacitances having the same value are prepared, and first, an electric field in the first direction (for example, the negative direction) is applied to the ferroelectric capacitor of the memory cell to be read. Data is read out to the first capacitance. Next, an electric field is applied to the ferroelectric capacitor of the memory cell in a second direction (for example, a positive direction) opposite to the data reading. Next, an electric field in a first direction (for example, a negative direction) is applied to the ferroelectric capacitor of the memory cell, and charges flowing when the electric field is applied are read out to a second capacitance. Next, an electric field in the first direction (for example, a negative direction) is again applied to the ferroelectric capacitor of the memory cell, and charges flowing when the electric field is applied are read out to a third capacitance. The potential obtained by connecting the second and third capacitances in parallel is set as a threshold value Vref.
The potential read out to the first capacitance, that is, VB1 or VB0 corresponding to the signal of “1” or “0” stored in the ferroelectric capacitor is compared. The direction of the electric field application may be opposite to the above-described example, in which the first direction is the positive direction and the opposite second direction is the negative direction. By controlling as described above, the second capacitance has a high level VB1.
And the low level VB0 is stored in the third capacitance. By connecting them in parallel, the threshold value Vref is always an intermediate value between the high level VB1 and the low level VB0, that is, Vref = (VB1 + VB0) / 2.
Becomes

Further, in the invention according to claim 2,
Three capacitances having the same value are prepared, and first, an electric field in a first direction (for example, a negative direction) is applied to a ferroelectric capacitor of a memory cell to be read, and data is read out to the first capacitance. Next, the same electric field in the first direction (for example, the negative direction) is again applied, and the charge flowing when the electric field is applied is read out to the second capacitance. Next, an electric field is applied to the ferroelectric capacitor in a second direction (for example, a positive direction) opposite to the data reading. Next, an electric field in the first direction (for example, a negative direction) is again applied to the ferroelectric capacitor, and charges flowing when the electric field is applied are read out to a third capacitance. Finally, the second and third capacitances are connected in parallel, and the potential Vref is compared with VB1 or VB0 read out to the first capacitance. In this case as well, the threshold value Vref is always an intermediate value between the high level VB1 and the low level VB0, that is, Vref = (VB1 + VB0) / 2, so that the noise margin can be maximized. As a result, data reading can be made more resistant to noise, and the reliability of the read data can be increased.

[0012] Claims 3 and 4 show the configuration of a read circuit for realizing the above read method. Claim 3 corresponds to, for example, the circuit of FIG.
Claim 4 corresponds to, for example, the circuit of FIG.

As described in claim 5, each of the first to third capacitances is mainly the first to third (claim 3) or the first to sixth (claim 4). A stray capacitance including a junction capacitance of a transistor and an input capacitance of the first to third sense amplifiers. The three or six transistors and the three sense amplifiers are symmetrically arranged on a substrate with the same structural dimensions. By arranging them, they can have the same value.

[0014]

According to the present invention, since the threshold Vref is always set to an intermediate value between the high level VB1 and the low level VB0, the noise margin can always be maximized. And the reliability of the read data can be improved. In addition, even if the ferroelectric capacitor constituting the memory cell is deteriorated due to the use, the life can be extended as much as possible according to the characteristics.

[0015]

FIG. 1 is a circuit diagram of a first embodiment of the present invention. To explain the configuration, the cell CE1 is composed of one ferroelectric capacitor Ca and one transistor T
Is a memory cell constituted by Although a plurality of similar memory cells are actually arranged, only one cell indicated by CE1 is shown here as an example. These memory cells are connected to a data reading unit via a bit line B1 and a row selecting transistor T1. The input stage of the data reading unit has three transistors T11,
T12 and T13, each of which has three sense amplifiers SA1 and S1 as shown in FIG.
A2 and SA3. And the transistor T
11, T12, and T13, each sense amplifier SA
Capacitors C11, C12, and C13 indicated by broken lines are formed in portions connected to the inputs of SA1, SA2, and SA3. These capacitances mainly depend on the transistors T11 to T11.
13 are stray capacitances composed of 13 junction capacitances (junction capacitances of source and drain) and input capacitances of the sense amplifiers SA1 to SA3, but are collectively shown at one place as shown. Therefore, if the transistors T11 to T13 have the same size and the sense amplifiers SA1 to SA3 have the same configuration and size and are arranged symmetrically on the substrate, the values of the capacitances C11 to C13 will be symmetrical in the figure. As can be seen from FIG. 6, the sizes are almost the same (C11 = C12 = C13). One end of the bit line B1 is connected to a high power supply (for example, Vcc) and a low power supply (for example, ground) via two transistors TH1 and TL1 for initialization.

Next, a method of reading data will be described. FIG. 2 is a diagram showing a polarization / electric field curve of the ferroelectric capacitor, and a broken line shows a state transition by application of an electric field. In FIG. 1, first, the transistor TH1 is turned off, and the transistors T1, T11, and TL1 are turned on, and the potentials of the bit line B1 and the capacitance C11 are initialized to “low”. Next, the transistor TL1 is turned off, and the transistor T1 is turned off.
1. Turn on T11 and set word line W1 and plate line PL to "high". Then the ferroelectric capacitor Ca
Is applied with a negative electric field, and a state transition as shown by a broken line in FIG. 2 occurs. With this state transition, electric charge is accumulated in the capacitance C11, and the electric potential is VB1 when the data stored in the cell CE1 is "1" and V when the data stored in the cell CE1 is "0".
It becomes B0.

Next, the transistor T11 is turned off, the transistor TH1 is turned on, and the plate line PL is set to "low". Then, a positive electric field is applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 2 occurs.
Next, the transistor TH1 is turned off, the word line W1 is turned "low", the transistors T12, T13 and the transistor TL1 are turned on, and the bit line B1, the capacitance C12
And the potential of C13 is initialized to “low”.

Next, the transistors TL1 and T13 are turned off again, T12 is turned on, and the word line W1 and the plate line P are turned off.
L is set to “high”. Then, a negative electric field is applied again to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 2 occurs. With this state transition, the capacitance C12
, And its potential becomes VB1.

Next, the transistor T12 is turned off, and the plate line PL is set to "low". Subsequently, the transistor T13
Is turned on, and the plate line PL is set to “high”. Then, a negative electric field is again applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 2 occurs. With this state transition, electric charge is accumulated in the capacitance C13, and the electric potential becomes VB
It becomes 0.

Next, the transistor T1 is turned off, and T12 and T13 are turned on. This allows the capacitances C12 and C12
13 are connected in parallel, and the potential thereof is (VB1 + VB0) /
It becomes 2. This potential is compared with the potential of the capacitance C11 as the threshold value Vref. That is, the potential of the capacitance C11 is applied to the + input terminal of the sense amplifier SA1, and the above-described threshold value Vref is applied to the-input terminal. Therefore, when the data stored in the cell CE1 is "1", the output of the sense amplifier SA1 is "high", and when the data is "0", it is "low".

Finally, after turning off the transistors T12 and T13 and turning on T11 and T1, the plate line PL
Lowering the potential of the cell CE1, the data initially stored in the cell CE1 is transferred to the ferroelectric capacitor Ca of the cell CE1.
When the data is written again and the data is restored, the data reading is completed.

As can be seen from the above description, in the circuit of the present embodiment, Vref = (VB1 + VB
0) / 2 holds, and the median between the high level VB1 and the low level VB0 automatically becomes the threshold value Vref. Therefore, the noise margin can be maximized, and as a result, data reading can be made strong against noise, and the reliability of the read data can be increased.

FIG. 3 shows the high level V in this embodiment.
FIG. 9 is a characteristic diagram showing the dependency of B1, low level VB0, and threshold value Vref on the number of read / write cycles. As can be seen from FIG. 3, even if the ferroelectric capacitor of the cell deteriorates as the number of cycles increases, the noise margin always becomes the maximum value at that time, and the reliability of the read data becomes the highest at that time. Get higher. Also, since the intersection of Vref and VB1 coincides with the intersection of VB1 and VB0, the longest life can be achieved in conformity with the characteristics of the ferroelectric capacitor. Compared with the characteristics shown in FIG. 9, the present invention clearly has a longer life.

FIG. 4 is a diagram showing a polarization / electric field curve of the ferroelectric capacitor according to the second embodiment of the present invention, in which a state transition by application of an electric field is shown by a broken line.

The circuit used in the second embodiment is the same as that of FIG. 1, but the order of the state transitions due to the application of the electric field is different.

Hereinafter, description will be made with reference to the circuit of FIG. 1 and FIG. First, the transistor TH1 is turned off, the transistors T1, T11, T13, and TL1 are turned on, and the potentials of the bit line B1, the capacitances C11 and C13 are set to "low".
Initialize to Next, the transistors T13 and TL1 are turned off, the transistors T1 and T11 are turned on, and the word line W1 and the plate line PL are set to "high". Then, a negative electric field is applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 4 occurs. With this state transition, electric charge is accumulated in the capacitance C11, and its potential becomes VB1 when the data stored in the cell CE1 is "1" and VB0 when the data stored in the cell CE1 is "0".

Next, the transistor T11 is turned off, and the plate line PL is set to "low". Subsequently, the transistor T13
Is turned on, and the plate line PL is set to “high”. Then, a negative electric field is again applied to the ferroelectric capacitor Ca, and a state transition occurs as shown by a broken line in FIG. With this state transition, electric charge is accumulated in the capacitance C13, and the electric potential becomes VB
It becomes 0. Next, the transistor T13 is turned off, the transistor TH1 is turned on, and the plate line PL is set to "low".
Then, a positive electric field is applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 4 occurs. Next, the transistor TH1 is turned off, the word line W1 is turned "low", and the transistors T12 and TL1 are turned on to initialize the potential of the capacitance C12 to "low".

Next, the transistor TL1 is turned off again, the transistor T12 is turned on, and the word line W1 and the plate line P are turned off.
L is set to “high”. Then, a negative electric field is applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 4 occurs. With this state transition, electric charges are accumulated in the capacitance C12, and the electric potential becomes VB1. Next, the transistor T1 is turned off, and T12 and T13 are turned on. As a result, the capacitances C12 and C13 are connected in parallel, and the potential Vref becomes (VB1 + VB0) / 2. Therefore, as in the case of FIG. 2, the output of the sense amplifier SA1 becomes "high" when the data stored in the cell CE1 is "1" and becomes "low" when the data stored in the cell CE1 is "0". Lastly, the transistors T12 and T13 are turned off, T11 and T1 are turned on, and then the potential of the plate line PL is lowered, so that the data initially stored in the cell CE1 is again written to the ferroelectric capacitor Ca of the cell CE1. When the data is returned to the original state, the data reading is completed.

As described above, even if the order of applying the electric fields in the opposite direction (positive direction in the above case) and the electric field at the time of reading (negative direction in the above case) are different, the same as in FIG. The effect is obtained.

In the circuit shown in FIG. 1, the case where one cell CE1 and one bit line B1 are shown as an example, but in an actual ferroelectric memory, many cells are connected to each other. And a bit line, and one read circuit can be shared by the plurality of cells. The circuit shown in FIG. 1 shows a basic configuration using three sense amplifiers to maintain symmetry. Generally, one sense amplifier is provided for each bit line in order to increase the signal processing speed. If provided, as shown in FIG.
The bit lines B1, B2, and B3 are connected, and a signal when each bit line is read is sent to the sense amplifier SA.
1, SA2, and SA3. In this case, the on / off control of the transistors T11, T12, and T13 described in the method of reading data changes in order according to which of the bit lines B1, B2, and B3 is read. For example, when a signal read from the bit line B2 is output from the sense amplifier SA2, the transistors T1, T11, T12, T13, and T13 described in the above-described method of reading data are described as T1 and T13, respectively.
It should be read as 1. When the signal read from the bit line B3 is output from the sense amplifier SA3, the transistors T1, T11, T12, and T13 described above in the method of reading data are described as T1 and T13, respectively.
It should be read as 2. When the number of bit lines is further increased, the number of transistors and sense amplifiers may be increased accordingly.

When the signal processing speed may be slightly reduced, more bit lines than the number of sense amplifiers may be connected for processing. For example, as shown in FIG. 5, a read circuit including three sense amplifiers includes 9 of B1 to B9.
B1 → SA1, B2 → SA2,
B3 → SA3, B4 → SA1, B5 → SA2, B6 → S
A3, B7-> SA1, B8-> SA2, B9-> SA3, the sense amplifiers can be overlapped and sequentially repeated to output the read result.

Next, a third embodiment of the present invention will be described. In the circuits shown in FIGS. 1 and 5, each of the sense amplifiers SA1
SA3 are not symmetrically connected to the input terminals of each sense amplifier. That is, the transistor T
11 is connected to the + terminals of the sense amplifiers SA1 and SA2, the connection line from the transistor T12 is connected to the-terminal of the sense amplifier SA1 and the + terminal of SA3,
The connection line from the transistor T13 is connected to the sense amplifier SA2.
And SA3 are connected to the-terminal. When the terminals are asymmetrically connected to the positive terminal and the negative terminal of the sense amplifier as described above, the capacitances C11, C12, C
There may be some differences in the value of 13. In the third embodiment, the imbalance that occurs in the capacitance as described above is eliminated.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention. In this circuit, the transistors T1 and T2 used in FIGS. 1 and 5 are eliminated, and instead, six transistors T1 are connected to both the + and-input terminals of each sense amplifier SA.
1, T12, T13, T21, T22 and T23 are arranged. The transistors T11, T12, and T13 are all connected to the + terminals of the sense amplifiers SA1, SA2, and SA3, and the transistors T21, T22, and T23 are all connected to the-terminals of the sense amplifiers SA1, SA2, and SA3. The capacitance consisting of the junction capacitance of each of these transistors and the input capacitance of each sense amplifier is represented by C11, C1.
2, C13, C21, C22, and C23. And +
Transistors T11, T12, T connected to terminals
13 and one of the transistors T21, T22, and T23 connected to the-terminal, respectively, to form three sets of combinations, and the transistors in each set operate synchronously (ON). , Off)
The six capacitances are connected in parallel two by two, and each of the three sets becomes three capacitances equivalently connected one by one. For example, if the transistors T11 and T21, T12 and T22, and T13 and T23 are respectively combined, C
Three sets of capacitances of 11 + C21, C12 + C22, and C13 + C23 are formed. With the connection as described above, the connection of the input terminals of each sense amplifier is symmetrical, and there is no possibility that the capacitances become unbalanced. Note that, in this case as well, the transistors T11, T12, T13, T2
1, T22 and T23 have the same size, and the sense amplifier S
If A1 to SA3 have the same configuration and size and are symmetrically arranged on the substrate, three sets of electrostatic capacitances C11 + C21, C12 + C22 composed of the junction capacitance of each transistor and the input capacitance of each sense amplifier can be obtained from the symmetry of the drawing. C13 + C23
Are equal to each other. 6, the same reference numerals as those in FIG. 1 denote the same components. Also, a large number of cells can be connected as in FIG.

Hereinafter, an example of a data reading method in the circuit of FIG. 6 will be described. First, in order to change the state as shown in FIG. 2, the transistor TH1 is turned off,
The transistors T11, T21 and TL1 are turned on to initialize the potentials of the capacitances C11 and C21 to "low".

Next, the transistor TL1 is turned off and T1
1. Turn on T21 and set word line W1 and plate line PL to "high". Then, a negative electric field is applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 2 occurs. With this state transition, the capacitances C11 and C2
1 accumulates electric charge. The potential becomes VB1 when the data stored in the cell CE1 is "1", and becomes VB0 when the data is "0".

Next, the transistors T11 and T21 are turned off, TH1 is turned on, and the plate line PL is set to "low".
Then, a positive electric field is applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 2 occurs.

Next, the transistor TH1 is turned off, the word line W1 is turned "low", and the transistors T12, T22,
Turn on T13, T23 and TL1 to set the capacitance C1
2. The potentials of C22, C13 and C23 are initialized to "low". Next, the transistors TL1, T13, T
23 is turned off, T12 and T22 are turned on, and the word line W1 and the plate line PL are set to "high". Then, a negative electric field is applied again to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 2 occurs. With this state transition, electric charges are accumulated in the capacitances C12 and C22, and the electric potential is VB
It becomes 1.

Next, the transistors T12 and T22 are turned off, and the plate line PL is set to "low". Subsequently, the transistors T13 and T23 are turned on, and the plate line PL is set to "high".
To Then, a negative electric field is applied to the ferroelectric capacitor Ca, and a state transition as shown by a broken line in FIG. 2 occurs.
With this state transition, electric charges are accumulated in the capacitances C13 and C23, and the potential becomes VB0. Next, the transistors T12, T22, T13 and T23 are turned on. As a result, the capacitances C12 and C22 are connected in parallel with C13 and C23, and the potential Vref is (VB1 + VB0) /
It becomes 2. Therefore, the output of the sense amplifier SA1 is
When the data stored in the cell CE1 is "1", it becomes "high", and when it is "0", it becomes "mouth".

Finally, the transistors T12, T22, T
13. By turning off T23 and turning on T11 and then lowering the potential of the plate line PL, the data initially stored in the cell CE1 can be rewritten to the ferroelectric capacitor Ca of the cell CE1 to restore the data. In this case, the data reading is completed.

In the above description, the case of performing the reading shown in FIG. 2 using the circuit of FIG. 6 has been described.
The reading as shown in FIG. 4 can be performed by using the circuit of FIG. Also, in the circuit of FIG. 6, the read circuit can be shared by a plurality of cells as described with reference to FIG. Specifically, the input terminals (T11 to T11) of the reading unit
Each bit line may be connected to a portion where the left terminals of T13 and T21 to T23 are commonly connected). In this case, the on / off control of each transistor is sequentially changed in accordance with the bit line to be read, as described in FIG.

In the above description, the electric field in the positive and negative directions is changed by switching the potential of the plate line PL between "high" and "low".
The case where it is configured to apply the voltage to a is illustrated. But,
In addition, the potential of the plate line PL is fixed at Vcc / 2, and the potential of the bit line is switched between “high” and “low” (for example, Vcc and 0) to change the electric field in the positive and negative directions to ferroelectricity. It can also be applied to the body capacitor Ca. Even in this case, each embodiment of the present invention described above can be applied.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating one embodiment of the present invention.

FIG. 2 is a diagram showing a polarization / electric field curve of a ferroelectric capacitor for explaining a reading method of the present invention.

FIG. 3 shows a high level VB1 and a low level VB according to the present invention.
FIG. 4 is a characteristic diagram showing the dependence of the threshold value Vref on the number of read / write cycles.

FIG. 4 is a view showing a polarization / electric field curve of a ferroelectric capacitor for explaining another reading method of the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a circuit diagram showing still another embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional example.

FIG. 8 is a diagram showing a polarization / electric field curve of a ferroelectric capacitor for explaining a reading method in a conventional example.

FIG. 9 shows a high level VB1 and a low level VB in a conventional example.
FIG. 4 is a characteristic diagram showing the dependence of the threshold value Vref on the number of read / write cycles.

[Explanation of symbols]

CE1 to CE3: a memory cell Ca: a ferroelectric capacitor in a memory cell T: a transistor in a memory cell T1 to T3: a transistor for selecting a row T11, T12, T13, T21, T22, T23: a transistor SA1, SA2, SA3 ... Sense amplifiers C0, C1, C11, C12, C13, C21, C2
2, C23 ... Capacitance TH1 to TH3 ... Transistor TL1 to TL3 ... Transistor B1 to B3 ... Bit line PL ... Plate line W1 to W3 ... Word line

Claims (5)

[Claims] 1. A reading method for a ferroelectric memory having a plurality of memory cells each constituted by one ferroelectric capacitor and one transistor, wherein the first, second, and third capacitances have the same value. And applying an electric field in a first direction to the ferroelectric capacitor via the transistor constituting a memory cell to be read,
Storing an electric charge flowing when an electric field is applied to the first capacitance;
Next, the applied electric field is reversed in the opposite second direction, then the applied electric field is removed, and then the electric field in the first direction is applied again, and then the applied electric field is removed. An electric field in the first direction is applied once more to the second capacitance, the electric charge flowing when the electric field is applied is stored in the third capacitance, and then the second and third capacitances are stored. A method for reading out a ferroelectric memory, comprising comparing a potential obtained by parallel connection with a potential of the first capacitance as a threshold value. 2. A reading method for a ferroelectric memory having a plurality of memory cells each constituted by one ferroelectric capacitor and one transistor, wherein the first, second, and third capacitances have the same value. And applying an electric field in a first direction to the ferroelectric capacitor via the transistor constituting a memory cell to be read,
Storing an electric charge flowing when an electric field is applied to the first capacitance;
Next, the electric field in the first direction is applied again, the electric charge flowing when the electric field is applied is stored in the second capacitance, and then the applied electric field is inverted in the opposite second direction, and then the applied electric field is removed. Then, the electric field in the first direction is applied once more, the electric charge flowing when the electric field is applied is stored in a third capacitance, and the electric potential obtained by connecting the second and third capacitances in parallel is obtained. A reading method for a ferroelectric memory, wherein the threshold value is compared with a potential of the first capacitance. 3. A semiconductor device comprising: first to third three sense amplifiers having the same structure and the same size; and first to third three transistors having the same structure and the same size. A terminal is connected to one input terminal of the first and second sense amplifiers, and one terminal of the second transistor is connected to the other input terminal of the first sense amplifier and one input terminal of the third sense amplifier. By connecting to an input terminal and connecting one terminal of the third transistor to the other input terminal of the second and third sense amplifiers, two input terminals are provided for each of the sense amplifiers, for a total of six By connecting two input terminals from one terminal of each of the transistors to two input terminals, and forming a state in which capacitance is equivalently connected to each of the three terminals of the three transistors, First to third three And the other terminals of the three transistors are connected in common to serve as input terminals of a read unit, and one end of each of a plurality of bit lines connected to a memory cell is connected to a seventh transistor. Wherein the other end of the bit line is connected to a high power supply and a low power supply via eighth and ninth transistors, respectively. Readout circuit. 4. A semiconductor device comprising: first to third three sense amplifiers having the same structure and the same size; and first to sixth six transistors having the same structure and the same size. One terminal is connected to one input terminal of the first sense amplifier, one terminal of the second transistor is connected to one input terminal of the second sense amplifier, and one terminal of the third transistor is connected. To one input terminal of the third sense amplifier, from one terminal of the fourth transistor to the other input terminal of the second sense amplifier, and from one terminal of the fifth transistor to the By connecting to the other input terminal of the third sense amplifier and connecting from one terminal of the sixth transistor to the other input terminal of the first sense amplifier, two transistors are provided for each of the three sense amplifiers. Entering A total of six input terminals are connected to one input terminal from each one terminal of the six transistors, and a capacitance is equivalently connected to each one terminal of the six transistors. And forming one of the first to third three transistors and one of the fourth to sixth three transistors to form three sets of combinations. , By operating the transistors in each set in synchronization, the first to third three capacitances which are equivalently connected one by one to each of the three sets are formed; The other terminals of the transistors are connected in common to serve as input terminals of a read unit, and one ends of a plurality of bit lines connected to memory cells are connected to the input terminals of the read unit. Of the 8th and 9th respectively
A reading circuit for a ferroelectric memory, wherein the reading circuit is connected to a high power supply and a low power supply via the transistor. 5. The first to third capacitances mainly include a junction capacitance of the first to third or first to sixth transistors and an input capacitance of the first to third sense amplifiers. And formed so that the three or six transistors and the three sense amplifiers have the same value by mutually symmetrically arranging them on the substrate with the same structural dimensions. The read circuit of the ferroelectric memory according to claim 3 or 4, wherein: