JP2000286390A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obviate high-accuracy alignment for irradiation with light and enable operation mode change in real time, by adding a test circuit provided with a state machine which changes the plurality of operation modes of an internal circuit through control of mode setting signals with a pulse width corresponding to the time of irradiation with light. SOLUTION: A photoelectric conversion element 12 consists of a transistor which is turned on/off in correspondence with irradiation/non-irradiation with light and the source, drain, and non-active gate of the NMOS 18 are connected between ground GND and a current-voltage conversion circuit 14. In addition to the NMOS, a p-type MOS transistor may be used as the photoelectric conversion element 12 and a combination of both may be adopted. Subsequently, the current-voltage conversion circuit 14 converts current passed between a power supply Vcc and the ground GND into voltage through the photoelectric conversion element 12 and produces a mode setting signal MODE. Further, a test circuit containing a state machine 16 is provided, which state machine produces operation mode signals for changing the operation mode of the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a test circuit for switching an operation mode of an internal circuit depending on irradiation / non-irradiation of light.

[0002]

2. Description of the Related Art In a conventional test circuit, for example, a mode switching pin is provided as an external terminal of a semiconductor device, and an operation mode signal supplied through the mode switching pin causes
Switching the operation mode of the internal circuit. The mode switching pins are provided in a predetermined number according to the number of operation modes of the internal circuit. For example, there are cases where the mode switching pins are provided as dedicated pins, but provided in order to realize the original normal operation of the semiconductor device. Often shared with a user pin.

Here, the operation mode is, as described above,
This means, for example, a test mode or a debug mode in addition to a normal operation mode for executing a normal operation which is an original function of the semiconductor device. The test mode is GO (go)
/ NG (No Go) is an operation mode for efficiently testing the operation of each internal block, and the debug mode is an operation for diagnosing which part of the internal circuit has a failure / malfunction. Mode.

The operation modes include a simple function mode in addition to the various operation modes described above. The simple function mode is not an operation mode for diagnosing an operation failure of only a semiconductor device, but by, for example, mounting a semiconductor device on a printed board and performing system operation of the entire device mounted on the printed board. This is an operation mode for diagnosing the quality of operation of a system in which a semiconductor device is actually mounted.

In a semiconductor device on which a test circuit is mounted, various tests are performed by appropriately switching the operation mode described above, and the operation is verified. However, there is a problem that the number of external terminals increases when an external terminal dedicated to the mode switching pin is provided, and when the mode switching pin is shared with the user pin, for example, if the user pin is an output-only pin, Since it is necessary to redesign as a bidirectional pin, it is a hotbed where design errors occur.

When the printed board is designed to operate only in the normal operation mode, after the semiconductor device is mounted on the printed board, the operation verification of the semiconductor device may be performed by switching the operation mode of the semiconductor device. I ca n’t,
Conversely, even after mounting a semiconductor device on a printed board, it is necessary to redesign the printed board so that various operation modes can be switched and the operation can be verified. However, there is a problem that the number increases.

As one method for solving such a problem, for example, there is a test method for a semiconductor integrated circuit device disclosed in Japanese Patent Publication No. 6-52751.

In the test method for a semiconductor integrated circuit device disclosed in the publication, as shown in FIG. 9, a photoelectric sensor sensitive to externally applied light is provided for each signal holding circuit 54 included in an internal circuit of the semiconductor integrated circuit device. A signal for testing the function of an internal circuit at a connection point between the conversion element 56, a diode as a specific example thereof, and a resistance element 58 connected in series with the diode when the photoelectric conversion element receives light. Is generated in advance.

In this test method, one laser generating means externally generates a photoelectric conversion element corresponding to a desired signal holding circuit in an internal circuit while bringing a test terminal probe into contact with an output terminal pad. The laser beam is deflected by the optical deflecting means and irradiated sequentially, and the corresponding signal holding circuit is forcibly set or reset to monitor the electric signal of the output terminal pad, thereby performing a function test of the internal circuit. Done.

However, the test signal generator disclosed in the above publication merely sets the corresponding signal holding circuit to a high level or resets it to a low level, and once the signal holding circuit is reset, Unless the power is turned off, it can not be set again, it can not switch between set / reset in real time,
In order to set a plurality of operation modes, there is a problem that a plurality of test signal generators are required.

Further, since the test signal generating section is formed close to each signal holding circuit, the position of the laser generating means is moved and aligned for sequentially setting / resetting each signal holding circuit. It is necessary and very troublesome, and when multiple signal holding circuits are arranged close to each other, extremely high alignment accuracy is required when irradiating light to the photoelectric conversion elements of each test signal generator. There was also a problem that was required.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which does not require a high positioning accuracy for light irradiation and can switch the operation mode in real time, in view of the problems based on the prior art. Is to provide. Another object of the present invention is to provide a semiconductor device capable of verifying the operation of a pudding including a semiconductor device and the entire system on a board even after mounting on the printed board without redesigning the printed board. It is to provide a device.

[0013]

In order to achieve the above object, the present invention comprises a transistor whose gate is connected to an inactive state potential and which is turned on / off in response to light irradiation / non-light irradiation. A photoelectric conversion element, a current-voltage conversion circuit that converts a current flowing between a power supply and ground through the photoelectric conversion element into a voltage, and generates a mode setting signal having a pulse width corresponding to the light irradiation time, According to another aspect of the present invention, there is provided a semiconductor device including a test circuit including a state machine that generates an operation mode signal for switching a plurality of operation modes of an internal circuit by controlling the mode setting signal.

Here, the semiconductor device is preferably sealed in a package having a window with a filter through which only light of a specific frequency can pass.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 is a conceptual diagram showing the configuration of an embodiment of a semiconductor device according to the present invention. The semiconductor device 10 shown in FIG. 1 includes a photoelectric conversion element 12 including an N-type MOS transistor (hereinafter, referred to as an NMOS) 18, a current-voltage conversion circuit 14 for generating a mode setting signal MODE, and a mode setting signal MOD.
A test circuit having a state machine 16 that generates an operation mode signal for switching an operation mode of an internal circuit (not shown) under the control of E is mounted.

First, the photoelectric conversion element 12 is composed of a transistor which is turned on / off in response to light irradiation / non-light irradiation. Both ends (source and drain) of the NMOS 18 in the illustrated example are connected to the ground GND and the current. Voltage conversion circuit 1
4 and its gate is connected to ground GND which is in an inactive state. In addition, as the photoelectric conversion element 12, a P-type MOS transistor (hereinafter, referred to as a PMOS) may be used in addition to the NMOS, or both may be combined.

Subsequently, the current-voltage conversion circuit 14 converts the current flowing between the power supply Vcc and the ground GND through the photoelectric conversion element 12 into a voltage, and converts the current to the mode setting signal MOD.
E is generated. Note that the current-voltage conversion circuit 14 may be a circuit having any configuration as long as it realizes the above-described functions. For example, a resistor element may be used as the simplest configuration. It is preferable to use a combination of the above and the like with high accuracy.

FIGS. 2 and 4 are circuit diagrams showing one embodiment of the photoelectric conversion element 12 and the current-voltage conversion circuit 14. FIG. First, the circuit shown in FIG. 2 shows the photoelectric conversion element 12 shown in FIG. 1 and an equalizer 14a which is a part of the current-voltage conversion circuit 14. Photoelectric conversion element 12
Has a PMOS 20 and an NMOS 22, and the equalizer 14a includes three NMOSs 24, 26, and 28,
OS30.

Both ends of the PMOS 20 of the photoelectric conversion element 12 are connected between the power supply and the signal A2, and the gate thereof is connected to the power supply in an inactive state. Also, NMO
Both ends of S22 are connected between the ground and the signal A1,
The gate is connected to the inactive ground.

The equalizer 14a equalizes the potentials of the signals A1 and A2.
2 and the power supply, and similarly, both ends of the NMOS 26 are connected between the signal A1 and the power supply. Also, N
Both ends of the MOS 28 and the PMOS 30 have the signal A
1 and A2. NMOS 24, 2
Each of the gates 6 and 28 is connected to a power supply, and a PMOS
The gate of 30 is connected to the ground which becomes active.

In the circuit of the illustrated example, when light is not irradiated, the PMOS 20 and NM
OS22 is off, NMOS of equalizer 14a
24, 26, and 28 and the PMOS 30 are all on, and the signals A1 and A2 are charged up to the same constant potential, in this embodiment, Vcc- _VthN ( _VthN is the threshold value of the NMOS). .

As shown in the graph of FIG. 3, when light is irradiated, the PMOS 20 and NMOS
22 is turned on, and the potentials of the signals A1 and A2 are
Discharged via 22. At this time, the signal A1
Is discharged via the NMOS 22, and the potential of the signal A2 is charged up via the PMOS 20, so that the potential of the signal A1 is discharged relatively quickly and lower than the potential of the signal A2. A small potential difference occurs.

Thereafter, when the light irradiation is stopped, the PMOS 20 and the NMOS 22 of the photoelectric conversion element 12 are turned off again, and the potentials of the signals A1 and A2 are changed to the equalizer 14a.
Are charged up to the pre-change potential via NMOSs 24 and 26 of NMOS 28 and PMOS 3
The potential is made the same through 0.

Next, the circuit shown in FIG. 4 is a current mirror type sense amplifier (hereinafter simply referred to as a sense amplifier) 14b which is a part of the current-voltage conversion circuit 14 shown in FIG. The sense amplifier 14b detects a minute potential difference generated between the signals A1 and A2 and amplifies and outputs the difference. The PMOSs 32 and 34 which are current mirror loads are used.
And NM for inputting signals A1 and A2 that cause a minute potential difference
OSs 36 and 38 and an NMOS 40 serving as a constant current source are provided.

The sources of the PMOSs 32 and 34 are connected to the power supply, the gates are both connected to the drain of the PMOS 32, and the drain of the PMOS 34 is connected to the mode setting signal MODE. Also, NMOSs 36 and 38
Are connected to the signals A1 and A2, the drains are connected to the drains of the PMOSs 34 and 32, respectively, and the source is connected to the drain of the NMOS 40. The source of the NMOS 40 is connected to the ground, and the gate is connected to a power supply in an active state.

When the signals A1 and A2 are at the same power supply potential, the NMOSs 36 and 38 are on and the NMOS 40 is always on, so that the gate potentials of the PMOSs 32 and 34 are similarly set via the NMOSs 38 and 40 to set the mode. The potential of the signal MODE is discharged via the NMOSs 36 and 40. Therefore, the PMOSs 32 and 34 are also turned on, and the potential of the mode setting signal MODE becomes
The potential becomes a predetermined low potential determined by the division of the on-resistance between S32 and S34 and the NMOSs 36, 38 and 40.

As shown in the graph of FIG. 5, when light is applied, the potential of the signal A1 drops faster than the potential of the signal A2, and when a small potential difference occurs between the two, the NMOS 38
The on-resistance value of the NMOS 36 is larger than that of the NMOS 36, and N
Since the current driving capability of the NMOS 36 is smaller than that of the MOS 38, the potential of the mode setting signal MODE increases,
The potential becomes a predetermined high potential determined by the division of the on-resistance between the PMOS 32, 34 and the NMOS 36, 38, 40.

Thereafter, when the light irradiation is stopped, the signal A
1 and A2 have the same potential, and the NMOSs 36, 3
8 have the same current driving capability, and the mode setting signal MOD
The potential of E drops, and the PMOS 32, 34 and NMOS
A predetermined low potential is determined by the division of the on-resistance between 36, 38 and 40. As described above, the mode setting signal MOD having the pulse width corresponding to the light irradiation time
E is generated.

Next, the state machine 16 will be described. FIG. 6 is a configuration circuit diagram of one embodiment of the state machine. The state machine 16 in the illustrated example controls the operation mode signals Q1, Q2, and Q2 for switching a plurality of operation modes of an internal circuit (not shown) by controlling the mode setting signal MODE.
Q3 is generated. In the illustrated example, a shift register including three flip-flops 42, 44, and 46 is illustrated.

A mode setting signal MODE and a reset signal RESET are commonly input to clock terminals and preset terminals of the flip-flops 42, 44, 46, respectively. The D terminal of the flip-flop 42 is connected to the ground GND, and the Q terminal outputs the operation mode signal Q1. Similarly, flip-flop 4
Operation mode signals Q1 and Q4 are connected to D terminals 4 and 46, respectively.
Q2 is input, and operation mode signals Q2 and Q3 are output from the Q terminal, respectively.

As shown in the timing chart of FIG.
First, when the reset signal RESET is set to the low level, all the flip-flops 42, 44, and 46 are preset, and the operation mode signals Q1 to Q3, which are outputs thereof, are initialized to the high level. After the reset signal RESET is set to the high level, the potential of the ground GND is shifted in synchronization with the rise of the mode setting signal MODE, and the operation mode signals Q1, Q2, Q3 are sequentially set to the low level.

The specific circuit configuration of the state machine 16 is not limited as long as it generates a plurality of operation mode signals, such as a counter, in addition to the shift register in the illustrated example. Any of the conventionally known test mode generating circuits that switch the operation mode by controlling one signal supplied via the mode switching pin of the external terminal can be applied. Also, the reset signal R
ESET may use, for example, a signal for initializing the semiconductor device 10.

The semiconductor device to which the present invention is applied is basically as described above. Next, a method for switching the operation mode of the semiconductor device of the present invention will be described.

In the present invention, for example, as shown in FIG.
A light irradiation device 48 such as a laser beam is positioned at a position corresponding to the test circuit shown in FIG. If the semiconductor device 10 of the present invention is sealed in a package having a window 50 with a filter through which only light of a specific frequency can pass, as shown in FIG. Irradiation of light to the vicinity of the conversion element 12 is possible.

By irradiating / non-irradiating the light, the photoelectric conversion element 12 is turned on / off, and a small potential difference is generated between the signals A1 and A2 of the equalizer 14a. This signal A
The minute potential difference between A1 and A2 is detected by the sense amplifier 14b and amplified and output as a mode setting signal MODE. In the state machine 16, the state of the operation mode signals Q1 to Q3 is appropriately set by controlling the mode setting signal MODE, and the operation mode of the internal circuit is determined accordingly.

The semiconductor device of the present invention is basically as described above. As described above, the semiconductor device of the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. .

[0038]

As described in detail above, the semiconductor device of the present invention, as a photoelectric conversion element, has its gate connected to a potential in an inactive state, and is turned on / off in response to light irradiation / non-irradiation. A transistor that converts the current flowing between the power supply and the ground through the photoelectric conversion element into a voltage, generates a mode setting signal having a pulse width corresponding to the light irradiation time, and generates a mode setting signal of the mode setting signal. By control
An operation mode signal for switching a plurality of operation modes of the internal circuit is generated. Therefore, according to the semiconductor device of the present invention, without requiring the mode switching pin,
Various operation modes can be switched in real time, and of course, since there is only one portion to be irradiated with light, the semiconductor device and the light irradiation device need to be positioned only once, and alignment is easy. There is an advantage. Further, according to the semiconductor device of the present invention, since the semiconductor device is sealed in a package having a window with a filter through which only light of a specific frequency can pass, even after mounting the semiconductor device on a printed board, The operation mode of the semiconductor device can be verified by switching to the operation mode, the design of the printed board can be simplified, and the semiconductor device is included on-site even after the printed board is supplied to the user. The operation of the entire print board can be debugged.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a configuration of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a partial configuration circuit diagram of an embodiment of the semiconductor device of the present invention.

FIG. 3 is a graph of an example showing the operation of the circuit shown in FIG. 2;

FIG. 4 is a partial circuit diagram of another embodiment of the semiconductor device of the present invention.

FIG. 5 is a graph of an example showing the operation of the circuit shown in FIG.

FIG. 6 is a configuration circuit diagram of an embodiment of a state machine.

FIG. 7 is a timing chart of one embodiment showing the operation of the circuit shown in FIG. 6;

FIGS. 8A and 8B are conceptual diagrams of one embodiment showing how to switch the operation mode of the semiconductor device of the present invention.

FIG. 9 is a conceptual diagram of one embodiment of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 10 semiconductor device 12, 56 photoelectric conversion element 14 current / voltage conversion circuit 14a equalizer 14b current mirror type sense amplifier 16 state machine 18, 22, 24, 26, 28, 36, 38, 40N
Type MOS transistor 20, 30, 32, 34 P-type MOS transistor 42, 44, 46 flip-flop 48 light irradiation device 50 window 52 print board 54 signal holding circuit 58 resistance element

Claims (2)

[Claims] 1. A photoelectric conversion element having a gate connected to a potential in an inactive state and turned on / off in response to light irradiation / non-irradiation, and a power supply and a ground via the photoelectric conversion element. A current-to-voltage conversion circuit that converts a current flowing between them into a voltage and generates a mode setting signal having a pulse width corresponding to the light irradiation time, and controls a plurality of operation modes of an internal circuit by controlling the mode setting signal. A semiconductor device comprising a test circuit having a state machine for generating an operation mode signal for switching. 2. The semiconductor device according to claim 1, wherein the semiconductor device is sealed in a package having a window with a filter through which only light of a specific frequency can pass.