JP2000284981A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate the generation of parity data at high speed by compact hardware. SOLUTION: An EEPROM controller 7 of this computer system is provided with a parity data generating circuit 72 which calculates parity for data in parity data generation units and a byte counter 73 which counts the parity data generating unit amounts, and which successively stores parity data in each parity data generation unit generated by the parity data generating circuit 72 in plural parity registers 32 in a register group 71.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer system such as a portable personal computer.

[0002]

2. Description of the Related Art Conventionally, various slots are provided in a computer system, for example, a portable personal computer.
For example, a flash type EEPROM called a compact flash or the like has come to be detachably attached as a memory for external expansion. By the way, in such a flash type EEPROM, a frequent rewriting operation of data may cause a defect in a memory cell.

Therefore, in order to increase the reliability of a computer system using such an EEPROM, it is necessary to take measures against possible defects, and an ECC (error correction code) is used for detecting the defects and taking measures. Used.

[0004] Therefore, in order to use an EEPROM, it is necessary to generate parity data of ECC. The prior art includes the following method.

(1) Parity data generation of the EEPROM is performed by software.

(2) Parity generation is performed using simple hardware that generates parity data only for data transfer in units of parity data generation.

(3) A buffer memory for a page size is provided, the buffer memory is divided into a plurality of banks by a parity data generation unit amount, and parity generation is performed by reading data of the parity data generation unit amount for each bank. (P
H-207726) Hereinafter, the above prior arts will be described in comparison with each other. NAND
In the ECC employed in the smart media using the type flash EEPROM, the parity data generation unit amount is 256 bytes, and the parity data is added to the 256-byte data. In addition, flash type E
In the EPROM, the data transfer unit amount is the page size of the EEPROM, and data transfer for the page size is performed at a time. The initial EEPROM page size is 256 bytes, and there are currently 256 bytes and 512 bytes. EEPROM ECC with page size of 512 bytes
For, 512 bytes are divided into two 256-byte areas, and parity data is generated for each area.

For example, in the prior art (1), in which parity data is generated by software, the processor needs to perform parity calculation on 256-byte data, so that processing takes time.

When parity generation is performed using hardware for generating parity data only for the data transfer of the parity data generation unit of the prior art (2), the page size of the EEPROM is 256 bytes of the parity data generation unit. For larger 512 bytes,
Parity data generation processing for 256 bytes is performed twice, so that the parity data generated after the first parity generation is read out and stored in another location (such as a work memory of a processor), and then the 256th parity data is generated. Since the parity generation processing for the bytes must be performed, the processing becomes complicated. If the size of the data to be transferred is smaller than the page size of the EEPROM, the size of the data to be transferred by the processor with dummy data must be adjusted to the page size of the EEPROM.

Further, PH10-20 of prior art (3)
In the method described in 7726, a buffer memory having a page size is provided in an EEPROM controller, a processor transfers data between the buffer memories, and a parity is provided between the buffer memory and the ECC circuit of the EEPROM. Although the data is divided into banks of the data generation unit amount and the parity is generated by reading the data for each bank, there is a problem that a buffer memory having a capacity corresponding to the page size is required.

[0011]

However, such a conventional technique has the following problems.

For example, in the prior art (1), EEP
Since the parity data generation of the ROM ECC is performed by software, there is a problem that the processing time becomes long.

In the prior art (2), since hardware is used to generate parity only for the parity generation unit, there is not much problem when the page size of the EEPROM matches the data size of the parity data generation unit. If the page size of the parity data generation unit is larger than the data size of the parity data generation unit, the data transfer must be performed a plurality of times and the parity data generation process must be performed for each data transfer of the parity data generation unit. Is smaller than the EEPROM page size, parity generation processing must be performed by adding dummy data to match the data size to the EEPROM page size, and parity error detection must be performed by software. Complex to be there is a problem that time-consuming.

Prior Art (3) (PH10-20772)
6) In the EEPROM controller, the EEPROM
Since the system has a buffer memory of the page size of the ROM and reads the data from the buffer memory to generate the parity data, there is a problem that the hardware must have a buffer memory for the page size. Was. At present, the maximum page size of the EEPROM is 512 bytes. However, if the page size becomes larger than 512 bytes in the future, a larger buffer memory is required, and there is a problem that the hardware configuration becomes large.

The present invention has been made to solve such a problem, and has as its object to provide a computer system capable of generating parity data at high speed with small hardware.

[0016]

According to a first aspect of the present invention, there is provided a computer system comprising: a counting means for counting an amount of data to be processed; A parity data generation circuit that calculates parity in the parity data generation unit for the data and generates parity data when the amount reaches a predetermined parity data generation unit, and can hold the parity data in each parity data generation unit A plurality of parity data registers, and means for sequentially storing the parity data of the parity data generation unit generated by the parity data generation circuit in the plurality of parity data registers.

According to the first aspect of the present invention, for data transfer of a page size, parity data is generated for each parity data generation unit amount, and the generated parity data is stored in a parity data register.

That is, by adding a parity data generation circuit for calculating parity for data of a parity generation processing unit and a plurality of parity data registers capable of holding the generated parity data, parity data processing can be performed. Since parity data can be created and stored for each unit amount, even if data is stored in a storage medium having a page size larger than the parity data generation unit amount, for example, data in an EEPROM, for example, data is transferred between the processor and the ECC circuit in a page size When writing parity data to the EEPROM, the processor reads the stored parity data and writes the parity data to the EEPROM.
The processing load on the processor can be reduced.

According to a second aspect of the present invention, there is provided a computer system comprising:
2. The computer system according to claim 1, wherein an end register in which end information indicating that the data processing has been completed is set, and the data processing is performed in the end register when the data is smaller than a data access size of a predetermined storage medium. It further comprises means for setting end information and means for reading / writing data from / to a predetermined storage medium when the data processing end information is set in the data processing end register.

In the second aspect of the present invention, when the data to be transferred is less than the page size of the EEPROM, the data transfer is completed by setting the data transfer end information in the data transfer end register after the data transfer is completed. In operation, parity data can be generated while writing data of a specific pattern to the EEPROM until the page size of the EEPROM is reached, and in read operation, parity data can be generated while reading data until the page size of the EEPROM is reached. The processing on the side can be completed by transferring the required amount of data, and the processing load on the processor can be reduced.

According to a third aspect of the present invention, there is provided a computer system comprising:
In a computer system having a storage medium control unit connected to a processor via an internal bus, the storage medium control unit counts an amount of data transferred through the internal bus, and counts by the counting unit. A parity data generation circuit that calculates parity in the parity data generation unit for the data and generates parity data when the data amount reaches a predetermined parity data generation unit; A plurality of parity data registers that can be held in the memory, and means for sequentially holding the parity data of the parity data generation unit generated by the parity data generation circuit for the plurality of parity data registers;
Means for causing the processor to generate an interrupt after the end of the data transfer.

In the case of the third aspect of the present invention, a means for generating an interrupt to the processor after the completion of the data transfer is newly added, so that the processor performs data transfer processing smaller than the page size of a storage medium such as an EEPROM. In this case, the processor can know that the processing for the page size has been completed by the interruption.

According to a fourth aspect of the present invention, there is provided a computer system comprising:
In a computer system having a storage medium control unit connected to a processor via an internal bus, the storage medium control unit counts an amount of data transferred through the internal bus, and counts by the counting unit. A parity data generation circuit that calculates parity in the parity data generation unit for the data and generates parity data when the data amount reaches a predetermined parity data generation unit; A plurality of parity data registers that can be held in the memory, and means for sequentially holding the parity data of the parity data generation unit generated by the parity data generation circuit for the plurality of parity data registers;
Comparing means for comparing parity data generated while reading the data with parity data read from a predetermined storage medium; a comparison result register for holding a comparison result by the comparison means; and a comparison held in the comparison result register Means for generating an interrupt signal to the processor in accordance with the result information.

According to the fourth aspect of the present invention, when data is read from a predetermined storage medium and processed, parity data is read from the predetermined storage medium after transferring data of a page size, and the generated parity data is compared. ,
In the case of a mismatch, an interrupt signal is issued to the processor.

That is, the generated parity data and EE
The addition of a comparator that compares the parity data read from the PROM and a means for generating an interrupt to the processor in the case of a mismatch, the processor has an error in the transfer data due to the interrupt after the page size data transfer. You can know.

According to a fifth aspect of the present invention, there is provided a computer system comprising:
2. The computer system according to claim 1, wherein when the parity data generation unit generated by the parity data generation circuit is 256 bytes, the counting means uses the parity data generation unit.
If 6 bytes have been counted and there is data remaining at that time, at least 2
The parity data is stored in each of the parity data registers.

In the case of the invention described in claim 5, the data access size is EE of both 256 bytes and 512 bytes.
It can correspond to a PROM, for example, a NAND flash EEPROM.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a computer system according to the present invention, for example, a portable personal computer (hereinafter referred to as a personal computer), and FIG. 2 is a diagram showing a main configuration of the computer system.

This computer system includes a bus controller 1, a display controller 2, a graphics accelerator 3, a USB host controller 4, a VRAM controller 5, a PCMCIA controller 6, and a flash EEPROM controller 7 as a storage medium control means.
(Hereinafter referred to as EEPROM controller 7), I / O bus interface controller 8 (hereinafter referred to as I / O bus controller 8), register interface bus 9, VRAM interface bus 10, clock controller 11, interrupt controller 12, system memory 20, Processor 21, power control circuit 22, ROM2
3, a VRAM 24, a keyboard controller 25 (hereinafter referred to as KBC 25), and the like.

Bus controller 1, display controller 2, graphics accelerator 3, USB host controller 4, VRAM controller 5, PCMCIA
Controller 6, EEPROM controller 7, I / O
Bus controller 8, register interface bus 9,
The VRAM interface bus 10, clock controller 11, interrupt controller 12, and the like are each mounted as a device controller 100 in one IC chip and are integrated into one chip.

The bus controller 1 converts a system bus into an internal bus. The display controller 2 performs control for displaying on an LCD panel or a CRT. The graphics accelerator 3 improves the display speed. The USB host controller 4 controls the connected USB device. V
The RAM controller 5 controls the VRAM 24. PC
The MCIA controller 6 controls the connected card device. The EEPROM controller 7 is the processor 2
1, a predetermined storage medium connected in accordance with a read / write instruction from, for example, a flash EEPROM 77 (hereinafter referred to as EE).
To write and read data. I / O bus controller 8 is K
It controls the BC 25 and other connected expansion devices.
The register interface bus 9 is an internal bus used for accessing an internal register. That is, the register interface bus 9 is used for data transmission between registers of each module connected inside the device controller 100. VRAM interface bus 10 is VRAM2
4 is a bus for connecting devices that access 4. DR
The AM system memory 20 stores various programs including a program of a processing procedure related to the operation of the present apparatus and constant data. The processor 21 performs overall control of the apparatus based on a program stored in the DRAM system memory 20, and performs arithmetic processing on various data input from a keyboard or the like, and instructs writing and reading of data to and from the EEPROM 77. . Power control circuit 22
Controls the power supply voltage of the entire system. The MROM 23 stores an application program for improving the use efficiency of the interface. The VRAM 24 stores various data to be displayed on the display device in a bitmap image. The KBC 25 is one of the extension devices, and encodes key information input from a keyboard and transmits it to the I / O bus controller 8. The EEPROM 77 is, for example, a NAND flash EEPROM and has a page size of 256 bytes or 512 bytes. As one of the NAND flash EEPROMs,
For example, there is a product called smart media.

FIG. 2 shows the EEPROM controller 7 of FIG.
FIG. 4 is a block diagram showing the details of.

The EEPROM controller 7 includes a register group 71, an EEPROM ECC parity generation circuit 7,
2 (hereinafter referred to as a parity generation circuit 72), a byte counter 73, a data area counter 74, a read / write control circuit 75, a comparator 76, and the like. The register group 71 is for the processor 21 to access, and includes a plurality of registers. The parity data generation circuit 72 calculates a parity every time data is input, and incorporates the parity into the parity data. The byte counter 73 counts the number of bytes of data subjected to the parity generation processing. The data area counter 74 counts the number of bytes of the parity data generation unit for each process. The read / write control circuit 75 is EEPRO
Read data from M77 and EEPROM 77
Write data to The comparator 76 compares the parity data generated by the parity data generation circuit 72 with the parity data read from the EEPROM 77, and stores the comparison result in the register group 71.

As shown in FIG. 3, a register group 71 includes a data transfer register 31, a plurality of parity data registers 32 for storing ECC parity data in units of generation, and a data transfer end flag indicating the end of data transfer. Register 33, data transfer processing completion flag register 3
4. A comparison result register 35 for storing data of the comparison result by the comparator 76 is provided.

The operation of the computer system according to this embodiment will be described below. First, an operation for writing data to the EEPROM 77 will be described.

Writing of data to the EEPROM 77 is performed by writing data from the processor 21 to the data transfer register 31 in the register group 71 of FIG. When data is written from the processor 21,
The read / write circuit 75 stores the data in the EEPROM 7
Write to 7. When the data is written to the EEPROM 77, the parity data generation circuit 72 calculates the parity and incorporates the parity into the parity data. The byte counter 73 counts the number of bytes each time data is written. When the counter value reaches the number of bytes of the parity data generation unit, the data area counter 74 indicates the parity data generated by the parity data generation circuit 72. Register group 7
1 (one of the plurality of parity data registers 32). After storing the parity data, the byte counter 73 returns to the initial value, and the data area counter 74 is counted up by the byte counter 73. If the page size of the EEPROM 77 is larger than the number of bytes of the parity data generation unit (256 bytes or 512 bytes), there is still data to be transferred, and the processor 21 stores the remaining data in the data transfer register 31. Write. Even in this case, the byte counter 73 returns to the initial value, and the data area counter 74 counts up. At this time, since the count value of the data area counter 74 indicates the next area, the parity data generation circuit 72 continuously generates parity data for the next parity data generation unit.

Similarly, this operation is repeated, and the parity data generation circuit 72 generates the parity data. After the processing of the parity data generation unit amount is completed, the parity data generated by the parity data generation circuit 72 is transferred to the data area counter 74. (One of the parity data registers 32). Also in this case, since the data area counter 74 has been counted up, the parity data generated for each parity data generation unit is stored in a different parity data register 32 in the register group 71.

If the write data ends without satisfying the page size of the EEPROM 77, the processor 21
Is the data transfer end flag register 33 of the register group 71
Is set to indicate a data transfer end. When this flag is set, the EEPROM controller 7
It is assumed that data of a specific pattern (for example, data in a reset state of the EEPROM 77) has been
Data writing to the EEPROM 77 and parity data generation processing are continued until the page size of the OM 77 is reached.

When the processing is completed with the page size of the EEPROM 77, a completion flag is set in the data transfer processing completion register 34 in the register group, and an interrupt signal is output to the processor 21.

When the above-described processing is completed and the data transfer processing of the page size is completed, the parity data is stored in the plurality of parity data registers 32 so that the parity data is stored in the EEPROM.
When writing to the ROM 77, the processor 21 can write the parity data to a predetermined position of the EEPROM 77 only by reading the respective parity data held in each parity data register 32. That is,
The processor 21 does not need to calculate the parity,
The load on the processor 21 can be reduced.

With such a configuration, the EEP
The process of writing data to the ROM 77 is independent of the parity data generation unit of the ECC, that is, without being fixed to either 256 bytes or 512 bytes.
It is possible to send data.

Further, even when the data amount is less than the page size of the EEPROM 77, the data transfer can be completed without sending dummy data for supplementing the data amount, so that a large-capacity buffer memory is not required as hardware. This can simplify the program and speed up the writing process.

Next, a case where data is read from the EEPROM 77 will be described. Reading data from the EEPROM 77 is performed by reading the data transfer register 31 in the register group 71 of FIG. 3 from the processor 21.

When the data in the data transfer register 31 is read by the processor 21, the read / write circuit 75 reads the data from the EEPROM 77.

The parity data generation circuit 72 has a read /
The parity of the data read by the write circuit 75 is calculated and incorporated into the parity data.

The byte counter 73 counts the number of bytes each time data is read. When the counted number of bytes (count value) of the byte counter 73 reaches the number of bytes of the parity data generation unit, the parity data is counted. The parity data in the generation circuit 72 is stored in a location (any of the plurality of parity data registers 32) in the register group 71 indicated by the data area counter 74.

After storing the parity data, the byte counter 7
3 returns to the initial value, and the data area counter 74 is counted up.

When the page size of the EEPROM 77 is larger than the number of bytes of the parity data generation unit, there is still data to be transferred, and the processor subsequently reads the data transfer register. The byte counter 73 returns to the initial value, and the data area counter 74 counts up. Since the count value of the data area counter 74 indicates the next area by counting up the data area counter 74, the parity data generation circuit 72 continuously generates parity data for the next parity data generation unit.

Similarly, this operation is repeated to generate parity, and after the parity data generation circuit 72 completes processing of the parity data generation unit amount, the data area counter 74 indicates the parity data generated by the parity data generation circuit 72. Stored in position. Also in this case, since the data area counter 74 is counted up, the generated parity data is stored in a different parity data register 32 in the register group 71 for each parity data generation unit.

If the data to be read ends without satisfying the page size of the EEPROM 77, the processor 21
Sets a flag indicating the end of the data transfer process in the data transfer end flag register 33 in the register group 71.

When this flag is set in the data transfer processing end flag register 33, the EEPROM controller 7 continues reading processing up to the page size of the EEPROM 77.

On the other hand, when the processing is completed with the page size of the EEPROM 77, the EEPROM controller 7 sets a flag indicating the processing completion in the data transfer processing completion register 34 in the register group 71 and sets the processor 21
An interrupt signal (completion) is output to notify the completion of the parity check.

When performing the data reading process, first, the comparator 76 compares the data generated by the parity data generation circuit 72 and stored in the plurality of parity data registers 32 in the register group 71 with the EEPR.
The parity data read from the OM 77 is compared.
The comparison result (match / mismatch) is stored in the comparison result register 35.
To memorize.

Here, if the comparison result data stored in the comparison result register 35 indicates, for example, a mismatch, E
The EPROM controller 7 outputs an interrupt signal (error) to the processor 21 to notify a parity check error.

Thus, in the process of reading data from the EEPROM 77, data can be read irrespective of the ECC parity data generation unit. Further, even if the required data amount is less than the page size of the EEPROM 77 by providing the data transfer completion flag register 33 as one of the register groups 71, the data transfer is completed without reading the data in the page size. Therefore, some registers 71 may be used as hardware.
Thus, data processing becomes possible without having a large-capacity buffer memory having a page size, thereby simplifying a program and speeding up a reading process.

As described above, according to the computer system of this embodiment, the EEPROM controller 7 has the register group 7
1 and the parity data generation circuit 72, and the parity data is generated by hardware.
Data processing can be performed at high speed (short time) as compared with the case where parity data generation of PROM ECC is performed by software and parity calculation takes time.

Conventionally, parity data of the EEPROM ECC is generated using a large-capacity buffer memory having a page size of the EEPROM, so that a buffer memory having a certain capacity is required. Since a plurality of parity data registers in units of parity data generation are provided, and the comparison processing is performed while holding the parity data in each unit, it is not necessary to have a costly buffer memory as a hardware configuration, and the cost can be reduced. .

Further, conventionally, parity generation is performed in a configuration that places a load on a processor that generates parity only for a fixed value data amount of the parity data generation unit. Therefore, the page size of the EEPROM, the parity generation unit amount, The parity generation process of the processor 21 becomes complicated when the values do not match. However, in this computer system, the parity data generation circuit 72 for calculating the parity for each data transfer of the parity data generation unit amount.
And a register group 71 for holding the generated parity data in a plurality of parity data registers 32 for each data generation unit, so that parity generation processing can be performed even when the page size of the EEPROM does not match the parity generation unit amount. Can be done at high speed.

If the data transfer amount is smaller than the page size of the EEPROM 77, the processor 21 transfers the necessary amount of data and then sets the flag indicating the end of the data transfer to the data transfer end register 3 in the register group 71.
If the value is set to 3, the next processing can be performed, so that the parity data can be transferred at a high speed. Further, by providing a plurality of registers of the minimum parity data generation unit, it is possible to cope with the case where the page size is equal to or larger than the parity data generation unit amount. Further, the processor 21 transfers only the necessary data amount and
When the processing between the M controllers 7 is completed, even if the data transfer amount is less than the page size of the EEPROM 77, the EEPROM controller 7 can generate the parity data while continuing the transfer of the dummy data until the data size reaches the page size.

Further, by providing the EEPROM controller 7 with a comparator 76 for comparing parity data and a function for generating an interrupt based on the comparison result, the processor 21 transfers a necessary amount of data, and the processor 21 and the EEPROM controller 7 When the process between the two is completed, the EEPROM controller 7
Since the parity is generated by reading the dummy data until the page size is reached, a parity error can be detected and an interrupt can be generated when an error occurs.

[0062]

As described above, according to the first aspect of the present invention, a parity data generating circuit for calculating a parity for data of a parity generation processing unit, and a plurality of parities capable of holding the generated parity data By adding a new data register, parity data can be created and stored for each processing unit amount of parity data.
For example, even in a storage medium having a page size larger than the parity data generation unit amount, for example, data of an EEPROM or the like,
For example, data may be transferred in a page size between the processor and the ECC circuit.
When writing to the OM, the processor only needs to read the stored parity data and write it to a predetermined position in the EEPROM, so that the processing load on the processor side can be reduced. According to the second aspect of the present invention, when the data to be transferred is less than the page size of the EEPROM, as long as the processor sets the data transfer end information in the data transfer end register after the end of the data transfer,
During a write operation, parity data is generated while writing data of a specific pattern into the EEPROM until the data reaches the EEPROM page size.
Parity data can be generated while reading data up to the OM page size, and the processing on the processor side can be completed by transferring the required amount of data, thereby reducing the processing load on the processor side. it can.

According to the third aspect of the present invention, a means for generating an interrupt to the processor after the completion of data transfer is newly added, so that the processor performs data transfer processing smaller than the page size of a storage medium such as an EEPROM. In this case, the processor can know that the processing for the page size has been completed by the interruption.

According to the fourth aspect of the present invention, the comparing means for comparing the generated parity data with the parity data read from the predetermined storage medium, and the means for generating an interrupt to the processor when the comparison results do not match. Is newly added, the processor can know that there is an error in the transfer data due to the interruption after the transfer of the page size data.

According to the fifth aspect of the present invention, the data access size is E bytes of both 256 bytes and 512 bytes.
EPROM, for example, NAND flash EEPROM
Can respond to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an EEPROM controller of the computer system.

FIG. 3 is a diagram showing a register group of the computer system.

[Explanation of symbols]

1: Bus controller, 7: Flash EEPROM
Controller (EEPROM controller), 8 ... I /
O bus interface controller, 20 ... DRAM,
21: processor, 25: KBC, 71: register group,
72: EEPROM ECC parity generation circuit 72 (parity data generation circuit), 73: byte counter, 74
... Data area counter, 75 ... Read / write control circuit, 76 ... Comparator, 77 ... EEPRO
M, 100: Device controller.

Claims (5)

[Claims] A counting means for counting an amount of data to be processed; and when the data amount counted by the counting means reaches a predetermined parity data generation unit, a parity data generation unit is used for the data. A parity data generation circuit that calculates parity data and generates parity data; a plurality of parity data registers capable of holding the parity data for each parity data generation unit; and a parity data generation circuit for the plurality of parity data registers. Means for sequentially storing the generated parity data of the generated parity data generation unit. 2. The computer system according to claim 1, wherein: an end register in which end information indicating that data processing has been completed is set; and when the data is less than a data access size of a predetermined storage medium, Means for setting data processing end information in an end register; and means for reading / writing data from / to a predetermined storage medium when the data processing end information is set in the data processing end register. A computer system characterized by the following. 3. A computer system having a storage medium control unit connected to a processor via an internal bus, wherein the storage medium control unit counts an amount of data transferred through the internal bus; When the data amount counted by the counting means reaches a predetermined parity data generation unit, a parity data generation circuit that calculates parity in the parity data generation unit for the data and generates parity data; A plurality of parity data registers that can be held for each parity data generation unit, and means for sequentially holding the parity data of the parity data generation unit generated by the parity data generation circuit in the plurality of parity data registers, and data transfer Generate an interrupt to the processor after termination Computer system, characterized by comprising a stage. 4. A computer system having a storage medium control unit connected to a processor via an internal bus, wherein the storage medium control unit counts an amount of data transferred through the internal bus; When the data amount counted by the counting means reaches a predetermined parity data generation unit, a parity data generation circuit that calculates parity in the parity data generation unit for the data and generates parity data; A plurality of parity data registers that can be held for each parity data generation unit; a means for sequentially holding the parity data of the parity data generation unit generated by the parity data generation circuit for the plurality of parity data registers; Parity data generated while reading Comparison means for comparing the parity data read from the storage medium; a comparison result register for holding the comparison result by the comparison means; and an interrupt signal to the processor in accordance with the information on the comparison result held in the comparison result register. And a means for generating. 5. The computer system according to claim 1, wherein when the parity data generation unit generated by the parity data generation circuit is 256 bytes, when the counting means counts 256 bytes, A computer system, wherein when there is remaining data, at least two parity data calculated continuously are held in each of the parity data registers.