KR20030000017A - Apparatus and Method for controlling flash memories - Google Patents

Abstract

PURPOSE: A device and a method for controlling a flash memory are provided to improve the reading and writing speed of the flash memory without increasing the number of the pins of the flash memory control device, and to reduce the time for accessing the flash memories even while plural flash memories are operated parallel. CONSTITUTION: The flash memory controller(30) is connected with a flash memory array(100) via a memory bus(20) and with a host system(50) via a host bus(40). The flash memory array(100) includes plural memory banks(106,108). Each memory bank(106,108) includes plural memory units(102,104). The flash memory(100) is connected to the system bus of a CPU via an input/output interface. The host system(50) transmits the address signals, the data signals, the command signals, and the control signals to the flash memory controller(30). The host system(50) exchanges the data in the sector unit with the memory array(100) via the memory controller(30). If the data are the data of more than two sectors, the memory controller(30) simultaneously programs the sector data in the enabled memory units(102,104). If the data are one sector data, one memory unit(102,104) is enabled.

Description

Flash memory control device and flash memory control method {Apparatus and Method for controlling flash memories}

The present invention relates to a memory semiconductor technology, and more particularly to a flash memory control apparatus and method that can increase the operating speed of the flash memory without increasing the number of pins.

As the data storage capacity required by various portable electronics and embedded devices increases, the demand for flash memory type EEPROM (Electrically Erasable Programmable Read Only Memory) is increasing. Flash memory serves as a replacement for mass data storage devices, such as hard disks, but also includes embedded processors such as PCMCIA flash cards, MP3 players, digital voice recorders, RISC CPUs used in routers, or DSPs used in mobile phones. Function to save program code.

In the flash memory, data input / output is controlled by a controller connected between the host system (eg, a PC or a portable electronic device) and the flash memory. Writing (or programming) data to and from the flash memory takes a lot of time. For this reason, reducing the time taken to read and write data to and from a flash memory control system is one of the most important technical challenges. In the prior art, in order to speed up data read and write, a method of optimizing software or increasing frequency (for example, speeding up an operation of a memory controller that processes data input from a host system, or between a memory controller and a flash memory) To speed up the interface) or to connect several flash memories in parallel. However, the conventional software optimization technique has limitations according to the configuration of the host system or the flash memory control system, and the frequency increase method has a disadvantage in that the speed improvement is limited due to the operation limit of the flash memory and the increase in the current of the system.

On the other hand, in the prior art of connecting the flash memory in parallel, for example, because the two flash memory chips are controlled independently, the controller is parallel to the number of parallel control signal interface pins to independently access the connected flash memory in parallel. You will need as many data interface pins as you can connect. In addition, since each flash memory connected in parallel must be controlled separately, there is a disadvantage that a program is lengthened by the number of flash memories connected in parallel.

An object of the present invention is to improve the read / write speed for a flash memory without increasing the pin count of the flash memory control device.

Another object of the present invention is to reduce the time required to access each flash memory while operating a plurality of flash memories in parallel.

1 is a block circuit diagram showing an overall connection structure of a flash memory control system, a host system and a flash memory array according to the present invention.

2 is a block circuit diagram illustrating a data storage structure of a memory unit according to an embodiment of the present invention.

3 is a flowchart illustrating a flash memory control process according to the present invention;

<Description of Major Symbols in Drawing>

12, 22: chip select signal bus 14, 24: status signal bus

16, 26: data signal bus 18: control signal bus

20: memory bus 30: flash memory controller

40: host bus 50: host system

100: flash memory array 102, 104: flash memory unit

106, 108: Flash Memory Bank 112: Page

114: block 116: I / O buffer

123, 127, 133, 135: sector

The flash memory control apparatus according to the present invention is connected between a host system and a flash memory array to transfer sector-by-sector data from the host system to the flash memory array, wherein the flash memory array includes a plurality of memory banks. Each of the plurality of memory banks includes a plurality of memory units, each of the plurality of memory units including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of pages, each of the plurality of pages being one or more Include sectors. If the data received from the host system is two or more sector data for different memory units, the flash memory control device simultaneously enables two different memory units addressed to send the data, thereby enabling the two sector data to be received. While simultaneously programming the enabled memory units, if the data received from the host by the flash memory controller is one sector data, the flash memory controller enables one memory unit designated to send sector data to this memory unit. Program the received sector data.

A flash memory control device according to another aspect of the present invention includes a number of data interface pins that can be connected in parallel with a plurality of memory banks connected in parallel, and the flash memory control device and the flash memory array share control signal interface pins. The data interface pin and the chip select signal pin are independently connected between the flash memory controller and the plurality of memory banks of the flash memory array.

The flash memory control method according to the present invention comprises the steps of receiving a logical address for the flash memory from the host system to convert to a physical address, determining the number of sectors to be written to the flash memory in the host system, the determination step In the case where the number of sectors is '1', one sector data is received and the bank is calculated and the corresponding one flash memory bank is enabled, and when the number of sectors is '2' or more, two sector data are received. Receiving and enabling two corresponding flash memory banks and initiating a flash write operation for a memory block designated by the physical address of the enabled memory bank. When two memory banks are enabled, for example, data is written to the first flash memory via the first data bus [0: 7] and data is also written to the second flash memory via the second data bus [8:15]. Record it.

Embodiment

Embodiments of the present invention will be described below with reference to the drawings.

1 is a block circuit diagram illustrating an overall connection structure of a flash memory control system, a host system, and a flash memory array according to the present invention.

The flash memory controller 30 is connected to the flash memory array 100 through the memory bus 20 and to the host system 50 through the host bus 40. Host bus 40 may be, for example, a 16-bit data line. The flash memory array 100 includes a plurality of memory banks 106 and 108, each of which includes a plurality of memory units 102 and 104. Although two memory banks 106 and 108 are shown in this implementation, it is also possible for memory array 100 to include three or more memory banks. The memory units 102 and 104 are, for example, NAND flash memory in which 16 memory cells are connected in series. The host 50 may be an OS-based processor such as a PC or a processor chip of an embedded system without an OS. If the host 50 is an OS processor, the flash memory 100 operates as one of the standard peripherals and is connected to the system bus of the CPU through an I / O interface such as an IDE disk drive. The host system 50 transmits an address signal, a data signal, a command signal, and a control signal to the memory controller 30 through the host bus 40. The host 50 exchanges data in sector units with the memory array 100 through the memory controller 30. One sector may consist of, for example, 512-byte user data and Error Coding and Correction (ECC) data.

The memory controller 30 exchanges data with the memory array 100 through the memory bus 20 and controls the operation of the memory array 100. The memory bus 20 may include a chip enable (CE) signal 12, a state signal bus 14, a data bus 16, and a second flash memory for the first flash memory 102 and FM0. Controls commonly connected to the chip select signal bus 22, the state signal bus 24, the data bus 26, and the first flash memory 102 and the second flash memory 104 for (104, FM1). A signal bus 18. The control signal bus 18 includes a first control signal bus 18a branched and connected to the first flash memory 102, and a second control signal bus 18b connected to the second flash memory 104. .

In this embodiment, since the chip select signal CE output from the memory controller 30 is supplied through separate buses 12 and 22 for each of the flash memories 102 and 104, a plurality of flash memory units may be provided. It is possible to enable at the same time or only one. In addition, while the control signals for the flash memories 102 and 104 are commonly connected, the data signals are supplied separately through separate buses. Thus, according to this embodiment, the memory controller 30 is configured to send data if the data received from the host 50 is two or more sector data for different memory units. Simultaneously enable the unit to program two sector data simultaneously into the enabled memory units, and if the data received from the host 50 by the memory controller 30 is one sector data, then one memory unit It is possible to enable and program the received sector data in this memory unit.

The flash memory controller 30 may include, for example, a control chip and a flash control block. In this case, the control chip may include circuit elements for SRAM, core, MMU, interrupt control, sector buffer, remap, CR interface, and the like. The control chip activates the CE signal according to the size of data to be sent through the flash control block, and sends data to each memory bank through an ECC in each memory bank.

2 is a block circuit diagram illustrating a data storage structure of a memory unit according to an embodiment of the present invention.

One memory unit 102 includes a plurality of memory blocks 114, i.e., block 0, block 1,... , Block [N-1], and one memory block includes a plurality of pages 112, that is, page 0, page 1,. , Page [M-1]. One page 112 includes a plurality of sectors 123, 127, 131, and 135. Each sector consists of user data 122, 126, 130, and 134 and corresponding ECC data 124, 128, 132, and 136, respectively. One user data is for example 512-bytes and ECC data is 8-bytes. The ECC data varies in size depending on the configuration of the ECC block, and is used, for example, in the memory controller 30 to perform error detection and correction operations on user data of each sector. 2 shows a 2k-byte page having four sectors, but if the capacity of the memory unit is 1G or less, the page and sector may be equalized to 512-bytes. In one embodiment of the present invention, 64 pages may be configured in one memory block, and 2,048 memory blocks may be configured in one memory unit.

Control signals supplied via bus 18 are, for example, command latch enable (CLE), address latch enable (ALE), write enable (WE), read enable (RE), write protect (WP), power (on) Read Enable) signal. A status signal, that is, a R / B (Ready / Busy output) signal is generated in the flash memory to indicate whether the flash memory is ready or busy. The R / B signal terminal is connected to a 5V power supply, for example, and pulls up an R / B signal generated from a flash memory to the memory controller 30 to support parallel access of two flash memories. Two status registers are available for this purpose. The data buses 16 and 18 transmit data signals, address signals and command signals in a time multiplexed manner. Data supplied from the memory controller 30 to the flash unit 102 is latched in the I / O buffer 116 and then written to the sector of the corresponding block of the flash unit 102.

If the data to be supplied to the flash array 100 is two sector data, for example, sector 0 data is sent to the first flash unit 102 through the first data bus 16, and sector 1 data is sent to the second data bus. Simultaneously to the second flash unit 104 via 26. Even sectors, that is, sector 0, sector 2, etc., are included in the first memory bank 106, and odd sectors, that is, sector 1, sector 3, etc., are included in the second memory bank 108. do. Data supplied via one data bus 16, 26 is 8-bit of the 16-bit sector data. On the other hand, if the data to be supplied to the flash array 100 is one sector data, the sector data to the corresponding flash unit via one of the two data buses (for example, [0: 7] or [8:15] data bus). Send it. To send two sectors of data simultaneously, for example two parallel accesses of 512M flash memory, the memory controller uses a buffer of 1K capacity per page, or 4K per page to support parallel access of two 1G or 2G flash memories. A capacity buffer can be used.

3 is a flowchart illustrating a flash memory control process according to the present invention.

When a host write operation (or write operation) is initiated (step 302), the host, for example, passes a 4-byte address-related input and a 1-byte sector number to the memory controller and provides a write command or a read command (step 304). The memory controller calculates the logical address using the 4-byte address related input received from the host. The address received from the host is a logical address and in order to write it to the flash unit, the memory controller must calculate and translate a physical address corresponding to the logical address (step 306). It is determined whether the converted physical address is a valid address (step 308), and if it is not a valid address, the physical address conversion process 306 is repeated, and if it is a valid address, it is determined whether the number of sectors is less than two (step 310). . If the number of sectors in step 310 is less than two, the memory controller receives one sector data (step 316) and calculates a bank (step 318). In the bank calculation, for example, the least significant bit of the sector address is checked and 'bank 0' when the value is '0' and 'bank 1' when the value of the least significant bit is '1'. According to the calculated bank, bank 0 or bank 1 is enabled (step 320), and the flash write operation is performed. On the other hand, if the number of sectors is greater than 2 in the sector number determination step 310, the memory controller receives two sector data (step 312), enables bank 0 and bank 1 simultaneously (step 314), Proceed to a flash write operation.

For one or two banks enabled, a sequential data input command (80H command) is input, for example, in a flash write command input step 322. The flash data is sequentially loaded into the I / O buffer according to the 80H command, and an address is received, in which the column address and the row address are sequentially received after the ALE signal is activated (step 324). After the ALE signal is made inactive, the flash data is written to the designated memory cell while the WE signal is repeated in the active-inactive state (step 326). Since data is written in the memory cell in page units, for example, in step 326, 512-byte + 16-byte, that is, 528-byte data is written at a time. It is determined whether there is more sector data to be written to the memory (step 328). If there is more sector data to be written, the process returns to the physical address translation step 306 along the path 330 to repeat the above process. If there is no more, the write operation is completed (step 332). During the write operation, the memory controller may determine whether a program cycle is terminated by examining a state signal output from the flash memory, that is, an R / B signal. Completion step 332 gives a read status command (70H command) and examines the data of I / O 0. If the value is '0', it is determined that the write operation was normal and the data of I / O 0 is '1'. In this case, the method may include determining that there is an error in the program.

According to the present invention, since an additional pin is not required to control each chip separately in the memory controller of the related art, a flash can be operated while saving a number of pins required for a package while simultaneously operating a plurality of flash memory units in parallel. The operation speed of the memory can be improved.

In addition, in the present invention, the additional memory required by accessing along each chip in the prior art can speed up the flash memory.

Claims (16)

A flash memory control device connected between a host system and a flash memory array to transfer sector-based data from the host system to the flash memory array. The flash memory array includes a plurality of memory banks, each of the plurality of memory banks including a plurality of memory units, each of the plurality of memory units including a plurality of memory blocks, and each of the plurality of memory blocks A plurality of pages, each of the plurality of pages comprising one or more sectors, When the data received from the host system is two or more sector data for different memory units, the flash memory control device simultaneously enables two memory data addressed to different memory units addressed to the data. Is simultaneously programmed into enabled memory units, while the flash memory controller enables one memory unit designated to send sector data if the data received from the host by the flash memory controller is one sector data. And program the received sector data into the memory unit. The flash memory controller of claim 1, wherein the flash memory device is connected through a separate bus for chip selection of each of a plurality of memory banks. The flash memory control device according to claim 1 or 2, wherein the flash memory device is connected through a control signal bus which is commonly connected to a plurality of memory banks. 3. The flash memory control device of claim 1 or 2, wherein the flash memory device is connected to each of a plurality of memory bank banks through a separate data signal bus. The flash memory device of claim 1, wherein the flash memory device is connected through a separate data signal bus for each of the plurality of memory bank banks, and is connected through a control signal bus commonly connected to the plurality of memory banks. Flash memory control device characterized in that. 2. The flash memory controller of claim 1, wherein each of the pages has the same size as a sector. 2. The flash memory controller of claim 1, wherein each of the pages is larger in size than a sector. A flash memory control device connected between a host system and a flash memory array and transferring sector data from the host system to the flash memory array. The flash memory array includes a plurality of memory banks connected in parallel, each of the plurality of memory banks including a plurality of memory units, each of the plurality of memory units including a plurality of memory blocks, and the plurality of memories. Each block includes a plurality of pages, each of the plurality of pages including one or more sectors, The flash memory control device includes as many data interface pins as can be connected in parallel with the plurality of memory banks connected in parallel, the flash memory control device and the flash memory array share a control signal interface pin, and the data interface pins And the chip select signal pins are independently connected between the flash memory controller and the plurality of memory banks of the flash memory array. 9. The flash memory controller of claim 8, wherein the flash memory control device simultaneously enables different memory units addressed to send the data when the data received from the host system is two or more sector data for different memory units. Program two sector data simultaneously to the enabled memory units, and if the data received from the host by the flash memory controller is one sector data, the flash memory controller is one memory designated to send sector data. Enabling a unit to program the received sector data into the memory unit. The memory controller of claim 1, wherein the memory controller uses a buffer of 1K capacity per page for parallel access of two 512M flash memories of the flash memory array, or supports two parallel accesses of 1G or 2G flash memories. In order to use the flash memory control device characterized in that for using a buffer of 4K capacity per page. As a flash memory control method, Receiving a logical address for the flash memory from the host system and converting the logical address into a physical address; Determining, by the host system, the number of sectors to be written to the flash memory; In the determining step, when the number of sectors is '1', one sector data is received and a bank is calculated to enable one corresponding flash memory bank, and when the number of sectors is '2' or more, 2 Receiving two sector data and enabling two corresponding flash memory banks; Initiating a flash write operation for a memory block specified by the physical address of the enabled memory bank. The unit of claim 11, wherein the unit for obtaining data from the host system is a sector, the unit for writing data to the flash memory bank is a page, and the plurality of pages constitutes one memory block and the plurality of memory blocks are one unit. A flash memory control method comprising: a memory unit, wherein a plurality of memory units constitute a memory bank. 12. The method of claim 11, wherein before the address translation step, a flash memory controller receives an address related input and sector number data from the host system, and when a read or write command is received from the host system, the memory controller receives the address related input. And calculating a logical address by using the flash memory. 12. The flash memory control method of claim 11, further comprising determining whether the converted physical address is a valid address after the address translation step. 12. The method of claim 11, wherein the flash write operation comprises sequentially inputting flash data, receiving an address, and then writing the flash data to a designated memory cell. The data storage device of claim 11, wherein when the two memory banks are enabled in the enable step, data is written to the first flash memory through the first data bus and simultaneously to the second flash memory through the second data bus. Flash memory control method characterized in that.