JP2000277911A - Manufacture of wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board that can reduce the number of manufacturing steps for forming via hole, improve reliability of conductivity between the circuit layers through the via holes, and form an aperture of each circuit layer forming a part of the via hole with high positional accuracy. SOLUTION: A method of manufacturing a wiring board having a plurality of circuit layers 1 comprises the steps in which an insulation resin layer 2 and a circuit layer 1 are laminated on the circuit layer 1 of an interval layer substrate 5 that is formed on the surface of the insulation resin layer 2, by providing a circuit layer 1 and the circuit layer 1 is connected conductivity with a via hole 3 opened in the surface layer side. To the circuit layer 1 which is conductivity connected with the via hole 3, an aperture 4 forming a part of the via hole 3 is provided. Among the circuit layers 1 connected conductively, the diameter of the aperture 4 of the circuit layer 1 arranged in the surface layer side is formed larger by about 50 to 200 μm, than the diameter of aperture 4 of the circuit layers 1 which are arranged on the internal layer side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board in which a plurality of circuit layers are laminated and formed, and conduction between the circuit layers is secured by via holes which are non-through holes.

[0002]

2. Description of the Related Art In recent years, the size and weight of electric and electronic devices such as mobile phones have been rapidly reduced. The multilayer wiring board used for the substrate of such an electric or electronic device has been increasingly densified, miniaturized, and thinned by a build-up multilayer wiring board.

Various methods have been provided for manufacturing a build-up multilayer wiring board. For example, one of the methods is as follows. That is, a circuit is formed by patterning the metal layer on the surface of the inner substrate 5 using the inner substrate 5 having a metal layer such as copper formed by metal foil or metal plating on the surface of the resin laminate. A resin-coated metal foil formed by providing a resin layer on one side of a metal foil such as a foil is superimposed on the surface of the inner layer substrate 5 on the side of the resin layer, and is heated and pressed to form the inner layer substrate via the resin layer. By laminating a metal foil on 5 and patterning the metal foil to form a circuit, a build-up multilayer wiring board can be obtained. If necessary, the circuit can be further formed in multiple layers by repeating the lamination of the metal foil with resin and the patterning of the circuit.

Here, in order to secure conduction between circuits,
Via holes are generally formed as disclosed in Japanese Patent Publication No. Hei 4-3676. In forming the via hole, each time the circuit layer 1 is sequentially formed, the via hole 3 for electrically connecting the circuit layer 1 and the inner circuit layer 1 can be formed, but the number of manufacturing steps is reduced. From the viewpoint, it is desirable to form the via holes 3 after the circuit layers 1 are all laminated and formed.
In this case, as shown in FIG. 6A, an opening 4 is formed in advance in each of the circuit layers 1 laminated and formed, and a portion where the opening 4 is formed is irradiated with a laser beam. Via holes 3 are formed on the inner periphery so that the openings 4 of the circuit layers 1 are exposed, and plating layers are formed on the inner surfaces of the via holes 3.

However, in the prior art disclosed in the above publication, as shown in FIG. 6B, if the formation position of the opening 4 formed in each circuit layer 1 is slightly shifted, the via hole 3 is not formed. There is a problem that the area of each circuit layer 1 exposed on the inner peripheral surface is reduced, and the conduction reliability between circuits is impaired. Also, the via hole 3 thus formed is formed.
The inner peripheral shape becomes more complicated as the opening 4 is displaced, and becomes more complicated as the number of stacked circuit layers 1 is increased. Even so, plating solution is via hole 3
It becomes difficult to reach the entire inner circumference, and the circuit layer 1
The reliability of conduction between them was impaired.

On the other hand, as a method of ensuring conduction between circuit layers by using a through-hole as a through-hole, US Pat.
No. 8468 discloses a technique of forming an opening in each circuit layer to be laminated and forming a through hole by irradiating a laser beam to a portion where the opening is provided.
Also, it is described that the conduction between circuit layers is improved by sequentially reducing the diameter of each opening formed in each circuit layer from the surface layer side. Regarding the formation of holes, such a technique has not been disclosed. Further, in this prior art, there is no mention of the difference in diameter between the openings, and there is no technical idea of ensuring the conduction by forming the openings with high positional accuracy. Was.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to reduce the number of steps for forming a via hole and to improve the reliability of conduction between circuit layers by the via hole. It is another object of the present invention to provide a method of manufacturing a wiring board that can form openings of each circuit layer constituting a part of a via hole with high positional accuracy.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a wiring board, wherein a circuit layer of an inner substrate formed by providing a circuit layer on a surface of an insulating resin layer is provided on an insulating substrate. A method for manufacturing a wiring board having a plurality of circuit layers 1 by laminating and forming a resin layer 2 and a circuit layer 1 and conducting between the circuit layers 1 through via holes 3 opened on the surface side. The circuit layer 1 to be electrically connected is provided with an opening 4 constituting a part of the via hole 3, and the diameter of the opening 4 of the circuit layer 1 disposed on the surface layer side of the circuit layer 1 to be electrically connected. Is formed to be 50 to 200 μm larger than the diameter of the opening 4 of the circuit layer 1 disposed on the inner layer side.

According to a second aspect of the present invention, in addition to the first aspect, the insulating resin layer 2 is irradiated with laser light using the circuit layer 1 in which the opening 4 is formed as a mask. In this case, a via hole 3 is formed.

According to a third aspect of the present invention, in addition to the configuration of the second aspect, a carbon dioxide laser is used as a laser beam for irradiating the insulating resin layer 2. .

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

The inner substrate 5 is formed by providing a circuit layer 1 on the surface of a resin laminate 1 such as a glass cloth base epoxy resin laminate, and is formed on both surfaces such as a copper-clad laminate by an additive method or a sub-transformer. The circuit layer 1 can be obtained by forming a circuit layer 1 on the surface layer of the insulating resin layer 2 by forming a circuit by an active method or the like.

The surface of one circuit layer 1a of the circuit layers 1 formed on the inner substrate 5 or both circuit layers 1a, 1
An insulating resin layer 2 and a circuit layer 1 are successively laminated and formed on the surface of a ', and a via hole 3 opening to the surface layer side is formed to form a wiring board.

As a method of forming the insulating resin layer 2 and the circuit layer 1, a metal foil with a resin formed by applying an insulating resin to one surface of a metal foil is laminated, and a circuit foil is formed on the metal foil of the metal foil with the resin. A method in which a metal foil is formed as a circuit layer 1 by patterning, or a liquid resin is applied and cured to form an insulating resin layer 2, and the circuit layer 1 is formed on the surface of the insulating resin layer 2 by a semi-additive method or the like. Can be adopted.

First, an insulating resin layer 2 is formed using a metal foil with resin.
A method for forming the circuit layer 1 will be specifically described.

After forming the circuit layer 1 on the inner substrate 5, a metal foil with resin is laminated and formed on the surface of the inner substrate 5. The resin-attached metal foil is formed by applying a thermosetting resin such as an epoxy resin to one side of a metal foil such as a copper foil to provide a resin layer which is in a semi-cured state. Then, the resin-coated metal foil is placed on the resin layer side, on the surface of one of the circuit layers 1a of the circuit layers 1 formed on the inner layer substrate 5, or on both circuit layers 1a, 1a.
a ′ can be laminated on the surface of the inner substrate 5 via the cured resin layer by heating and press-molding the resin layer to melt and cure the resin layer. At this time, the resin layer of the cured metal foil with resin is
It is formed as the insulating resin layer 2 of the wiring board. After the metal foil with resin is formed on the surface of the inner layer substrate 5 in this manner, patterning is performed on the metal foil with resin of the outer layer, and this metal foil is formed as the circuit layer 1. The patterning process can be performed by a normal procedure of applying, exposing, developing, and etching an etching resist on the surface of the metal foil. At the same time, the opening 4 is formed in the metal foil at the place where the via hole 3 is formed. After the insulating resin layer 2 and the circuit layer 1 are laminated and formed on the inner layer substrate 5 in this manner, if necessary, a metal foil with a resin is laminated on the surface of the newly formed circuit layer 1 on the resin layer side. Then, the insulating resin layer 2 and the circuit layer 1 are laminated and formed. Thus, the formation of the insulating resin layer 2 and the circuit layer 1 is sequentially repeated, and the circuit layer 1 is formed in a desired number of steps. However, in the circuit layer 1d formed closest to the surface, no circuit is formed at this stage, and only the opening 4 is formed.

Next, a method of sequentially laminating and forming an insulating resin layer 2 made of a cured liquid resin and a circuit layer 1 formed by a semi-additive method or the like on the surface of the inner substrate 5 will be specifically described.

A liquid resin is applied to the surface of one of the circuit layers 1a of the circuit layers 1 formed on the inner substrate 5 or the surfaces of both circuit layers 1a and 1a 'by a curtain coater, a roll coater, screen printing, or the like. As this liquid resin,
For example, 55 to 70 parts by weight of a brominated bisphenol A type epoxy resin monomer, 20 to 35 parts by weight of a bisphenol A type epoxy resin monomer, 20 to 35 parts by weight of a bisphenol A type epoxy resin oligomer, and a cyan curing agent 1
２2 parts by weight, 5-10 parts by weight of an amine curing agent,
35-60 wt% solids, preferably 52 wt% solids
A mixture prepared by blending a solvent such as methyl ethyl ketone and dimethylformamide can be used. When using a curtain coater, the liquid resin thus obtained has a viscosity of 60 to 300 cp.
s, preferably 110 cps, while applying it to the circuit layer 1 of the inner substrate 5 while adjusting with methyl ethyl ketone. After coating, the coating is dried by heating at 80 to 130 ° C. for 15 to 45 minutes, preferably at 120 ° C. for 30 minutes.
~ 160 ° C for 40-80 minutes, preferably 150 ° C for 5 minutes
The resin is cured by heating for 0 minutes to form the insulating resin layer 2.

After the surface of the insulating resin layer 2 is leveled using a polishing machine, electroless plating pretreatment, electroless plating, plating resist formation, electrolytic plating, plating resist peeling, and soft etching are sequentially performed. The circuit layer 1 is formed through a process using a semi-additive method. At the same time, an opening 4 is formed in the circuit layer 1 at the location where the via hole 3 is formed. After the insulating resin layer 2 and the circuit layer 1 are laminated and formed on the inner layer substrate 5 in this manner, the surface of the newly formed circuit layer 1 is coated with a liquid resin and cured to form the insulating resin layer 2 if necessary. Then, the circuit layer 1 is formed. Thus, the formation of the insulating resin layer 2 and the circuit layer 1 is sequentially repeated, and the circuit layer 1 is formed in a desired number of steps. However, the circuit layer 1 formed on the most surface side
At d, only the opening 4 is formed without forming a circuit at this stage.

The opening 4 formed by the two methods exemplified above is used for the circuit layer 1 to be electrically connected to the via hole 3.
Of these, the circuit layer 1 is provided on all circuit layers 1 except for the one disposed on the innermost layer side. In the present invention, the openings 4 formed in the circuit layer 1 to be electrically connected to each other through the via holes are formed such that the closer to the surface layer, the larger the diameter of the openings. Is formed so that the diameter formed on the opening side becomes larger. Here, the shape of the opening 4 is not limited to a circular shape, and various shapes such as a rectangular shape can be applied. In this specification, the diameter of the opening 4 is When the opening 4 has a shape other than a circle, it indicates the diameter of the circle circumscribing the opening 4. Further, it is preferable that the openings 4 formed in each circuit layer 1 are formed so as to be aligned so that the centers thereof are substantially linearly arranged along the direction in which the via holes 3 are formed. Insulating resin layer 2
Is not particularly limited, but in order to efficiently form via holes 3 by laser processing, 20 to 100 μm is required.
m. The opening 4 is also formed in the circuit layer 1 that does not ensure conduction, which is disposed between the circuit layers 1 to be connected to each other. This point will be described in detail later.

After the insulating resin layer 2 and the circuit layer 1 are successively formed on the inner layer substrate 5 as shown in FIG. 1A in this manner, the insulating resin layer 2 and the circuit layer 1 are exposed from the opening 4 of the circuit layer 1 formed on the outermost side. Is irradiated with the laser beam toward the insulating resin layer 2 to be decomposed, and the portion of the insulating resin layer 2 irradiated with the laser beam is decomposed and removed.
A via hole 3 is formed as shown in FIG. At this time, the laser light passes through the opening 4 in which the circuit layer 1 is formed with the circuit layer 1 disposed on the surface layer serving as a conformal mask, and the insulating layer formed on the inner layer side with respect to the circuit layer 1. The resin layer 2 is removed. Thereafter, the laser light reaches the circuit layer 1 which is disposed on the inner layer side of the circuit layer 1 and is to be electrically connected to the circuit layer 1, and the laser light is transmitted to the circuit layer 1 disposed on the inner layer side by the conformal mask. And passes through the opening 4 in which the circuit layer 1 is formed.
The insulating resin layer 2 formed on the inner layer side is further removed. As described above, the circuit layers 1 to be conducted through the via holes 3 are sequentially formed as a conformal mask, the inner surface is formed in multiple steps in a stepped manner, and the innermost layer of the circuit layers 1 to be conducted is formed on the bottom surface. In the case of FIG. 1, a via hole 3 exposing the circuit layer 1a of the inner substrate 5 is formed. Here, it is preferable to use a carbon dioxide gas laser as the laser light. In this case, the laser light is easily reflected by the circuit layer 1, particularly the circuit layer 1 formed of copper, and is easily absorbed by the insulating resin layer 2. And circuit layer 1
Can be reliably formed with the use of a conformal mask. After subjecting the via hole 3 to desmear treatment as necessary, the inner surface of the via hole 3 is subjected to panel plating for electroless plating and electrolytic plating, so that the inner surface of the via hole 3 has a desired circuit layer to be electrically connected. 1 is formed. By forming a circuit on the circuit layer 1 closest to the surface,
A wiring board is manufactured.

In the example shown in FIG. 1, three circuit layers 1 are further formed on the surface of one circuit layer 1a of the inner substrate 5 on which the circuit layers 1a and 1a 'are formed, and one circuit of the inner substrate 5 is formed. Layer 1
a, and all the circuit layers 1 formed on the surface layer side thereof are electrically connected to each other through the via hole 3.
The openings 4 are formed in all of the circuit layers 1 formed on the surface layer side of the one circuit layer 1a of the inner layer substrate 5, and the diameter of each opening 4 is adjusted to the opening 4 of the circuit layer 1 immediately inside. It was formed larger than the caliber of. In this way, conduction between all the circuit layers 1 can be ensured by one via hole 3, but the presence or absence of the openings 4 in each circuit layer 1 and the diameter of each opening 4 are controlled. Thereby, conduction only between desired circuit layers 1 can be secured.

For example, in the example shown in FIG. 2, the circuit layers 1a, 1
Three circuit layers 1 are further formed on the surface of one circuit layer 1a of the inner substrate 5 on which the a ′ is formed, and the circuit of the inner substrate 5 which is the innermost circuit layer 1 of the circuit layers 1 is formed. This is to ensure conduction between the three circuit layers 1b, 1c and 1d excluding the layer 1a. In such an example, a circuit layer 1a formed on the inner layer substrate 5 and a circuit layer 1b formed on the surface layer side therefrom,
Circuit layers 1a, 1c, 1c, 1d,
The opening 4 is not formed in 1b, and the opening 4 is formed only in the two circuit layers 1c and 1d on the surface side thereof, and the diameter of the opening 4 of the circuit layer 1d on the surface side is adjusted immediately. It is formed larger than the diameter of the opening 4 of the inner circuit layer 1c.

In the case where conduction with all the circuit layers 1 arranged on the inner layer side with respect to a certain circuit layer 1 is not ensured, the opening 4 is not formed in the circuit layer 1.

FIG. 3 shows an example of the circuit layers 1a and 1a '.
Are further formed on the surface of one circuit layer 1a of the inner layer substrate 5 on which the first layer, the third layer, and the fourth layer are formed from the inner side of the circuit layer 1. Eye circuit layers 1a, 1
Only c and 1d are made conductive to each other. In such an example, the openings 4 are formed in all the circuit layers 1b, 1c, 1d on the surface layer except for the circuit layer 1a formed on the inner layer substrate 5, which is the first circuit layer 1, from the inner layer side, Second circuit layer 1 from the inner layer side that does not secure conduction
The diameter of the opening 4b is formed larger than the diameter of the opening 4 of the third circuit layer 1c, which is the circuit layer 1 immediately on the surface side, and the circuit layers 1 to be electrically connected to each other. In a certain third circuit layer 1c and a fourth circuit layer 1d, the diameter of the opening 4 formed in the fourth circuit layer 1d on the surface side is determined by changing the diameter of the opening 4 immediately inside the third circuit layer 1d. Of the opening 4 of the circuit layer 1c. In this case, the diameter of the via hole 3 is set such that the third circuit layer 1c functions as a conformal mask on the inner layer side with respect to the third circuit layer 1c at the time of laser light irradiation. Of the opening 4 of the circuit layer 1c of the second layer, and smaller than the diameter of the opening 4 of the second circuit layer 1b. As a result, the second circuit layer 1b on the inner surface of the via hole 3 is not exposed, and conduction between the second circuit layer 1b and the other circuit layers 1a, 1c, 1d in the via hole 3 is not ensured. You can do so.

In the example shown in FIG. 4, four circuit layers 1 are formed, and the first, second, and fourth circuit layers 1a, 1a, Only 1b and 1d are electrically connected to each other. In this example, all the circuit layers 1b, 1 on the surface layer excluding the circuit layer 1a formed on the inner layer substrate 5, which is the first circuit layer 1, from the inner layer side.
The openings 4 are formed in the circuit layers c and 1d, and the diameter of the opening 4 of the third circuit layer 1c from the inner layer side where conduction is not secured is determined by the circuit of the fourth layer, which is the circuit layer 1 immediately above the circuit layer 1c. Tier 1
In the second circuit layer 1b and the fourth circuit layer 1d, which are formed to be larger than the diameter of the opening portion 4d and are to be electrically connected to each other, the fourth layer on the surface side The diameter of the opening 4 of the first circuit layer 1d is larger than the diameter of the opening 4 of the inner second circuit layer 1b. In this case, the diameter of the via hole 3 becomes the first diameter.
Between the first circuit layer 1a and the third circuit layer 1c, the opening of the fourth circuit layer 1d becomes a conformal mask when the laser light is irradiated. The diameter becomes the same as the diameter of the portion 4 and becomes smaller than the diameter of the third circuit layer 1c. As a result, the third circuit layer 1c on the inner surface of the via hole 3 is not exposed, and the third circuit layer 1c and the other circuit layers 1 in the via hole 3 are not exposed.
a, 1b, 1d can be prevented from being secured.

As shown in FIGS. 3 and 4, between the circuit layers 1 for which conduction is to be ensured, the circuit layer 1 for which conduction is not ensured.
Is arranged, the diameter of the opening 4 of the circuit layer 1 that does not secure conduction is arranged immediately on the surface layer side.
The diameter of the opening 4 of the circuit layer 1 for which conduction is to be ensured is formed larger than the diameter of the opening 4 so that the circuit layer 1 which does not ensure conduction is not exposed from the inner surface of the via hole 3.

In the example shown in FIGS. 1 to 4, the insulating resin layer 2 and the circuit layer 1 are sequentially laminated only on one of the circuit layers 1a and 1a 'formed on the inner layer base material 5. As shown in FIG. 5, when the insulating resin layer 2 and the circuit layer 1 are sequentially laminated and formed on both the circuit layers 1a and 1a 'on both sides of the inner layer substrate 5, one of the inner layer substrates 5 is used. The insulating resin layer 2 and the circuit layers 1b, 1c, and 1d laminated on the surface of the circuit layer 1a on the surface of the inner layer substrate 5 and the insulating resin layer laminated on the surface of the circuit layer 1a 'on the other surface of the inner layer base material 5 2 and the circuit layers 1b ', 1c', and 1d 'are formed with openings 4 and via holes 3 as illustrated in FIGS.

When the via hole 3 is formed as described above, the area of the inner surface of the via hole 3 increases, and since the inner surface of the via hole 3 is formed stepwise, there is a plating layer formed on the inner surface. When a stress is applied to the step surface, the peeling of the plating layer is suppressed by the frictional force at the other step surface, and the adhesion between the inner surface of the via hole 3 and the plating layer is improved, and the circuit layer 1 is removed. The reliability of conduction between them is improved. The openings 4 of the circuit layers 1 to be electrically connected to each other are formed to have a larger diameter toward the opening of the via hole 3, so that the positions of the openings 4 of the circuit layers 1 can be easily adjusted. In addition, poor conduction between the circuit layers 1 due to displacement of the opening 4 can be prevented. On the inner surface of the formed via hole 3, the entire outer periphery of the opening 4 of the circuit layer 1 on the inner layer side is exposed on the inner layer side of the opening 4 of the circuit layer 1 on the surface layer side. The exposed area of each circuit layer 1 to be electrically connected to each other increases. Therefore, the reliability of conduction between the circuit layers 1 by the plating layer formed on the inner surface of the via hole 3 can be improved. In addition, despite the formation of the via hole 3 for conducting the plurality of circuit layers 1, the inner shape of the via hole 3 is prevented from being complicated, and when the plating layer is formed on the inner surface of the via hole 3, the plating solution is not used. This makes it easier to spread over the entire inner surface of the hole 3, and in this regard, the reliability of conduction between the circuit layers 1 by the via hole 3 can be improved.

Here, the diameter of the opening 4 of the circuit layer 1 arranged on the surface layer of the circuit layers 1 to be electrically connected to each other in the via hole 3 is determined by the diameter of the circuit layer 1 arranged immediately on the inner layer side. The opening 4 is formed to be 50 to 200 μm larger than the diameter of the opening 4. That is, when the circuit layer 1 is laminated and formed, the forming accuracy of the opening 4 of the circuit layer 1 is ± 25 μm.
m and the opening 4 of the circuit layer 1 disposed on the surface layer side.
Is formed to be 50 μm or more larger than the diameter of the opening 4 of the circuit layer 1 disposed immediately on the inner layer side, the entire circumference of the outer edge of the opening 4 of the circuit layer 1 on the inner layer side is surely formed. It can be exposed on the inner surface. On the other hand, when the difference between the diameters of the openings 4 exceeds 200 μm,
The diameter of the opening 4 becomes too large, and the wiring density in the circuit layer 1 decreases. The diameter of the laser beam is
Generally, it is 350 μm, but in order to form the via hole 3 using the circuit layer 1 as a conformal mask,
If the diameter of the opening 4 is larger than 350 μm, the via hole 3 cannot be formed by a single irradiation of the laser beam, and even if the diameter of the opening 4 is smaller than 350 μm, the difference between the diameters will not increase. Is small, it is difficult to obtain a via hole 3 having a uniform shape because the inner periphery of the via hole 3 to be formed is tapered.
In order to form the via hole 3 having a uniform shape by irradiating the laser light once, it is preferable that the diameter of the opening 4 formed on the most surface layer side be 300 μm or less. The diameter of the other opening 4 is appropriately designed according to the diameter of the opening 4 formed on the side. On the other hand, when the internal shape of the via hole 3 is too narrow,
When the plating layer is formed on the inner surface of the via hole 3, the plating solution does not reach the inside and there is a possibility that a conduction failure may occur. The diameter of the opening 4 formed on the inner layer side is preferably 50 μm or more. In this case, the diameter of the inner peripheral surface of the via hole 3 becomes 50 μm or more at any depth, and At this time, the plating solution can be easily spread over the entire inner surface of the via hole 3, and the conduction between the circuit layers 1 by the via hole 3 can be reliably ensured.

[0031]

The present invention will be described below in detail with reference to examples.

(Example 1) As the inner substrate 5, FR-4
Using an equivalent glass cloth substrate copper-clad epoxy resin laminate (“R1766” manufactured by Matsushita Electric Works, Ltd.), applying an etching resist to the surface of the metal layer 2 of the inner substrate 5, exposing,
The circuit layer 1 was formed on the surface of the inner substrate 5 by developing and etching to pattern the metal layer 2 on the surface of the inner substrate 53.

Next, "R08" manufactured by Matsushita Electric Works, Ltd., prepared by applying an epoxy resin to a copper foil as a metal plate with a resin.
80 ", the resin-coated metal foil was laminated on the circuit layer 1 of the inner substrate 5 on the side of the resin layer,
The metal foil with resin was laminated on the inner layer substrate 5 by heating and pressing under the conditions of cm ² and 90 minutes. A patterning process was performed on the metal foil of the resin-coated metal foil, and a circular opening 4 having a diameter of 50 μm was formed to form the metal foil as the circuit layer 1. Further, a metal foil with resin was laminated on the surface of the newly formed circuit layer 1 on the side of the resin layer, and heated and pressed under the same conditions as the previous time to further laminate and mold the metal foil with resin. The metal foil of the resin-coated metal foil is aligned with the opening 4 formed in the inner layer side to have a diameter of 10 mm.
A metal opening is formed in the circuit layer 1 by forming a 0 μm circular opening 4.
Molded as

The opening 4 of the circuit layer 1 on the surface layer was irradiated with carbon dioxide laser light to form a via hole 3. After the inner periphery of the via hole 3 was desmeared, panel plating consisting of electroless plating and electrolytic plating was performed to form a plating layer having a thickness of 20 μm on the inner surface of the via hole 3.

Thereafter, application, exposure, development, and etching of an etching resist on the surface of the surface circuit layer 1 were performed to perform patterning processing to obtain a four-layer wiring board.

Example 2 A four-layer wiring board was obtained in the same manner as in Example 1, except that the diameter of the opening 4 formed in the circuit layer 1 on the surface layer side was 175 μm.

Example 3 A four-layer wiring board was obtained in the same manner as in Example 1 except that the diameter of the opening 4 formed in the circuit layer 1 on the surface layer side was changed to 250 μm.

Example 4 Example 1 was the same as Example 1 except that the diameter of the opening 4 formed in the inner circuit layer 1 was 80 μm, and the diameter of the opening 4 formed in the surface layer 1 was 180 μm. In the same manner as in the above, a four-layer wiring board was obtained.

Comparative Example 1 A four-layer wiring board was obtained in the same manner as in Example 1, except that the diameter of the opening 4 formed in the circuit layer 1 on the surface layer side was changed to 50 μm.

Comparative Example 2 A four-layer wiring board was obtained in the same manner as in Example 1 except that the diameter of the opening 4 formed in the circuit layer 1 on the surface layer side was changed to 80 μm.

(Evaluation of Via Hole Shape) With respect to each of the wiring boards obtained in Examples 1 to 4 and Comparative Examples 1 and 2, after forming the via hole 3 and before forming the panel plating, the inner periphery of the via hole 3 was viewed from above the opening. Observation is made to confirm whether or not the opening 4 formed in the circuit layer 1 of the inner layer substrate 5 is exposed over the entire circumference. Those were evaluated as "x".

(Evaluation of conduction reliability) Each wiring board obtained in Examples 1 to 4 and Comparative Examples 1 and 2 was subjected to
A heat cycle test was performed for 300 cycles in which heating was performed from a temperature of 55 ° C. to 125 ° C. over 30 minutes, and further cooling to a temperature of −55 ° C. over 30 minutes was performed for 300 cycles. The presence or absence of conduction between the layers 1 was inspected, and the case where conduction was maintained was evaluated as “○”, and the case where conduction was not maintained was evaluated as “×”. Here, the circuit pattern formed on the circuit layer 1 was a daisy chain pattern.

Table 1 shows the above results.

[0044]

[Table 1]

[0045]

As described above, according to the method for manufacturing a wiring board according to the first aspect of the present invention, the insulating resin layer and the circuit are formed on the circuit layer of the inner substrate formed by providing the circuit layer on the surface of the insulating resin layer. A method of manufacturing a wiring board for manufacturing a wiring board having a plurality of circuit layers by laminating and forming layers and conducting between circuit layers by via holes opened to the surface layer side, wherein the circuit layers conducted by the via holes In the circuit layer to be conducted, the diameter of the opening of the circuit layer arranged on the surface layer is set to the opening of the circuit layer arranged on the inner layer side. 50-20 than the diameter of the part
The via hole is formed to be larger by 0 μm, the area of the inner surface of the via hole is increased, and since the inner surface of the via hole is formed in a stepped shape, the adhesion between the inner surface of the via hole and the plating layer is improved, and the opening of the circuit layer is increased It is easy to adjust the position of the part forming position, and it is possible to prevent the position of the opening from being shifted.In addition, the inner surface of the formed via hole has the inner layer side of the inner layer side of the opening of the circuit layer on the surface layer side. The entire outer periphery of the opening of the circuit layer is exposed, and the exposed area of each circuit layer to be electrically connected to each other is increased on the inner surface of the via hole, and the inner surface shape of the via hole is complicated. When the plating layer is formed on the inner surface of the via hole, the plating solution can easily spread over the entire inner surface of the via hole, and thus is formed on the inner surface of the via hole. In which it is possible to improve the continuity reliability of each circuit layers by Tsu Ki layer.

According to a second aspect of the present invention, in addition to the first aspect, the insulating resin layer is irradiated with laser light using the circuit layer having the opening as a mask. A via hole is formed, and after lamination molding of all circuit layers is performed, a via hole for securing conduction between circuit layers can be formed by irradiating a laser beam. It can be reduced.

According to a third aspect of the present invention, in addition to the configuration of the second aspect, a carbon dioxide laser is used as a laser beam for irradiating the insulating resin layer, and the carbon dioxide laser is reflected by the circuit layer. The via hole is easily formed and easily absorbed by the insulating resin layer, and the via hole using the circuit layer as a mask can be easily formed.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views showing an example of an embodiment of the present invention.

FIG. 2 is a sectional view showing another example of the embodiment of the present invention.

FIG. 3 is a sectional view showing still another example of the embodiment of the present invention.

FIG. 4 is a sectional view showing still another example of the embodiment of the present invention.

FIG. 5 is a sectional view showing still another example of the embodiment of the present invention.

6A and 6B are diagrams showing a conventional technique, in which FIG.
(B) is a conceptual diagram explaining an arrangement state of an opening.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit layer 2 Insulating resin layer 3 Via hole 4 Opening 5 Inner substrate

Continuing on the front page (72) Inventor Masao Aozu 1048, Kadoma Kadoma, Osaka Prefecture Matsushita Electric Works Co., Ltd. 5E346 AA35 AA43 CC04 CC09 CC32 DD22 DD25 DD44 EE13 EE33 FF15 GG15 GG17 GG18 GG22 GG28 HH22 HH31

Claims (3)

[Claims] An insulating resin layer and a circuit layer are laminated and formed on a circuit layer of an inner substrate formed by providing a circuit layer on the surface of an insulating resin layer, and the circuit layers are electrically connected by a via hole opened on the surface side. A method of manufacturing a wiring board having a plurality of circuit layers by providing an opening that constitutes a part of the via hole in the circuit layer that is conducted by the via hole and conducting the conduction. Of the circuit layers to be formed, the diameter of the opening of the circuit layer arranged on the surface layer side should be 50 to 200 μm larger than the diameter of the opening of the circuit layer arranged on the inner layer side.
A method for manufacturing a wiring board, characterized by being formed large. 2. The method for manufacturing a wiring board according to claim 1, wherein a via hole is formed by irradiating the insulating resin layer with a laser beam using the circuit layer in which the opening is formed as a mask. 3. The method for manufacturing a wiring board according to claim 2, wherein a carbon dioxide laser is used as a laser beam for irradiating the insulating resin layer.