JP2000275610A - Liquid crystal display device and inspection method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a liquid crystal display device and inspection method therefor, capable of strictly and quantitatively detecting and discriminating defect and defective states of a liquid crystal panel, a signal driver, etc., without necessitating an external inspection device. SOLUTION: In a drive circuit, this liquid crystal display device comprises output circuit parts 22a, 23a for supplying a signal voltage for driving liquid crystal arranged corresponding to each signal line connected with a liquid crystal pixel, a mode change-over circuit 50a for supplying an output voltage monitoring line with the signal voltage applied to the signal line in the normal mode, for making a liquid crystal panel perform normal display operation based on a mode control signal and in the inspection mode, an inspection signal generating circuit 60 for supplying an inspection signal to an output circuit via a display signal line to which a display driving signal is applied, and an output voltage discriminating means 70 for discriminating an abnormal state of the liquid crystal panel based on the signal voltage of the signal line which is supplied to the output voltage monitoring line by the mode change-over circuit 50a in the inspection mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for inspecting the same, and more particularly, to a drive circuit, a joint portion between the drive circuit and the liquid crystal display panel, or a defective portion inside the liquid crystal display panel. 1. Field of the Invention The present invention relates to a liquid crystal display device having a function of inspecting a liquid crystal display and a method of inspecting the same.

[0002]

2. Description of the Related Art In recent years, with the rapid progress of the information society, a liquid crystal display (LC) has been used as a substitute for a monitor of a personal computer, a large display, and a television.
The spread of D) is remarkable. The liquid crystal display device has features such as thinness, light weight, and low power consumption as compared with a cathode ray tube (CRT), which has conventionally been the mainstream of displays, and is expected to become the mainstream of displays in the future. . For this reason, there is a need for a high-performance product with an even larger screen and a higher definition, and there is also a need for the establishment of an inspection technique corresponding to higher quality.

[0003] The configuration of a conventional liquid crystal display device will be briefly described with reference to the drawings. FIG. 8 is a thin film transistor (hereinafter abbreviated as TFT).
FIG. 1 is a block diagram showing a schematic configuration of a TFT type active matrix liquid crystal display device that uses a TFT as a switching element. 8, 10 is a liquid crystal display panel, 20 is a signal driver (also called a source driver), and 30 is a scanning driver (also called a gate driver). The liquid crystal display panel 10 includes pixel electrodes arranged in a matrix, a TFT having a drain terminal connected to the pixel electrode, and a signal line (source) extending in a column direction of the matrix and connected to source terminals of a plurality of TFTs. (Also called electrode wire) 20
a, a scanning line (also referred to as a gate electrode line) 30 a extending in the row direction of the matrix and connected to the gate terminals of the plurality of TFTs, and a common voltage Vcom disposed on the common line 40. A common electrode (also referred to as a counter electrode) applied through the pixel electrode, a pixel capacitor Clc filled with liquid crystal between the pixel electrode and the common electrode, and a storage added to the drain terminal of the pixel electrode in parallel with the pixel capacitor Clc. It is composed of a capacitance Cs. Here, a liquid crystal pixel is constituted by the TFT, the pixel capacitance Clc, and the storage capacitance Cs.

The signal driver 20 is an LC (not shown).
Based on the horizontal control signal supplied from the D controller, display signals of each color component of red (R), green (G), and blue (B) constituting the video display signal are stored in units of one row, and the corresponding signals are stored. A voltage is applied to each liquid crystal pixel via the signal line 20a. The scan driver 30 controls each scan line 3 based on a vertical control signal supplied from the LCD controller.
0a are sequentially applied to the liquid crystal pixels arranged at positions intersecting with the signal lines 20a.
The signal voltage is applied through the signal line 20a.

[0005] An LCD controller (not shown) generates a horizontal control signal and a vertical control signal based on the horizontal clock signal, the vertical clock signal, and the synchronization signal, and supplies them to the signal driver 20 and the scanning driver 30. As a result, a signal voltage is applied to the liquid crystal pixels at a predetermined timing to control the liquid crystal display panel 10 to display desired image information. In such a configuration, the scanning signal is turned on, a signal voltage is applied to the liquid crystal pixels connected to the selected scanning line 30a via the signal line 20a, and the potential of the signal voltage and the common voltage is applied to the pixel capacitance Clc. Is charged, and a display corresponding to a predetermined display signal is realized.

Next, the schematic configuration of the output circuit section of the signal driver will be briefly described with reference to the drawings. FIG.
FIG. 10 is a simplified circuit diagram showing an output circuit section of a signal driver. FIG. 10 is a specific configuration diagram of a sample-hold circuit and an amplifier circuit. As shown in FIG. 9, the signal driver 20 includes a plurality of stages of latch circuits. The signal driver 20 generates a timing pulse for a sample and hold operation based on a reference clock CK, and samples and displays each of the RGB display signals. Sample / hold circuits (hereinafter abbreviated as S / H) 22a and 22 for holding
b, 22c, and amplifier circuits (hereinafter abbreviated as AMP) 23a, 23b that generate signal power for driving liquid crystal pixels.
23c, and switches SW1, SW2, and SW3 that control ON / OFF of application of the output of the AMPs 23a, 23b, and 23c to the signal lines 20a, 20b, and 20c. Here, CK is an externally input reference clock, and OE is an output enable signal.

In FIG. 10, S / H 22a, 2
Although 2b, 22c and AMPs 23a, 23b, 23c are simplified for the sake of explanation, specifically, as shown in FIG. 10, they are configured with two systems of S / H and AMP. . Here, only the configuration of one output circuit is shown, but the same configuration is provided for each signal line.
As shown in FIG. 10, the switch Swa1 and the amplifier Amp
1 and a switch Swb1 connected in series.
Is connected to a connection point between the switch Swa1 and the amplifier Amp1 and a sample-and-hold capacitor (hereinafter abbreviated as S / H capacitor) C1 whose other end is connected to a low-potential power supply (ground potential) Vss. I have. On the other hand, the switch Swa2, the amplifier Amp2, and the switch Swb2 are connected in series.
An S / H capacitor C2 whose other end is connected to the low potential power supply Vss is connected to a connection point between the amplifier a2 and the amplifier Amp2.

As described above, the output circuit of the signal driver has two sets of S / S per signal line of the liquid crystal display panel.
It has a path consisting of an H capacitor, an amplifier and a switch,
Switches Swa1 and Swa2, and Switch Swb1
And Swb2, when one is ON, the other is O
The FF state is controlled, and the sampling operation of the display signal and the output operation of the hold data (charge stored in the S / H capacitor C2) are alternately performed.

In the defect inspection of the liquid crystal display device as described above, a probe pin of the inspection device is brought into contact with a terminal to be inspected before a peripheral circuit portion is joined to the liquid crystal display panel and assembled. Inspection signals are applied, and the lighting and display state of the liquid crystal display panel in response to the inspection signals are visually determined by a person in charge of inspection, and the operating state is electrically determined by an inspection device. On the other hand, in a liquid crystal display device having a structure in which a liquid crystal display panel and a peripheral circuit are integrally formed on the same substrate after the peripheral circuit portion is joined and assembled to the liquid crystal display panel, a signal driver is used. A predetermined display signal is applied to the liquid crystal display panel, and the inspected person visually checks the displayed and output image pattern, or visually grasps with an image processing device to determine the presence / absence of a defect. Is adopted.

The following is an outline of the latter inspection method.
This will be described with reference to the configuration diagram of the signal driver shown in FIG.
First, when a start pulse is input to the shift register 21, a timing pulse for controlling the sample / hold operation of the S / H 22a is output at a predetermined timing from the first-stage latch circuit based on the reference clock CK. S
/ H22a holds the signal voltage of the R display signal applied to the R signal line at this timing in the S / H capacitor in the S / H22a, and then holds it at the timing of the timing pulse output from the shift register 21. The output signal voltage is output to the AMP 23a. When the sample / hold processing of the signal voltage of the R display signal by the S / H 22a is completed, a timing pulse is then output to the S / H 22b to change the signal voltage of the G display signal applied to the G signal line to the S / H 22b. Then, the signal voltage held by the S / H capacitor is output to the AMP 23b at the next timing pulse.

The same sample and hold operation is performed for the B display signal. When the sample and hold processing of the signal voltage for one line of the liquid crystal display panel 10 is completed, the OE signal is output.
And simultaneously switch SW1 to SW3 to the ON state, and simultaneously apply the held signal voltage to the liquid crystal pixels via the signal lines 20a to 20c and the TFT. Thereby, the liquid crystal pixels are charged based on the applied signal voltage, and a predetermined image pattern is displayed. Therefore, R
By applying a predetermined inspection signal instead of each of the RGB display signals to each of the GB signal lines, an image pattern corresponding to the inspection signal is displayed on the liquid crystal display panel 10. The defect inspection of the liquid crystal display device is performed by visually grasping the image pattern displayed on the liquid crystal display panel 10 by an inspector or an image processing device and determining the presence or absence of a defect.

[0012]

As described above, the liquid crystal display panel is joined to the peripheral circuit portion and assembled, or the liquid crystal is formed by integrally forming the peripheral circuit together with the liquid crystal display panel on the same substrate. In the display device, since the probe pins cannot be directly contacted with the junction between the liquid crystal display panel and the signal driver due to the structure of the liquid crystal display device, a predetermined display signal (inspection signal) is applied from the signal driver. A predetermined image pattern is displayed, and the inspector visually or via an image processing device visually grasps the display state, thereby detecting defects or defects in the liquid crystal display panel or the signal driver itself, or In addition, it is necessary to determine a defect such as a short circuit between adjacent terminals at a junction between the liquid crystal display panel and the signal driver. Therefore, in the inspection method as described above,
Drive circuits such as signal drivers and scan drivers (drive I
C) There is a problem that it is not possible to strictly identify an internal defect or a defective portion at a junction between the drive circuit and the liquid crystal display panel. In addition, there is a problem that the content of the inspection is highly dependent on the visual sense of the person in charge of the inspection, so that strict and quantitative inspection results cannot be obtained, and that the inspection work is not efficient.

A defect inspection in a liquid crystal display device in which a liquid crystal display panel and peripheral circuits are integrally formed on the same substrate is described in, for example, Japanese Patent Application Laid-Open No. 10-260391. JP-A-10-260391 discloses that an ON / OFF control is performed by a signal voltage applied to an input bus and an output bus for inputting / outputting an inspection signal from the outside via a signal pad and a data bus (bus line). There is known an inspection method in which a MOS transistor is provided in a peripheral circuit and a defective state of a driver, a disconnection of a data bus, and a short-circuit state are determined based on an inspection signal output to an output bus. However, JP-A-10-260
In the test circuit described in Japanese Patent No. 391, a signal pad for inputting / outputting a test signal must be provided for each data bus. In addition, a test signal to be applied to an input bus is generated, and the test signal is generated via an output bus. There is a problem that an external inspection device for determining the output of the output inspection signal must be connected to the signal pad.

Therefore, the present invention solves the above problems,
It is possible to strictly and quantitatively detect and judge a defect or a defect of the liquid crystal display panel or the signal driver itself, or a defective state at a joint portion between the liquid crystal display panel and the signal driver, without requiring an external inspection device. An object of the present invention is to provide a liquid crystal display device and an inspection method thereof.

[0015]

According to the present invention, a signal voltage for driving the liquid crystal pixels is applied to a bus line connected to a plurality of liquid crystal pixels arranged in a matrix. In a liquid crystal display device having a driving circuit, the driving circuit includes a normal operation mode in which a liquid crystal display panel including the plurality of liquid crystal pixels performs a normal display operation, and an inspection mode in which at least an abnormal state of the liquid crystal display panel is inspected. Mode switching means for extracting a signal voltage applied to the bus line connected to the liquid crystal pixel in the test mode, and generating a test signal in the test mode and applying the test signal to the bus line. Test signal generating means, and in the test mode, based on the signal voltage extracted by the mode switching means, Determining means for determining an abnormal state of the serial LCD panel, and further comprising a.

Further, in the liquid crystal display device according to the second aspect, in the liquid crystal display device according to the first aspect, the driving circuit includes:
RGB signal lines to which red (R), green (G), and blue (B) color signals based on a video display signal are applied, and RGB signal lines are provided corresponding to each of the RGB signal lines. A plurality of sample-and-hold circuits that individually capture and hold each color signal, and each sample-and-hold circuit based on a reference clock.
A shift register for generating and outputting a timing pulse for controlling an operation timing of capturing and holding each of the RGB color signals in the hold circuit;
A plurality of amplifier circuits that supply the RGB color signals held in the hold circuit as drive power to signal lines connected to the liquid crystal pixels, and control output timings from the amplifier circuits to the signal lines. The mode switching means controls the operation of each of the sample and hold circuits, and extracts the signal voltage applied to each of the signal lines during the test mode. The inspection signal generation means applies the inspection signal to each of the RGB signal lines in the inspection mode.

In the liquid crystal display device according to a third aspect, in the liquid crystal display device according to the second aspect, the mode switching means is configured to output the timing pulse from the shift register to the sample and hold circuit in an inspection mode. A first logic circuit that cuts off the output of the first logic circuit, a second logic circuit that extracts a signal voltage applied to each of the signal lines based on the timing pulse, and an operation of the first and second logic circuits. It has a mode switching control line to which a mode switching signal for switching the state is applied, and an output voltage monitor line for outputting the extracted signal voltage to the determination circuit. According to a fourth aspect of the present invention, in the liquid crystal display device of the second or third aspect, the mode switching means sequentially extracts the signal voltage applied to each of the signal lines, and time-divisionally extracts the signal voltage. The data is output to the determination circuit. According to a fifth aspect of the present invention, in the liquid crystal display device according to any one of the second to fourth aspects, the inspection signal generation unit generates an inspection signal corresponding to the video display signal, The signal is applied to each of the RGB signal lines at a timing.

According to a sixth aspect of the present invention, in the liquid crystal display device according to any one of the second to fifth aspects, the inspection signal generating means includes an H level and an L level corresponding to the video display signal. Wherein the test signal of the H level and the test signal of the L level are alternately inverted and applied to the signal lines arranged adjacent to each other. According to a seventh aspect of the present invention, in the liquid crystal display device according to any one of the second to sixth aspects, the inspection signal generation unit generates an H level inspection signal corresponding to the video display signal. A first signal voltage generation circuit for outputting to each of the RGB signal lines, and a second signal voltage generation circuit for generating an L-level inspection signal corresponding to the video display signal and outputting the same to each of the RGB signal lines Circuit, the first and second signal voltage generation circuits, and the RGB
And a timing generating circuit for outputting a control signal for controlling a connection state with each signal line.

According to an eighth aspect of the present invention, in the liquid crystal display device according to any one of the second to seventh aspects, the determining means includes a signal voltage of each signal line extracted by the mode switching means. And a preset reference voltage. If the signal voltage does not satisfy the reference voltage, it is determined that the liquid crystal display panel is abnormal. According to a ninth aspect of the present invention, in the liquid crystal display device according to any one of the second to seventh aspects, the determining means includes a signal voltage of each signal line extracted by the mode switching means, Compare the set H level and L level reference voltages,
When the signal voltage does not belong to either the H level or the L level, it is determined that the liquid crystal display panel is abnormal. According to a tenth aspect of the present invention, in the liquid crystal display device according to any one of the second to seventh aspects, the determining means determines that a signal voltage of each signal line extracted by the mode switching means is equal to Divided H
It is characterized in that it is detected whether or not the level and the L level are alternately inverted.

According to the present invention, there is provided a method for testing a liquid crystal display device, comprising applying a signal voltage for driving the liquid crystal pixels to a bus line connected to a plurality of liquid crystal pixels arranged in a matrix. A test method for applying a test signal to the bus line from a test signal generating means provided in the drive circuit, and holding a signal voltage of the test signal, wherein the drive circuit A process for extracting the signal voltage of the test signal held in the bus line by a mode switching unit provided in the control circuit; and a determination unit provided in the drive circuit based on the extracted signal voltage. And a process of determining an abnormal state of the liquid crystal display panel. According to a twelfth aspect of the present invention, there is provided an inspection method of a liquid crystal display device, wherein the method of inspecting a liquid crystal display device according to the eleventh aspect includes the liquid crystal display device according to any one of the second to tenth aspects. That is, the liquid crystal display device and the inspection method thereof according to the present invention include a defect inspection function in the drive circuit of the liquid crystal display panel, and utilize the internal operation of the drive circuit to obtain a defect state of the liquid crystal display panel and the drive circuit. Is electrically detected, a strict and quantitative defect inspection is performed, and a defective portion is specified.

[0021]

Next, an embodiment of a liquid crystal display device according to the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing an embodiment in which the liquid crystal display device according to the present invention is applied to a signal driver. Here, the same components as those of the conventional configuration shown in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 1, the signal driver according to the present embodiment has a conventional configuration in which an output circuit section (shift register 21, S / Hs 22a to 22c, and AMPs 23a to 23) of the signal driver shown in FIG.
c) includes a mode setting signal line I / O, operation mode switching circuits 50a, 50b, 50c, and a test signal generation circuit 6.
0, the output voltage monitor line ML, and the output voltage determination circuit 70
And an information processing device 80 including a monitor and the like. Here, the signal driver constitutes a drive circuit, the operation mode switching circuits 50a, 50b, 50c constitute mode switching means, the inspection signal generation circuit 60 constitutes inspection signal generation means, and the output voltage determination circuit 70 Configure means.

Hereinafter, each component will be described specifically. (Operation Mode Switching Circuit) FIG. 2 is a circuit diagram showing an example of the operation mode switching circuit. Here, the operation mode switching circuits 50a, 50b, 50c shown in FIG.
Since they have the same circuit configuration, only one output circuit unit and one operation mode switching circuit will be described. As shown in FIG. 2, the operation mode switching circuit 50
Are a first AND circuit 51 and a second AND circuit 52 between the shift register 21 and the S / H 22 of each output circuit section.
, An inverting circuit (inverter) 53, and an extraction control switch SWE. Here, the first A
The ND circuit 51 forms a first logic circuit, and a second AND circuit
The circuit 52, the inverting circuit 53, and the extraction control switch SWE form a second logic circuit.

The AND circuit 51 includes a timing pulse output from the shift register and a mode setting signal line I / O.
Is a two-input AND circuit that receives a mode setting signal (mode switching signal) applied to the S / H 22 and supplies a logical output to the S / H 22 as a control signal for a sample-and-hold operation. On the other hand, the AND circuit 52 receives the timing pulse output from the shift register and the mode setting signal inverted by the inverter 53, and supplies a logical output to the extraction control switch SWE as a control signal for switch opening / closing operation. Is an AND circuit. The extraction control switch SWE controls the connection state between the signal line 20 and the output voltage monitor line ML in the test mode based on the output from the AND circuit 52. Therefore, the operation mode switching circuit 50 outputs a control signal based on the timing pulse from the shift register 21 to S based on the mode setting signal applied via the mode setting signal line I / O.
/ H22 to sample and hold the display signal,
A normal operation mode in which a signal voltage based on the display signal is applied to the signal line 20, and a control signal based on a timing pulse from the shift register 21 are supplied to the extraction control switch SWE to apply a signal applied to the signal line 20. It has a function of switching between a test mode in which a voltage is extracted (supplied) to the output voltage monitor line ML.

(Test Signal Generating Circuit) FIG. 3 is a circuit diagram showing an example of the test signal generating circuit. In FIG.
The inspection signal generation circuit 60 includes a resistor R61 for generating a voltage,
Timing generator 62 and buffers BUF1, BUF2
And output control switches SWH1-SWH3, SWL1-
SWL3. The voltage generating resistor R61 is composed of one or more resistors connected between the high potential power supply VCC and the low potential power supply GND, and each contact N
The H-level and L-level reference voltages extracted from H and NL are amplified to predetermined signal powers by buffers BUF1 and BUF2, respectively, and used as test signals as output signals from output control switches SWH1 to SWH3 or RGB via SWL1 to SWL3. Output to each signal line.

The timing generator 62 generates a predetermined timing pulse based on a reference clock CK equivalent to that input to the shift register 21, and controls the opening / closing operation of the output control switches SWH1 to SWH3 and SWL1 to SWL3. Output as a control signal. The output control switches SWH1 to SWH3 and SWL1 to SWL3 are output control switches SWH1 connected to the R signal line based on the timing pulse output from the timing generator 62.
And the output control switch S connected to the SWL1 and G signal lines
Only one set of the output control switches SWH3 and SWL3 connected to the signal lines WH2 and SWL2 and the B signal line is driven, and the pair of output control switches SWH1 and SWL1, the pair of output control switches SWH2 and SWL2, and the pair of output control switches SWH3 and SWL3 are inverted. The opening / closing operation is controlled to operate and the RG
An inspection signal of a predetermined voltage level (H / L level) is output to each signal line of B. Therefore, the test signal generation circuit 6
0 is the operation mode switching circuit 5 based on the timing pulse output from the timing generator 62.
Prior to switching to the inspection mode by 0, a function of outputting an inspection signal (voltage level) in a predetermined pattern to the S / H 20 via each signal line of RGB. In addition,
The pattern of the inspection signal generated and output by the inspection signal generation circuit 60 will be described later.

(Output Voltage Determination Circuit) FIG. 4 is a circuit diagram showing an example of the output voltage determination circuit. As shown in FIG. 4, the output voltage determination circuit 70 includes a resistor R for generating a reference voltage.
71, R72, R73 and comparators COMP1, C
It is configured to include an OMP 2 and a serial I / O (SIO) 74. Reference voltage generating resistors R71, R7
2, R73 is composed of one or more resistors connected in series between the high potential power supply VCC and the low potential power supply GND, and has an H level reference voltage (3 /
4 VCC) and the L level reference voltage (1/4 VCC)
+ Input of comparator COMP1 and CO
Supply to the-input of MP2. On the other hand, the comparator COM
A signal voltage extracted from the signal line 20 is applied to the-input of P1 and the + input of COMP2 to the output voltage monitor line M.
L. This allows the comparator CO
When the signal voltage of the signal line 20 is equal to or lower than the H level reference voltage, MP1 indicates an H level (abnormality determination) as a comparison result.
When the signal voltage of the signal line 20 is equal to or higher than the L level reference voltage, the comparator COMP2 outputs an H level (abnormality determination) signal as a comparison result.

That is, the signal voltage of the signal line 20 supplied via the output voltage monitor line ML is a signal level (H level is 3/4 VCC) effective for driving the liquid crystal pixels.
When the L level is equal to or less than 1/4 VCC), an L level (normal discrimination) signal is output from the pair of comparators COMP1 and COMP2, while the signal voltage is 1
When the intermediate potential is equal to or higher than / 4 VCC and equal to or lower than ／ VCC, an H level (abnormality determination) signal is output from the comparators COMP1 and COMP2. Serial I / O7
4 outputs the comparison result sequentially output from the pair of comparators COMP1 and COMP2 to the information processing device 80 as a determination signal based on the reference clock CK.

Therefore, the output voltage determination circuit 70 is connected to the signal line 20 supplied through the output voltage monitor line ML.
Has a function of judging the voltage level of the signal voltage of the second signal and judging whether or not the voltage level is normal. It should be noted that the information processing device 80 does not illustrate the case where the determination signal output from the serial I / O 74 is different from an expected value prepared in advance, that is, is an H-level determination signal indicating a voltage abnormality. The occurrence of abnormal voltage is notified and displayed via a monitor device or the like which is omitted. The information processing device 80
Will be described later.

Next, the operation processing of the signal driver according to this embodiment will be described. The signal driver according to the present embodiment includes a normal operation mode for applying a predetermined display signal to a signal line, an inspection voltage application mode for applying an inspection signal,
And a voltage level determination mode for extracting a signal voltage or a test signal voltage applied to the signal line to determine a voltage level. Hereinafter, each operation mode will be described with reference to FIGS. (Normal Operation Mode) First, a normal operation mode in which a normal display signal is applied to a signal line will be described.

First, the mode setting signal applied to the mode setting signal line I / O is held at the H level. At this time,
As shown in FIGS. 1 and 2, the operation mode switching circuit 5
Since the mode setting signal of the H level is applied to one input of the AND circuits 51a to 50c and the timing pulse output from the shift register 21 is applied to the other input, the logical output of the AND circuit 51 is , Changes to H / L according to the timing pulse, and is supplied to the S / Hs 22a to 22c as a control signal, and the display signals set on the RGB signal lines are sequentially sampled at the timing set by the shift register 21.・ Perform a hold operation. Also, since the mode setting signal is inverted and applied to one input of the AND circuit 52, the logical output of the AND circuit 52 is always at L level, and the extraction control switch SWE
Is turned off, and the signal lines 20a to 20c and the output voltage monitor line ML are cut off.

Here, RG by S / Hs 22a to 22c
Specifically, the sample and hold operation of the B display signal is as follows.
The pulse of the start signal input to the shift register 21 is output to the first-stage latch by the reference clock CK, and selects and drives the operation mode switching circuit 50a.
Then, as described above, the timing pulse from the shift register 21 is supplied to the S / H 22a, and the signal voltage of the display signal set on the R signal line is accumulated and held in the S / H capacitor. , AMP 23a. After the sample / hold operation by the S / H 22a is completed, a start signal is output to the second-stage latch by the next reference clock CK, and the shift register 21
The operation mode switching circuit 50b is selected and driven by the timing pulse from
22b. Similarly to the sample / hold operation of the S / H 22a, the signal voltage of the display signal set on the G signal line by the S / H 22b is accumulated and held in the S / H capacitor in the S / H 22b.

The same operation as above is repeated, and all S / S
H (here, S / H 22a to 22c for convenience)
When the sample and hold operation of the display signal to
Switches SW1 to SW by output enable signal OE
3 are simultaneously turned on, and S / Hs 22a to 22
c are held in the AMPs 23a to 23c
Are applied to the respective signal lines 20a to 20c at the same time, the pixel capacitance is charged according to the signal voltage, and a predetermined image pattern is displayed and output. Although the sample-and-hold operation is simplified here, it has two sampling-and-hold circuits as described in the prior art. The operation of alternately sampling and holding the display signal voltage is performed.

(Test Voltage Application Mode) Next, the test voltage application mode for applying the signal voltage of the test signal to the signal line will be described. As in the normal operation mode described above, first, the mode setting signal applied to the mode setting signal line I / O is held at the H level. At this time, shift register 2
1 is output from the S / H 22a to 22 via operation mode switching circuits 50a to 50c.
c, the test signal voltage output from the test signal generating circuit 60 and applied to each of the RGB signal lines is set at the timing set by the shift register 21.
H22a to 22c sequentially sample and hold. When the sample and hold operation of the test signal voltage to all the S / Hs 22a to 22c is completed, the switches SW1 to SW3 are simultaneously turned on by the output enable signal OE.
The state is switched to the state, and the inspection signal voltages held in the S / Hs 22a to 22c are simultaneously applied to the signal lines 20a to 20c via the AMPs 23a to 23c.

Here, the inspection signal set to each of the RGB signal lines is, as shown in FIG.
Voltage generating resistor R61 and buffers BUF1 and BU
An inspection signal having a voltage level (H / L level) corresponding to a normal RGB display signal is generated by F2, and the output control switches SWH1 to SWH1 to SWL1 to SWL1 to SWL1 according to the timing pulse output from the timing generator 62. 3
Are turned on / off to output and set an inspection signal having a predetermined pattern to each of the RGB signal lines.
As a pattern of the inspection signal, for example, when a short-circuit state of an adjacent signal line described later is detected, the signal voltages applied to the adjacent signal lines are alternately inverted between H level and L level. The output control switches SWH1 to SWH1 and SWL1 to SWL1 to 3 are operated in such a manner as to be in the state as described above. When detecting a defective state of a specific signal line or an output circuit portion of a signal driver, a test signal voltage applied to a signal line to be inspected is set to, for example, H level, and applied to another signal line. The test signal generation circuit 60 is set such that the test signal voltage to be set is, for example, L level.

(Voltage Level Judgment Mode) Next, a voltage level judgment mode for extracting a signal voltage or a test signal voltage applied to a signal line and judging a voltage level will be described with reference to the drawings. FIG. 5 is a timing chart when the determination result of the voltage level is normal.
FIG. 6 is a conceptual diagram showing a state in which a short circuit has occurred between signal lines, and FIG. 7 is a timing chart in a case where the determination result of the voltage level is abnormal. As described above, in the normal operation mode or the test voltage application mode, the mode setting signal is applied via the mode setting signal line I / O in a state where a predetermined signal voltage or a test signal voltage is applied to the signal line and held. When the level is switched from the H level to the L level, the start signal is sequentially shifted in the shift register 21 based on the reference clock CK, and the timing pulse output from the shift register 21 is controlled by each extraction control in the operation mode switching circuits 50a to 50c. Each of the signal lines 20a to 20c and the output voltage monitor line M
L are connected in a time-division manner, and the signal voltages applied to and held on the signal lines 20a to 20c or the test signal voltages are sequentially supplied to the output voltage monitor line ML serially by the S / Hs 22a to 22c.

The operation mode switching circuits 50a to 50a
Specifically, the switching operation in the 50c is performed by the AND circuit 5c.
When the mode setting signal I / O, which is one of the two inputs, goes to L level, its logical output always goes to L level.
The sample / hold operation in / H22a to 22H does not function, and the signal voltage applied to the signal lines 20a to 20c or the test signal voltage is held at that point. On the other hand, since the mode setting signal I / O is inverted to the H level by the inverter 53 at one input of the AND circuit 52, the logical output thereof is controlled by the extraction control (H / L) of the shift register 21. The switch SWE is turned on / off. Therefore, based on the timing pulse from the shift register 21, the signal voltage applied to the signal lines 20a to 20c or the test signal voltage is sequentially extracted in a time division manner on the output voltage monitor line ML, and the output voltage determination is performed. The signal is supplied to the circuit 70.

Next, the process of determining the output voltage applied in the above-described voltage level determination mode will be described.
As shown in FIG. 4, the output voltage determination processing according to the present embodiment compares the output voltage captured by the output voltage determination circuit 70 via the output voltage monitor line ML with the comparator COMP.
1. H level (3/4) which becomes a reference voltage by COMP2
VCC) and L level (1/4 VCC) to determine the presence or absence of an abnormal voltage. That is, the output voltage is at a voltage level (3/4 VCC) belonging to the H level or the L level.
In this case, as shown in FIG. 5, an L-level signal is output as a comparison result, and an intermediate level that does not belong to either the H level or the L level is output as shown in FIG. When the signal has the potential voltage level, an H level signal is output as a comparison result as shown in FIG.

Here, a more detailed description will be given of the case where the foreign matter X exists between the adjacent signal lines 20b and 20c as shown in FIG. Here, as described above, for example, the H level is applied to the odd lines and the L level is applied to the even lines so that the inspection signal voltages applied to the adjacent signal lines are alternately inverted by the inspection signal generation circuit 60. It is assumed that it is set to In this case, in the determination period 2 by the output voltage determination circuit 70, the signal line 2
The H-level inspection signal voltage applied to the signal line 0b and the L-level inspection signal voltage applied to the signal line 20c are short-circuited by the foreign matter X, thereby making the signal voltage uniform as shown in FIG. And the same intermediate potential (1
/ 2VCC). Also in the determination period 3, the L-level inspection signal voltage applied to the signal line 20b and the H-level inspection signal voltage applied to the signal line 20c are short-circuited by the foreign matter X, so that the signal voltage is reduced. Uniform and the same intermediate potential (1/2 VC
C) is shown.

Therefore, the signal voltages of the signal lines 20b and 20c in the determination periods 2 and 3 are compared with the reference voltages of the H level and the L level by the comparators COMP1 and COMP2 described above, and the determination result of the H level (abnormality determination) is obtained. Is output. Based on such a determination result, an abnormal state in which the signal voltage indicates the intermediate potential is determined in the signal lines 20b and 20c in the determination periods 2 and 3, and a short-circuit state occurs immediately between the signal lines 20b and 20c. Is specified.

In the above-described embodiment, the state where the intermediate potential is detected by two consecutive signal lines is detected, and the state where the signal lines are short-circuited is determined. The present invention is not limited to this. By detecting whether a signal voltage in one independent signal line matches a predetermined test signal voltage, or by detecting whether the voltage level indicates an intermediate potential, An abnormal state of the signal line alone can also be determined. For example, when an H-level inspection signal is applied to a signal line to be inspected and the signal voltage determined by the comparator is at an intermediate potential or L level, the signal line is set to GN.
It can be determined that there is a defective state in contact with a low-potential power supply such as a D level, or that the driving capability of the signal driver AMP is defective. Further, in the above-described embodiment, the case where the present invention is applied to a signal driver has been described. However, the present invention is not limited to this, and may be applied to a scanning driver. Needless to say, the present invention may be applied to both the scanning driver and the scanning driver.

[0041]

As described above, according to the first, eleventh or twelfth aspect of the present invention, the drive circuit of the liquid crystal display device switches between the normal operation mode and the inspection mode of the liquid crystal display panel and the bus line. A mode switching unit for extracting a signal voltage applied to the LCD, a test signal generating unit for applying a test signal to the bus line, and a determination unit for determining an abnormal state of the liquid crystal display panel based on the extracted signal voltage. With the circuit, the LCD panel is inspected using the inspection signal generated inside the drive circuit without the need for an external inspection device that requires high-precision probing, etc. Based on this, the abnormal part can be specified. Therefore, not only the liquid crystal module stage but also the product stage can execute the inspection process as needed, and the failure of the inside of the liquid crystal display panel and the drive circuit can be electrically detected. As compared with a conventional inspection method that depends on the above, a strict and quantitative inspection result can be obtained, and an abnormal portion can be efficiently specified.

According to the second aspect of the present invention, the signal driver of the liquid crystal display device is provided with the test circuit, and the test signal is supplied to the signal driver.
By applying to the signal lines via the RGB signal lines and the sample-and-hold circuit used in the normal mode, not only in the liquid crystal display panel, but also in the signal driver itself and the joint between the signal driver and the liquid crystal display panel. Since the resulting abnormal state can be detected as an inspection target, more strict and various inspection processes can be executed. According to the third aspect of the present invention, the first logic circuit controls the output of the timing pulse to the sample and hold circuit, and the second logic circuit controls the extraction of the signal voltage applied to the signal line. Is controlled by the mode switching signal applied to the mode switching control line, so that the normal mode and the inspection mode can be switched with one control line, so that the inspection process can be performed with a simple and small circuit area. A liquid crystal display device that can be provided.

According to the fourth aspect of the present invention, a signal voltage applied to each signal line is sequentially extracted and output to the determination circuit in a time-sharing manner, so that one monitor line is output. Since the signal voltage of the signal line can be output to the determination circuit, it is possible to provide a liquid crystal display device that can easily perform the inspection process with a simple and small circuit area. According to the fifth, sixth or seventh aspect of the invention, the inspection signal generation means has a configuration in which an inspection signal corresponding to a video display signal is generated and applied to each of the RGB signal lines at a predetermined timing. As a result, since an inspection signal of an arbitrary pattern can be generated and output, an abnormal state of a single signal line or an adjacent signal line can be detected satisfactorily.

According to the present invention, the judging means judges the abnormal state of the liquid crystal display panel by comparing the signal voltage of each signal line with a preset reference voltage. Accordingly, since the signal voltage of each signal line can be determined strictly, an abnormal state can be easily specified. According to the tenth aspect of the present invention, the determination means detects whether or not the signal voltage of each signal line is alternately inverted in an H-level and an L-level in a time-sharing manner, thereby detecting an adjacent signal line. Since the mutual signal voltage can be determined, the short-circuit state between the signal lines can be easily detected without the probe pins coming into contact with the junction between the liquid crystal display panel and the signal driver.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment in which a liquid crystal display device according to the present invention is applied to a signal driver.

FIG. 2 is a circuit configuration diagram illustrating an example of an operation mode switching circuit.

FIG. 3 is a circuit diagram illustrating an example of a test signal generation circuit.

FIG. 4 is a circuit configuration diagram illustrating an example of an output voltage determination circuit.

FIG. 5 is a timing chart when a determination result of a voltage level is normal.

FIG. 6 is a conceptual diagram showing a state in which a short circuit occurs between signal lines.

FIG. 7 is a timing chart when the determination result of the voltage level is abnormal.

FIG. 8 is a block diagram showing a schematic configuration of a TFT type active matrix liquid crystal display device.

FIG. 9 is a simplified circuit diagram showing an output circuit section of a signal driver.

FIG. 10 is a specific configuration diagram of a sample-hold circuit and an amplifier circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Liquid crystal display panel 20 Signal driver 20a-20c Signal line 21 Shift register 22, 22a-22c S / H 23, 23a-23c AMP 50, 50a-50c Operation mode switching circuit 60 Test signal generation circuit 70 Output voltage judgment circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA59 JA24 JB77 MA57 MA58 NA16 NA30 PA06 2H093 NA16 NA43 NA64 NC12 NC16 NC22 NC23 NC25 NC34 NC59 ND17 ND34 ND53 ND56 5C006 AA22 AC24 AF42 AF43 AF51 AF53 AF54 AF64 BB16 BC03 BC11 BC BF25 BF26 EB01 FA00 5C080 AA10 BB05 CC03 DD15 EE30 FF11 GG02 JJ02 JJ03 JJ04 5G435 AA17 BB12 KK05 KK10

Claims (12)

[Claims] 1. A liquid crystal display device having a driving circuit for applying a signal voltage for driving the liquid crystal pixels to a bus line connected to a plurality of liquid crystal pixels arranged in a matrix, wherein the driving circuit comprises: Switching between a normal operation mode in which a liquid crystal display panel including the plurality of liquid crystal pixels is normally displayed and an inspection mode for inspecting at least an abnormal state of the liquid crystal display panel, Mode switching means for extracting a signal voltage applied to the connected bus line; test signal generation means for generating a test signal during the test mode and applying the test signal to the bus line; Judgment for judging an abnormal state of the liquid crystal display panel based on the signal voltage extracted by the switching means A liquid crystal display device comprising: the stage, a. 2. The driving circuit according to claim 1, wherein each of the RGB signal lines to which each of red (R), green (G), and blue (B) color signals based on a video display signal is applied, and each of the RGB signal lines. Is provided corresponding to each of the RGB color signals,
A plurality of sample-and-hold circuits for holding, a shift register for generating and outputting a timing pulse for controlling an operation timing of capturing and holding each of the RGB color signals in each of the sample-and-hold circuits based on a reference clock; A plurality of amplifier circuits for supplying the respective RGB color signals held in the respective sample and hold circuits as drive power to the respective signal lines connected to the liquid crystal pixels, and outputting from the respective amplifier circuits to the respective signal lines; A switch unit for controlling timing, wherein the mode switching unit controls the operation of each of the sample and hold circuits, and in the test mode,
2. The liquid crystal according to claim 1, wherein a signal voltage applied to each of the signal lines is extracted, and the inspection signal generating unit applies the inspection signal to each of the RGB signal lines in the inspection mode. Display device. 3. A mode switching unit, comprising: a first switch for interrupting output of the timing pulse from the shift register to the sample and hold circuit in a test mode.
Logic circuit, a second logic circuit for extracting a signal voltage applied to each signal line based on the timing pulse, and a mode switch for switching and controlling an operation state of the first and second logic circuits 3. The liquid crystal display device according to claim 2, further comprising: a mode switching control line to which a signal is applied; and an output voltage monitor line for outputting the extracted signal voltage to the determination circuit. 4. The liquid crystal display according to claim 2, wherein the mode switching means sequentially extracts the signal voltage applied to each of the signal lines and outputs the signal voltage to the determination circuit in a time-division manner. apparatus. 5. The inspection signal generation unit according to claim 2, wherein the inspection signal generation unit generates an inspection signal corresponding to the video display signal and applies the inspection signal to each of the RGB signal lines at a predetermined timing. 5. The liquid crystal display device according to any one of 4. 6. The test signal generating means generates test signals of H level and L level corresponding to the video display signal, and outputs the test signals of H level and L level to the adjacent signal lines. 6. The liquid crystal display device according to claim 2, wherein signals are alternately inverted and applied. 7. The inspection signal generating means generates an H-level inspection signal corresponding to the video display signal, and
A first signal voltage generation circuit that outputs to each of the B signal lines, a second signal voltage generation circuit that generates an L-level inspection signal corresponding to the video display signal, and outputs the inspection signal to each of the RGB signal lines; And a timing generation circuit for outputting a control signal for controlling a connection state between the first and second signal voltage generation circuits and each of the RGB signal lines. 7. The liquid crystal display device according to any one of 6. 8. The determination means compares a signal voltage of each signal line extracted by the mode switching means with a predetermined reference voltage, and when the signal voltage does not satisfy the reference voltage, The liquid crystal display device according to any one of claims 2 to 7, wherein the liquid crystal display panel is determined to be abnormal. 9. The determination means compares a signal voltage of each signal line extracted by the mode switching means with a preset H level and L level reference voltage, and determines whether the signal voltage is at the H level. 8. The liquid crystal display device according to claim 2, wherein the liquid crystal display panel is determined to be abnormal when it does not belong to any of the L level and the L level. 10. The method according to claim 1, wherein the determining means detects whether or not the signal voltages of the respective signal lines extracted by the mode switching means are alternately inverted in a time division manner between an H level and an L level. The liquid crystal display device according to claim 2. 11. A test method for a liquid crystal display device, comprising: a driving circuit for applying a signal voltage for driving the liquid crystal pixels to a bus line connected to a plurality of liquid crystal pixels arranged in a matrix. A process of applying a test signal to the bus line from a test signal generation unit provided in the circuit and holding a signal voltage of the test signal; and a mode switching unit provided in the drive circuit, A process of extracting a signal voltage of the inspection signal held in the driving circuit; and a process of determining an abnormal state of the liquid crystal display panel based on the extracted signal voltage by a determination unit provided in the drive circuit. A method for inspecting a liquid crystal display device, comprising: 12. A method for inspecting a liquid crystal display device according to claim 11, comprising the liquid crystal display device according to claim 2. Description: