JP2000269944A - Data scrambler system and device thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal superior in sandomness in a transmission section and to prevent the bit error of the received signal from affecting decoded data, seated to a data scrambler system and device. SOLUTION: This system is provided with a plurality of self-synchronization type scramblers for scrambling received data and with a plurality of self- synchronization type descramblers decoding the scrambled data. A 1st descrambler 10 with a 1st initial value descrambles received data TD and a 1st scrambler 20 with a 2nd initial value different from the 1st initial value scrambles and transmits (TxD) an output signal of the 1st descrambler 10. A 2nd descrambler 30 with the 1st or 2nd initial value descrambles a received signal RxD and a 2nd scrambler 40 with the 2nd or 1st initial value scrambles an output signal of the 2nd descrambler 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data scrambler system and a device therefor, and more particularly to a data scrambler system for scramble-descrambling data using a self-synchronous scrambler and descrambler, and a device therefor.

In data transmission using an NRZ code, if the same code (bit 0 or 1) continues, timing information (clock component) and the like are lost during reproduction, and a code error occurs. The data scrambler method is used to suppress (randomize) such continuation of the same code. By increasing the randomness of the transmission signal, the quality of the clock extraction is improved, the spectrum is equalized, and the transmission signal is equalized. And the DC level can be made constant.

[0003]

2. Description of the Related Art Conventionally, a reset type and a self-synchronous type are known as data scrambler systems. In the reset type, the same PN sequence generation circuit (scrambler) is provided on the transmission / reception side, and the transmission side transmits the PN sequence to the transmission data TD by EX.
On the receiving side, the received data RD (= T
D) is decoded (reproduced).

In order to correctly decode the received data RD, it is necessary that the initial value of the PN sequence generation circuit is identical (synchronous) between transmission and reception. In the reset type, generally, transmission and reception of frame bits are performed. Synchronization (reset) is performed as an opportunity, so that the period of the PN sequence is substantially equal to one of the main signals.
It will be limited by the frame length. For example, FE
When the C frame configuration is adopted, one frame is generally composed of several hundred bits.
A stage (255-511 bit period) is sufficient, and the randomness of the transmission signal is not sufficient.

On the other hand, the self-synchronous type described later does not require synchronization (reset) for each frame, and thus has an advantage that the period of the PN sequence can be lengthened as desired. However, there is a disadvantage that a one-bit error in the received signal spreads (spreads) to a plurality of bit errors on the decoded data RD. Hereinafter, this will be described in detail.

FIG. 13 shows a conventional self-synchronous data scramble.
It is a figure showing composition of a bra system. In FIG.
Self-synchronous scrambler (SC
R) and 30 are self-synchronous desks on the data receiving side.
Rambler (DSCR), E is EX-OR circuit, FF is
This is a flip-flop circuit. It should be noted that the drawings are simple for explanation.
An example of a three-stage (7-bit cycle) configuration will be described below. Where S
CR20 is GF (2) = 1 + x^Two+ X^ThreeIn the division circuit of
And DSCR30 is GF (2) = 1 + x^Two+ X ^ThreeTo the power of
It corresponds to an arithmetic circuit. Further, TD is transmission data, and TxD is
Transmission signal, RxD is reception signal, RD is reception (decoding) data
Between the main signals TxD and RxD by wire or wireless.
Connected by means.

FIG. 14 is a diagram for explaining the operation of a conventional self-synchronous data scrambler system.
"t" is a bit number, TD is input (transmission) data of SCR20 (E3), TxD is an output (transmission) signal of SCR20 (E3), RxD is an input (reception) signal of DSCR30 (FF11), and RD is DSCR30 (E12). ) Is output (received) data.

FIG. 14A shows a case where there is no transmission error in the main signal between TxD and RxD. On the transmission side, the initial value “FF4, FF5, FF6” of the SCR 20 =
Assuming “000”, the transmission data TD = “100,000”
.. Are scrambled into a transmission signal TxD = “1011100...”, Which is a 7-bit PN sequence “101”.
1100 ". In this example, since TD = “1” at the 17th bit of the transmission data, the PN sequence “111001” from the original is thereafter applied.
EX ”is a new PN series“ 1011100 ”for“ 0 ”
(Mod2 addition). Incidentally, a new PN sequence “1” is added to the original PN sequence “1110010”.
A sequence obtained by mod2 adding “011100” is a cyclically shifted PN sequence “01011110”, and therefore, the randomness of the transmission signal TxD is guaranteed for the transmission data TD of an arbitrary input pattern.

On the receiving side, in this example, the received signal Rx
D = transmission signal TxD. The initial value “F
F11, FF12, FF13 "=" 000 ",
The received signal RxD = "1011100 ..." is correctly decoded (descrambled) into the received data RD = "100000 ...".

FIG. 14B shows a case where there is a transmission error in the main signal between TxD and RxD. Now, the reception signal R
If "1" of the first bit of xD is erroneous to "0", the received data RD is descrambled into a pattern of "0011". This is because DSCR30 has GF (2) =
Since a multiplication circuit of 1 + x ² + x ³ is used, a multiplication result (syndrome) “1011” for a 1-bit error is modally applied to decoded data “1000” when there is no error.
It is considered that 2 has been added.

[0011]

As described above, in the conventional data scrambler system, the effect of a one-bit error in the received signal RxD spreads (spreads) to a plurality of bits (depending on the DSCR length) on the received data RD. There was an inconvenience. For this reason, an error correction circuit (not shown) at the subsequent stage can correct the received data RD if it is an original 1-bit error.
The inconvenience that the received data RD cannot be corrected due to the propagation of the error bit has also occurred.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to obtain a signal having excellent randomness in a transmission section and to obtain the effect of a bit error in the received signal. The object of the present invention is to provide a data scrambler system which does not spread over decoded data and an apparatus therefor.

[0013]

The above-mentioned problem is solved, for example, by referring to FIG.
Is solved. That is, the data scrambler method of the present invention (1) includes a plurality of sets of a self-synchronous scrambler for scrambling input data and a self-synchronous descrambler for decoding the scrambled data. The input data TD is descrambled by a first descrambler 10 having a first initial value, and its output signal is scrambled by a first scrambler 20 having a second initial value different from the first and transmitted. (T
xD), the received signal RxD is descrambled by the second descrambler 30 having the first or second initial value, and the output signal is descrambled by the second scrambler having the second or first initial value. The scramble is performed by the bra 40.

In the present invention (1), the input data TD
Is descrambled by a first descrambler 10 having a first initial value, and its output signal is scrambled by a first scrambler 20 having a second initial value different from the first and transmitted (TxD). With this configuration, the input data TD is scrambled into a transmission signal TxD having excellent randomness.

Further, the received signal RxD is descrambled by the second descrambler 30 having the first or second initial value, and the output signal is demultiplexed by the second or first signal.
With the configuration of scrambling by the second scrambler 40 having the initial value of, a 1-bit error has occurred in the received signal RxD, and this has been spread by the second descrambler 30 and has spread to a plurality of bit errors. However, as a result of the error propagation bits being canceled by the second scrambler 40, only the effect of the original one-bit error appears on the output data RD.

Thus, according to the present invention (1), a signal TxD excellent in randomness can be obtained in a transmission section,
Since the effect of the bit error in the received signal RxD does not affect the decoded data RD, high-quality data communication can be performed in combination with the error correction means.

Preferably, in the present invention (2), in the present invention (1), the transmitting side transmits known data in a set of arbitrary first and second initial values, and the receiving side transmits predetermined data. The received signal is decoded with the first and second initial values, the first and second initial values of the transmitting side are obtained based on the obtained decoding pattern, and the decoding phase of the receiving side is transmitted with the obtained initial values. Side.

According to the present invention (2), even if the receiving side does not know the initial value of the transmitting side, the receiving side receives and decodes the known data sent by the transmitting side with the predetermined initial value.
Based on the decoding (error) pattern, an initial value on the transmission side can be easily obtained.

The data transmitting apparatus according to the present invention (3) includes a self-synchronous scrambler for scrambling input data, and a self-synchronous descrambler having the same number of stages as the scrambler, and transmitting the transmission data to the first stage. And descrambles the output signal with a scrambler having a second initial value different from the first and transmits the output signal. Therefore,
In the transmission section, a transmission signal TxD excellent in randomness is obtained.

Further, the data receiving apparatus of the present invention (4) includes a self-synchronous scrambler for scrambling input data, and a self-synchronous descrambler having the same number of stages as the scrambler, and receiving a first received signal. And an output signal thereof is scrambled and decoded by a scrambler having a second initial value different from the first. Therefore, the effect of a bit error in the received signal RxD does not spread to the decoded data RD, and high-quality data communication can be performed in combination with the error correction means.

Preferably, in the present invention (5), in the present invention (4), the data receiving apparatus decodes the received signal with predetermined first and second initial values, and obtains the obtained decoding pattern. And a synchronizing means for synchronizing the decoding phase on the receiving side with the transmitting side using the obtained initial values. Therefore, even if the initial value of the transmitting side is unknown, the receiving side can be easily synchronized with the transmitting side.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings.

FIGS. 2 and 3 are diagrams (1) and (2) showing the configuration of the data scrambler system according to the embodiment, and FIG. 2 shows the configuration on the transmission side. In the figure, 10 is a self-synchronous descrambler (DSCR), and 20 is a self-synchronous scrambler (SCR). The difference between the transmitting side and the prior art is that the DSCR 10 corresponding to the SCR 20 is provided at the preceding stage.

FIG. 3 shows the configuration on the receiving side. In the figure, reference numeral 30 denotes a self-synchronous descrambler (DSC).
R) and 40 are self-synchronous scramblers (SCR), 5
0 is a synchronization unit for synchronizing the decoding phase on the reception side with the transmission side, 51 is a serial-parallel conversion unit (S / P) for converting the reception data RD into a parallel signal, and 52 is a plurality of types of reception data RD. A decoder (DEC) 53 for decoding the pattern of the DEC 52; an initial value setting signal generator (IPG) 53 for generating an initial value setting signal S / R for the DSCR 30 and the SCR 40 in accordance with the decoded output of the DEC 52; Signal bus. The difference from the prior art on the receiving side is that a corresponding SCR 40 is provided after the DSCR 30. The operation of the synchronization unit 50 will be described later.

FIGS. 4 to 10 are diagrams (1) to (7) for explaining the operation of the data scrambler system according to the embodiment.
In the figure, "bit" is a bit number, TD is DSCR
10, input (transmission) data, E2 is the output of DSCR10 and the input of SCR20 (E3), TxD is the output (transmission) signal of SCR20, RxD is the input (reception) signal of DSCR30, E12 is the output of DSCR30 and SCR40.
Input (E13) and RD are output (reception) data of the SCR 40.

FIG. 4 shows a case where the respective initial values of DSCR10 to SCR40 match. However, FIG.
FIG. 3 is a diagram for helping the understanding of the present invention,
This embodiment does not constitute the case where the initial values of 10 to SCR 40 match. In the example of FIG. 4, the transmitting side: FF1 to FF3 = “000” FF4 to
FF6 = “000” Reception side: FF11-FF13 = “000” FF14-
FF16 = “000”.

As shown, when the initial values of DSCR10 to SCR40 are "000" and coincide with each other, transmission data T
D = “100000 ...” means that the transmission signal TxD = “100
0000... ”And receive signal RxD (= Tx
D) = “1,000,000...” Indicates that the received data RD = “10
00000 ... ". Thus, DSCR10 is simply added before SCR20, and DSCR10 is added.
By simply adding SCR40 after CR30, TD
= TxD, RxD (= TxD) = RD,
The transmission signal TxD (= RxD) cannot be randomized. The same applies to the case where the initial values of DSCR10 to SCR40 match in any of the patterns “001” to “111”.

Therefore, in the present invention, DSCR10 and SCR
20 and between the DSCR 30 and the SCR 40.

FIG. 5 et seq. Show a case where the present embodiment is configured. FIG. 5 shows that the initial values of DSCR10 to SCR40 are, for example, transmission side: FF1 to FF3 = “000” FF4 to
FF6 = “110” Receiver: FF11-FF13 = “000” FF14-
The case where FF16 = “110” is shown. In this case, the transmission data TD = “1”
000000 ... ”is the transmission signal TxD =“ O001011 ”
… ”And receive signal RxD
(= TxD) = "O001011 ..." is the reception data RD
= Correctly decoded to "1,000,000 ...".

As described above, if the initial values are different between the DSCR 10 and the SCR 20, the correlation between coding and decoding is lost between the two.
20 will be scrambled (randomized). That is, high randomness is obtained for the transmission signal TxD (= RxD) in this case. This, according to the present invention,
This is a basic effect of providing the DSCR 10 in front of the CR 20 and having different initial values between them.

Here, the receiving side (DSCR 30, SCR
The initial value of each (CR40) is transmitted to the transmission side (DSCR10, SCR
20), the received signal RxD
(= TxD) = "O001011 ..." is the reception data RD
= Correctly decoded to "1,000,000 ...".

FIG. 6 shows the same configuration as that of FIG. 5, and shows a case where the first bit of the received signal RxD is incorrectly changed from "0" to "1". By the way, returning to FIG.
Focusing on the operation of the CR 30, the received signal RxD = “10
Output data E12 of DSCR 30 for “00” = “1”
011 ”. From a different point of view, the received signal Rx
1-bit error of D = “(1) 000” (where () indicates a bit error), which is nothing more than an error pattern on output data E12 for “(1) 011”.

The error pattern = “(1) 011” is directly input to the input E13 of the next stage SCR 40. At this time, the initial value of the SCR 40 (FF14 to FF16) =
By being "000", the first error pattern E1
At the stage where 2 = “(1) xxx” is input, the first received data RD = “(1)” and the FFs 14 to FF
16 = “100” is transited. In addition, for subsequent inputs, this is sequentially shifted, so that E14 is
For the subsequent input of E13 = “× 011”, the same error propagation pattern = “× 011” as the input is generated, and this is fed back to the input of E13. Therefore, E
13, the error propagation pattern “× 011”
The error data is always offset by the error correction pattern “× 011” generated in S14, and finally the received data RD of the SCR 40 becomes “(1) 000”. That is, the reception signal Rx
The one-bit error “(1) xxx” of D is reproduced as it is in the received data RD as RD = “(1) xxx”, but the accompanying error propagation pattern = “× 011” is received. It does not appear on the data RD. This is a basic effect of providing the SCR 40 after the DSCR 30 according to the present invention.

Returning to FIG. 6, the above concept is applied to the RxD
Can be applied to the 1-bit error of That is, here, DSC
Since the initial value of R30 (FF11 to FF13) = “000”, the RxD 1-bit error input “(1) 0
01 ”error pattern of E12 output =“ (1)
010 ". However, the fourth bit “0” is Rx
Since there is a correct reception signal “1” in the fourth bit of D, m
The output of E12 becomes "0" by the addition of the odd2. The fact that the fourth bit of RxD = “1” means that the initial value (FF4 to FF6) of the SCR 20 on the transmission side =
This is nothing but the result of being "110".

On the other hand, in the SCR 40 on the receiving side, since the initial value (FF14 to FF16) = “110”, at the stage where the first error pattern E12 = “(1) xxx” is inputted, The received data RD becomes “(0)”, and the state transits to FF14 to FF16 = “011”. Further, the subsequent input is shifted in order, so that E14 is equal to the input of the subsequent E13 = “×
010 "= the same error propagation pattern as the input =
“× 010” is generated, and this is fed back to the input of E13. Therefore, the error propagation pattern = “× 010” input to E13 is always canceled by the error correction pattern = “× 010” generated in E14, and thus the received data RD of the SCR 40 finally becomes “(0)”. 00
0 ". Here, only the first bit of the reception data RD is incorrect from “1” to “0”, and there is no other error. Therefore, an error correction circuit (not shown) at the subsequent stage can correct this one-bit error correctly.

FIG. 7 shows the same RxD 1-bit error case as in FIG. 6, except that DSCRs 10 and 30 and SCR2
The case where each initial value is exchanged between 0 and 40 is shown. That is, the transmitting side: FF1 to FF3 = “110” FF4 to
FF6 = “000” Receiver: FF11-FF13 = “110” FF14-
FF16 = “000”.

Focusing on the transmission signal TxD, TxD =
.., Which is the TxD in FIG.
Is the same as This is because if the combination of the initial values of DSCR10 and SCR20 is "110", "000", DSCR
Even if this initial value is exchanged between 10 and the SCR 20, the effect that appears outside (transmission signal TxD) is the same. This is the same on the receiving side, and although the data E12 and the like generated in the middle are different, the effect that appears on the outside (received data RxD) is the same.

FIG. 8 shows the same RxD 1-bit error case as in FIG. 6 described above, but on the transmitting side (DSCR10, SCR2).
This shows a case where each initial value of only 0) is replaced. That is, the transmitting side: FF1 to FF3 = “110” FF4 to
FF6 = “000” Reception side: FF11-FF13 = “000” FF14-
FF16 = “110”. According to the description of FIG. 7, even if the initial values are exchanged as shown in FIG.
The effect appearing in D) is the same.

FIG. 9 shows a case of the same RxD 1-bit error as in FIG. 6, but the receiving side (DSCR30, SCR4
This shows a case where each initial value of only 0) is replaced. That is, the transmitting side: FF1 to FF3 = “000” FF4 to
FF6 = “110” Receiver: FF11-FF13 = “110” FF14-
FF16 = “000”. As described above with reference to FIGS. 7 and 8, even if the initial values are exchanged as shown in FIG. 9, the effect that appears on the outside (the transmission signal TxD and the reception data RD) is the same.

Thus, according to the present embodiment, in general, any one of a set of initial values different from the initial values "000" to "111" can be selected between the DSCRs 10, 30 and the SCRs 20, 40. . Further, the selected set of initial values may be exchanged between the transmitting side and the receiving side.

FIG. 10 is a simulation of a more general operation state of the data scrambler system according to the embodiment. Here, the initial value is set, for example, on the transmission side: FF1 to FF3 = “111” FF4 to
FF6 = “010” Receiver: FF11-FF13 = “010” FF14-
FF16 = “111”. Transmission data TD = “1010101”
"0101010", "111111 ..."
Looking at each bit, the patterns are divided in this way.

The transmission signal TxD for this is: TxD = “0110000” “1001111” “00”
1101... ”And are sufficiently randomized. The received signal RxD for this is: RxD = “1001000” “0110111” “11”
0101..., And comparing TxD-RxD, the error pattern ExD of RxD is “(1001) 000”, “(0110) 111”, “(1
10) 101 ... ". The received data RD at this time is as follows: RD = “01010110” “1010010” “000”
111..., And when this is compared with the transmission data TD, TD = “1010101”, “0101010”, “111”
111..., The error pattern ED on the reception data RD is: ED = “XXX101”, “XXX010”, “XXX”
111..., And “0” → “1” on the received signal RxD.
Or, only bits wrong from “1” to “0” are received data R
It is also an error on D.

Next, the operation of matching (synchronizing) the initial value on the receiving side with the initial value on the transmitting side will be described. Referring back to FIG. 3, there are several methods for synchronizing the receiving side with the transmitting side.

First, when the initial value on the transmitting side is known on the receiving side, synchronization can be performed relatively easily. For example, the initial reset signal RS2 generated when the power supply of the receiving side is turned on causes D
A known initial value is set in SCR30 and SCR40. Alternatively, after turning on the power of the receiving side, a reset signal RS2 is generated in synchronization with a predetermined synchronizing signal (a specific frame synchronizing signal or the like) sent from the transmitting side, whereby the DSCR 30, SCR
40 is set to a known initial value. Alternatively, the receiving side requests the transmitting side to transmit a synchronizing signal via the reverse line (uplink), and upon receiving the request, the transmitting side transmits the synchronizing signal to the receiving side and initializes its own initial value. I do. The receiving side that has received the synchronization signal also sets a known initial value in its own DSCR 30 and SCR 40 in synchronization with the synchronization signal.

If the receiving side does not know the initial value of the transmitting side, it is possible to receive the information of the initial value from the transmitting side via a main signal line or the like in advance. And
Based on the received initial value, transmission and reception can be synchronized by any of the above methods.

If the receiving side does not know the initial value of the transmitting side, the receiving side can independently obtain the initial value of the transmitting side. Hereinafter, this will be described.

FIG. 11 is a diagram showing an initial value conversion table according to the embodiment. This table contains transmission data TD = “1010101” “010101” known from the transmission side.
"0""101..." is the initial value of DSCR10 = "000"
If the initial value of the SCR 20 is "000" to "111" and the data is decoded with the initial value of the DSCR 30 of the receiving side = "000" and the initial value of the SCR 40 = "000", what kind of reception is possible. This indicates whether the data RD is to be decoded.

That is, RD (0) in FIG.
Each initial value of CR10, 30 and SCR20, 40 is "0".
00 "," 000 ", and the received data RD = the transmitted data TD =" 1010101 ... "
(Known) is correctly decoded. On the other hand, other RD (1) ~
In the case of RD (7), the initial value of the SCR 20 on the transmitting side is any one of “001” to “111”, whereas the initial value of the SCR 40 on the receiving side is constant at “000”. Therefore, each of the received data RD (1) to RD (7) in this case has a unique pattern corresponding to the difference in the initial value between transmission and reception.

Returning to FIG. 2, this synchronization unit 50
This is an example of a configuration using one table information. That is, the initial values of the DSCR 30 and the SCR 40 are initialized to predetermined initial values = “000”, “000” by the reset signal R2. After that, the transmission data T
When D = “101010...” Is transmitted, D
The received data RD (RD (6) = “0011110...” In this case) is decoded by the SCR 30 and the SCR 40.

In this state, the serial-parallel converter 5
1 converts the received data RD into a parallel signal. Further, the decoder 52 decodes a plurality of (eight in this example) patterns of the received data RD. Note that the pattern length to be decoded may be any length as long as the eight types of patterns shown in FIG. 11 can be distinguished. Preferably, decoding is performed at a multiple of a 7-bit period. Also, if necessary, taking into account that RxD is wrong, the reception RD
The identity of the pattern may be confirmed. At this time, for example, R
The pattern of D (6), as shown in FIG.
Inverted like “0011110”, 2nd time = “1100001”, the identity of RD (6) is determined taking this fact into consideration.

Thus, in this example, the seventh pattern RD (6) of the eight patterns RD (0) to RD (7) in FIG.
Is activated. Then, the initial value setting signal generator 53 outputs the decoded output RD of the DEC 52.
(6) In accordance with = 1, the respective initial value setting signals S / R = “000”, “110” of the DSCR 30 and the SCR 40 are generated. Thereafter, for example, when the timing pulse SP is generated at a multiple of the reception cycle, each initial value setting signal S / R = “00”.
“0” and “110” are FF11 to FF13 and FF14 to F
It is set to F16.

FIG. 12 is a diagram for explaining a synchronization operation according to the embodiment. First, DSCR10, SCR on the sending side
20, each initial value = “000”, “110”, and the receiving side DSCR 30, SCR 40 initial value = “000”,
"000", which are different. Next, when data for one cycle is received and decoded in this state, the received data RD (6) = “0011110” in FIG. 11 is decoded, whereby each initial value of the DSCR10 and SCR20 on the transmission side = “000”. , "110".
Therefore, on the receiving side, for example, at the timing of bit 8, D
The initial values of SCR30 and SCR40 are “000”, “1”
10 ”. As a result, the subsequent received data RD of bit 8 or later is RD = “0101010” “11”
1111 ... "is correctly decoded.

Although the above example of the synchronization method has been specifically described, it is apparent that this method can be realized for any combination of the initial values on the transmission side.

Also, the case where the decoder 52 is used has been described. Instead of using the decoder 52, the memory storing the table information shown in FIG. 11 is compared with the reproduced RD pattern and each RD pattern of the memory. A configuration according to a normal table reference method using a comparator for performing the comparison can be adopted.

In the above embodiment, the DSCR10,
Although the case where each of the SCR 30 and the SCRs 20 and 40 has three stages has been described, it is apparent that any number of stages (and any generating polynomial) can be used.

In the above embodiment, the reception signal RxD
Has been described as a simple example in the case of a 1-bit error, but the operation in the case of a multiple-bit error can be easily understood as the effect of each 1-bit error being mod2 added.

Although the above embodiment has been described with specific numerical examples, it is apparent that the present invention is not limited to these.

Although the preferred embodiments of the present invention have been described, it goes without saying that various changes can be made in the configuration, control, and combination of these components without departing from the spirit of the present invention. .

[0059]

As described above, according to the present invention, a signal excellent in randomness can be obtained in a transmission section, and the effect of a bit error in the received signal does not spread on the decoded data. High transmission quality can be obtained by combining with the error correction coding means, and thus an excellent data scrambler method can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram (1) illustrating a configuration of a data scrambler system according to an embodiment;

FIG. 3 is a diagram (2) illustrating a configuration of a data scrambler system according to the embodiment;

FIG. 4 is a diagram (1) for explaining the operation of the data scrambler method according to the embodiment;

FIG. 5 is a diagram (2) illustrating the operation of the data scrambler method according to the embodiment.

FIG. 6 is a diagram (3) illustrating an operation of the data scrambler method according to the embodiment.

FIG. 7 is a diagram (4) illustrating the operation of the data scrambler method according to the embodiment.

FIG. 8 is a diagram (5) for explaining the operation of the data scrambler method according to the embodiment;

FIG. 9 is a diagram (6) for explaining the operation of the data scrambler method according to the embodiment;

FIG. 10 is a diagram (7) for explaining the operation of the data scrambler method according to the embodiment;

FIG. 11 is a diagram showing an initial value conversion table according to the embodiment.

FIG. 12 is a diagram illustrating a synchronization operation according to the embodiment.

FIG. 13 is a diagram showing a configuration of a conventional data scrambler system.

FIG. 14 is a diagram illustrating an operation of a conventional data scrambler method.

[Explanation of symbols]

 10, 30 Descrambler (DSCR) 20, 40 Scrambler (SCR) 50 Synchronization unit 51 Serial-parallel conversion unit (S / P) 52 Decoder (DEC) 53 Initial value setting signal generation unit (IPG) 54 Signal bus E EX-OR circuit FF flip-flop circuit

Claims (5)

[Claims] A plurality of sets of a self-synchronous scrambler for scrambling input data and a self-synchronous descrambler for decoding the scrambled data are provided, and the input data is set to a first initial value. Having the first descrambler and the output signal scrambled by a first scrambler having a second initial value different from the first, and transmitting the received signal. A data scrambler method, comprising descrambled by a second descrambler having an initial value of, and scrambled by an output signal of the second descrambler having the second or first initial value. 2. The transmitting side transmits known data in a set of arbitrary first and second initial values, and the receiving side decodes a received signal with predetermined first and second initial values and obtains the obtained signal. 2. The data according to claim 1, wherein first and second initial values on the transmitting side are obtained based on the obtained decoding pattern, and the decoding phase on the receiving side is synchronized with the transmitting side with the obtained initial values. Scrambler method. 3. A self-synchronous scrambler for scrambling input data, and a self-synchronous descrambler having the same number of stages as the scrambler, and transmitting transmission data to a first scrambler.
And a descrambler having a second initial value different from the first value, and a descrambler using the descrambler having the second initial value. 4. A self-synchronous scrambler for scrambling input data, and a self-synchronous descrambler having the same number of stages as the scrambler, wherein the received signal is descrambled by a descrambler having a first initial value. And a data receiving device for scrambling and decoding the output signal with a scrambler having a second initial value different from the first value. 5. A received signal is decoded with predetermined first and second initial values, and first and second initial values on the transmitting side are obtained based on the obtained decoding pattern. 5. The data receiving apparatus according to claim 4, further comprising a synchronizing means for synchronizing a decoding phase on a receiving side with a transmitting side.