JP6601282B2 - Data transfer apparatus, data transfer system, and control method for data transfer system - Google Patents

Description

  The present invention relates to a data transfer device, a data transfer system, and a data transfer system control method.

In data transfer using a high-speed serial bus of an information processing system, circuits called a scrambler and a descrambler are used to improve transmission quality. The data transfer device (data transmission device) on the transmission side randomizes the data with a scrambler and transmits the randomized data to the data transfer device (data reception device) on the reception side. The data receiving device receives the randomized data and restores the original data from the received data by the descrambler. Thus, the following effects are acquired by randomizing transmission data with a scrambler.
(1) The frequency of occurrence of data edges used by the clock data recovery (CDR) circuit provided in the data receiving apparatus to recover the clock signal increases.
(2) The balance between logic “1” and logic “0” of transmission data is improved, and deterioration of transmission quality due to baseline wander is prevented.
(3) Since the fixed frequency component of the transmission data is reduced, it contributes to the reduction of electromagnetic noise peaks.
(4) Transmission quality is prevented from deteriorating due to intersymbol interference caused by fixed frequency components of transmission data.

  The scrambler and descrambler randomize and restore data based on the same polynomial. Therefore, when the descrambler restores data, the descrambler is synchronized with the scrambler.

  For example, in the case of an additive scrambler used in PCI Express Base Specification Revision 3.0 or the like, a random number is generated using a linear feedback shift register (LFSR). When the scrambler of the data transmission device transmits the LFSR initialization pattern to the data reception device for synchronization of the scrambler and the descrambler, the random number held by the LFSR of the scrambler is set to an initial value called a seed value. initialize. When the descrambler of the data receiving device receives the LFSR initialization pattern from the data transmitting device, the descrambler initializes a random number held in the LFSR of the descrambler to a seed value.

  The data transmitting device and the data receiving device initialize the random numbers of the scrambler and descrambler to the same value by transmitting and receiving the LFSR initialization pattern, thereby completing the synchronization of the scrambler and descrambler. After the synchronization is completed, the descrambler can correctly restore the scrambled received data. The additive scrambler is sometimes called a synchronous scrambler.

  A system is also known that scrambles and transmits a signal obtained by adding a data signal sequence to a frame synchronization signal (see, for example, Patent Document 1).

JP 63-226145 A

  However, in the conventional data transfer apparatus, normal data is transmitted after being scrambled, but the LFSR initialization pattern is transmitted without being scrambled. For this reason, transmission quality may be degraded by transmission of an unscrambled LFSR initialization pattern.

  Such a problem occurs not only in the additive scrambler used in PCI Express, but also in scramblers used in other data transfer systems.

  In one aspect, an object of the present invention is to suppress a decrease in transmission quality in a data transfer system that synchronizes a scrambler and a descrambler.

In one plan, the data transfer apparatus includes a receiving unit, an updating unit, a restoring unit, and a control unit.
The receiving unit receives, from the data transmission device, a first transmission data sequence including the first random number generated by scrambling the first data sequence using the first random number in the first period. The receiving unit generates a second transmission data sequence including the second random number generated by scrambling the second data sequence using the second random number obtained by updating the first random number in the second period. Receive from the data transmission device.

  The updating unit updates the first random number included in the first transmission data sequence received by the receiving unit, and generates a second random number. The restoration unit restores the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the second random number generated by the update unit. When the second data string restored by the restoration unit is a predetermined data string, the control unit controls the update unit to update the generated random number.

  According to the embodiment, in the data transfer system that synchronizes the scrambler and the descrambler, it is possible to suppress a decrease in transmission quality.

It is a block diagram of a data transfer system using an additive scrambler. It is a block diagram of a scrambler. It is a block diagram of a descrambler. It is a block diagram of the data transfer system which does not use a LFSR initialization pattern. It is a flowchart of the control method of a data transfer system. It is a block diagram which shows the specific example of a data transfer system. It is a figure which shows a descrambler lock pattern. It is a block diagram of the scrambler which does not use a LFSR initialization pattern. It is a block diagram of the descrambler which does not use a LFSR initialization pattern. It is a flowchart (the 1) which shows operation | movement of a determination part. It is a flowchart (the 2) which shows operation | movement of a determination part. It is a timing chart which shows operation | movement of a descrambler. It is a flowchart (the 1) which shows operation | movement of a reception sequence controller. It is a flowchart (the 2) which shows operation | movement of a reception sequence controller. It is a flowchart (the 1) which shows operation | movement of a transmission sequence controller. It is a flowchart (the 2) which shows operation | movement of a transmission sequence controller. It is a flowchart (the 3) which shows operation | movement of a transmission sequence controller. It is a timing chart which shows operation | movement of a transmission sequence controller. It is a block diagram of an information processing system.

Hereinafter, embodiments will be described in detail with reference to the drawings.
FIG. 1 shows a configuration example of a data transfer system using an additive scrambler. The data transfer system in FIG. 1 includes a data transfer apparatus 101 and a data transfer apparatus 102. The data transfer apparatus 101 includes a transmission circuit 111, a reception circuit 112, and a training control unit 113, and the data transfer apparatus 102 includes a transmission circuit 121, a reception circuit 122, and a training control unit 123. The serial bus 103 connects the transmission circuit 111 of the data transfer apparatus 101 and the reception circuit 122 of the data transfer apparatus 102, and connects the transmission circuit 121 of the data transfer apparatus 102 and the reception circuit 112 of the data transfer apparatus 101. To do.

  The training control unit 113 includes a transmission sequence controller 151 and a reception sequence controller 152, and controls link initialization and link reinitialization of the serial bus 103. The transmission sequence controller 151 mainly controls the transmission circuit 111, and the reception sequence controller 152 mainly controls the reception circuit 112.

  The transmission circuit 111 includes a cyclic redundancy check (CRC) generation unit 131, a pattern generation unit 132, a selector 133, a scrambler 134, a selector 135, an encoder 136, and a conversion unit 137. The reception circuit 112 includes a conversion unit 141, an alignment circuit 142, an alignment detection unit 143, an elastic buffer 144, a decoder 145, a descrambler 146, a pattern reception unit 147, and a CRC checker 148.

  The scrambler 134 is an additive scrambler, and the descrambler 146 is an additive descrambler. Hereinafter, the random numbers held by the scrambler 134 and the descrambler 146 may be referred to as LFSR values.

  The configurations of the transmission circuit 121, the reception circuit 122, and the training control unit 123 of the data transfer apparatus 102 are the same as the configurations of the transmission circuit 111, the reception circuit 112, and the training control unit 113 of the data transfer apparatus 101.

  First, the operation of the transmission circuit 111 will be described. During link initialization, the transmission circuit 111 transmits training patterns called Training Sequence Ordered Set 1 (tsos1) and tsos2 to the data transfer apparatus 102. Hereinafter, tsos1 and tsos2 may be simply referred to as tsos.

  The training control unit 113 outputs the signal tsos1_send instructing transmission of tsos1 and the signal tsos2_send instructing transmission of tsos2 to the pattern generation unit 132. Further, the training control unit 113 outputs a signal scrambler_select for selecting the output of the scrambler 134 to the selector 135. The pattern generation unit 132 generates tsos, the selector 133 outputs tsos to the scrambler 134, the scrambler 134 scrambles tsos, and the selector 135 outputs the scrambled tsos to the encoder 136.

  The encoder 136 encodes the scrambled tsos to add an enc-bit to the tsos. The enc-bit includes information indicating the boundary of the encoding block, the data type such as a training pattern or a packet, the presence / absence of scramble, and the like. The data transfer apparatus 102 can determine the boundary of the encoded block, the data type, the presence / absence of scramble, and the like based on enc-bit. The enc-bit itself added after scrambling is not scrambled.

  The conversion unit 137 converts the encoded tsos from parallel data to serial data, and outputs the serial data to the serial bus 103. As a result, tsos is transmitted from the data transfer apparatus 101 to the data transfer apparatus 102.

  During transmission of tsos, the transmission circuit 111 periodically transmits a training pattern called an LFSR initialization pattern to the data transfer apparatus 102 in order to synchronize the scrambler 134 and the descrambler in the reception circuit 122.

  The training control unit 113 outputs a signal dsc_init_ptn_send for instructing transmission of the LFSR initialization pattern to the pattern generation unit 132, and outputs a signal scrambler_init for selecting the initial value of the LFSR value to the scrambler 134. The pattern generation unit 132 generates an LFSR initialization pattern, the selector 133 outputs the LFSR initialization pattern to the selector 135, and the selector 135 outputs the LFSR initialization pattern to the encoder 136. Therefore, the LFSR initialization pattern is output to the encoder 136 bypassing the scrambler 134.

  The encoder 136 encodes the LFSR initialization pattern, and the conversion unit 137 converts the encoded LFSR initialization pattern into serial data and outputs the serial data to the serial bus 103. As a result, the LFSR initialization pattern is transmitted from the data transfer apparatus 101 to the data transfer apparatus 102.

  When the link initialization is completed, the CRC generation unit 131 adds a CRC to the normal data packet and outputs the packet to the selector 133. The training control unit 113 outputs a signal packet_select for selecting the output of the CRC generation unit 131 to the selector 133, and outputs a signal scrambler_select for selecting the output of the scrambler 134 to the selector 135.

  The selector 133 outputs the packet to the scrambler 134, and the scrambler 134 scrambles the packet. The selector 135 outputs the scrambled packet to the encoder 136, the encoder 136 encodes the scrambled packet, and the conversion unit 137 converts the encoded packet into serial data and outputs it to the serial bus 103. . As a result, the packet is transmitted from the data transfer apparatus 101 to the data transfer apparatus 102.

  Regardless of link initialization or after link initialization is completed, the transmission circuit 111 periodically transmits a pattern called SKIP Ordered Set (skpos) to the data transfer apparatus 102. The skpos is used to absorb the frequency deviation of the oscillator between the data transfer apparatus 101 and the data transfer apparatus 102.

  The training control unit 113 outputs a signal skpos_send that instructs transmission of skpos to the pattern generation unit 132. The skpos generated by the pattern generation unit 132 bypasses the scrambler 134 and is output to the encoder 136 and is output from the conversion unit 137 to the serial bus 103. As a result, skpos is transmitted from the data transfer apparatus 101 to the data transfer apparatus 102.

  At this time, the training control unit 113 outputs a signal scrambler_hold instructing to hold the LFSR value to the scrambler 134, and the scrambler 134 holds the LFSR value.

  Next, the operation of the receiving circuit 112 will be described. The transmission circuit 121 of the data transfer apparatus 102 operates in the same manner as the transmission circuit 111, and transmits tsos, the LFSR initialization pattern, and skpos to the data transfer apparatus 101. The converter 141 converts the received data input from the serial bus 103 from serial data to parallel data, and outputs the converted data to the alignment circuit 142 and the alignment detector 143.

  During link initialization, the alignment detection unit 143 detects the boundary of the encoded block based on enc-bit or the like of the received data. Then, the alignment detection unit 143 outputs to the alignment circuit 142 a signal align_det indicating detection of the boundary of the encoded block and data align_boundary including the boundary of the encoded block.

  The alignment circuit 142 writes the received data to the write side of the elastic buffer 144 based on the detected boundary of the encoded block. As a result, the read side of the elastic buffer 144 can handle received data in units of encode blocks.

  The elastic buffer 144 outputs a signal elbf_act indicating that the elastic buffer 144 is active to the training control unit 113 when the write operation is continuously performed from the alignment circuit 142. When the elastic buffer 144 is active, the training control unit 113 recognizes that the alignment of the encoding block has been completed. When the link initialization is completed, the alignment of the detected encoded block is held.

  The write side of the conversion unit 141, the alignment circuit 142, the alignment detection unit 143, and the elastic buffer 144 is an area of the clock signal rx_clk. A CDR circuit (not shown) provided in the receiving circuit 112 generates rx_clk by reproducing a timing signal from the received data. In the elastic buffer 144, switching from rx_clk to the physical coding sublayer (PCS) clock signal pcs_clk of the reception circuit 112 is performed.

  Regardless of link initialization or after link initialization is completed, the decoder 145 decodes the received data read from the elastic buffer 144. At this time, the decoder 145 refers to enc-bit, determines the data type and the presence / absence of scramble, and outputs the scrambled received data to the descrambler 146. In addition, the decoder 145 outputs received data such as an unscrambled LFSR initialization pattern and skpos to the pattern receiving unit 147. The descrambler 146 descrambles the scrambled received data and restores the unscrambled data.

  The pattern receiving unit 147 detects tsos from the unscrambled data output from the descrambler 146, and outputs a signal tsos1_det indicating the detection of tsos1 and a signal tsos2_det indicating the detection of tsos2 to the training control unit 113. Further, the pattern receiving unit 147 detects the LFSR initialization pattern and skpos from the reception data directly output from the decoder 145.

  When the pattern reception unit 147 detects the LFSR initialization pattern, the pattern reception unit 147 outputs a signal descrambler_init for selecting an initial value of the LFSR value to the descrambler 146, and the descrambler 146 initializes the LFSR value. Further, when the pattern receiving unit 147 detects skpos, the pattern receiving unit 147 outputs a signal descrambler_hold for holding the LFSR value to the descrambler 146, and the descrambler 146 holds the LFSR value.

  When the link initialization is completed, the CRC checker 148 checks the CRC of the unscrambled data and outputs the unscrambled data as a packet. Further, the training control unit 113 outputs a signal rx_packet_valid indicating that the received data is valid.

  Regardless of link initialization or after completion of link initialization, the decoder 145 outputs a signal decode_error indicating the occurrence of a decode error to the training control unit 113 when a decode error occurs. Further, when a CRC error occurs, the CRC checker 148 outputs a signal crc_error indicating the occurrence of the CRC error to the training control unit 113.

  The training control unit 113 can detect misalignment of encode blocks based on frequent occurrences of decoding errors or CRC errors. When it is estimated that the encode block is misaligned, the training control unit 113 outputs a signal align_re_lock that instructs the alignment detection unit 143 to re-execute alignment. If link initialization is complete, link initialization is resumed.

  FIG. 2 shows a configuration example of the scrambler 134 of FIG. The scrambler 134 in FIG. 2 includes an LFSR 201, a selector 202, a logical sum (OR) circuit 203, a flip-flop (FF) 204, and an exclusive logical sum (XOR) circuit 205. The FF 204 holds the LFSR value, and the XOR circuit 205 outputs the exclusive OR of the LFSR value output from the FF 204 and the input data D1 as scrambled transmission data D2.

  The LFSR 201 updates the LFSR value output from the FF 204, generates the next LFSR value, and outputs it to the selector 202. The OR circuit 203 outputs the logical sum of the signal output from the selector 202 and the reset signal R to the FF 204. Except at the time of resetting, the reset signal R is set to logic “0”. The selector 202 is controlled by scrambler_init and scrambler_hold output from the training control unit 113.

  At the time of transmitting the LFSR initialization pattern, the training control unit 113 sets the scrambler_init to logic “1”, and the selector 202 selects the signal lfsr_init_value representing the initial value and outputs it to the OR circuit 203. Thereby, lfsr_init_value is stored in the FF 204, and the LFSR value is initialized.

  At the time of transmitting skpos, the training control unit 113 sets scrambler_hold to logic “1”, and the selector 202 selects the LFSR value output from the FF 204 and outputs the LFSR value to the OR circuit 203. Thereby, the LFSR value of the FF 204 is held, and the LFSR value is not updated.

  On the other hand, when transmitting tsos and normal data, the selector 202 selects a signal output from the LFSR 201 and outputs it to the OR circuit 203. As a result, the LFSR value of the FF 204 is updated to the next LFSR value.

  FIG. 3 shows a configuration example of the descrambler 146 of FIG. The descrambler 146 of FIG. 3 includes an LFSR 301, a selector 302, an OR circuit 303, an FF 304, and an XOR circuit 305. The FF 304 holds the LFSR value, and the XOR circuit 305 outputs an exclusive OR of the LFSR value output from the FF 304 and the scrambled input data D3 as non-scrambled data D4.

  The LFSR 301 updates the LFSR value output from the FF 304, generates the next LFSR value, and outputs it to the selector 302. The OR circuit 303 outputs the logical sum of the signal output from the selector 302 and the reset signal R to the FF 304. The selector 302 is controlled by descrambler_init and descrambler_hold output from the pattern receiving unit 147.

  When receiving the LFSR initialization pattern, the pattern receiving unit 147 sets descrambler_init to logic “1”, and the selector 302 selects the signal lfsr_init_value representing the initial value and outputs it to the OR circuit 303. As a result, lfsr_init_value is stored in the FF 304, and the LFSR value is initialized.

  At the time of reception of skpos, the pattern receiving unit 147 sets descrambler_hold to logic “1”, and the selector 302 selects the LFSR value output from the FF 304 and outputs it to the OR circuit 303. As a result, the LFSR value of the FF 304 is held, and the LFSR value is not updated.

  On the other hand, when receiving tsos and normal data, the selector 302 selects a signal output from the LFSR 301 and outputs it to the OR circuit 303. As a result, the LFSR value of the FF 304 is updated to the next LFSR value.

  Thus, in the data transfer system of FIG. 1, tsos and normal data are transmitted after being scrambled, but the LFSR initialization pattern and skpos are transmitted without being scrambled. Therefore, the serial bus 103 transfers two types of data, scrambled data and unscrambled data.

  In the first place, in the data transfer system, scrambled data is transmitted in order to improve the transmission quality. Therefore, transmission of an unscrambled LFSR initialization pattern may cause a decrease in transmission quality. Therefore, it is desirable to synchronize the scrambler and descrambler without using such an LFSR initialization pattern.

  Further, the receiving circuit is provided with a circuit for distinguishing between scrambled data and unscrambled data. In both the transmission circuit and the reception circuit, control for enabling or disabling the scrambler or descrambler is performed according to the data type. As described above, since the LFSR initialization pattern is transmitted and received, the control of the transmission circuit and the reception circuit becomes complicated.

  As a scrambler that is different from the additive scrambler, a self-synchronous scrambler that is standardized in 49 of IEEE 802.3-2008 and used in 10 GbE or the like is also known. When the self-synchronizing scrambler is employed, the transmission circuit scrambler and the receiving circuit descrambler can be synchronized with a simple circuit configuration, as the name of the self-synchronizing type indicates.

For example, when the LFSR value is generated based on the polynomial G (x) = x ⁵⁸ + x ³⁹ +1, the scrambler and the descrambler can be synchronized only by transmitting and receiving 58-bit data. That is, if communication is simply continued without transmitting / receiving a special LFSR initialization pattern, synchronization between the scrambler and the descrambler is performed. The self-synchronizing scrambler is sometimes called a multiple scrambler.

  However, the self-synchronizing scrambler increases the 1-bit transmission line error by the number of taps of the polynomial. For example, when the LFSR value is generated based on the above polynomial, since the number of taps is 2, a 3-bit transmission path error is generated by adding 2 bits to the 1-bit transmission path error. Usually, since the high-speed serial bus is protected by redundant bits such as CRC, the probability that the occurrence of a transmission path error is not detected due to the CRC error increases when the number of transmission path errors increases.

  FIG. 4 shows a configuration example of a data transfer system that synchronizes the scrambler and the descrambler without using the LFSR initialization pattern. The data transfer system in FIG. 4 includes a data transfer device 401 and a data transfer device 402. The data transfer device 401 includes a generation unit 411, a randomization unit 412, a transmission unit 413, and an update unit 414. The data transfer device 402 includes a reception unit 421, a restoration unit 422, an update unit 423, and a control unit 424. .

  The generation unit 411 generates a first data sequence and a second data sequence, and the update unit 414 updates the first random number to generate a second random number. The randomization unit 412 generates a first transmission data sequence including the first random number by scrambling the first data sequence using the first random number, and scrambles the second data sequence using the second random number. Thus, a second transmission data string including the second random number is generated.

  The transmission unit 413 transmits the first transmission data string to the data transfer apparatus 402 in the first period, and transmits the second transmission data string to the data transfer apparatus 402 in the second period. The receiving unit 421 receives the first transmission data string from the data transfer apparatus 401 in the first period, and receives the second transmission data string from the data transfer apparatus 401 in the second period.

  The updating unit 423 updates the first random number included in the first transmission data sequence received by the receiving unit 421 and generates a second random number. The restoration unit 422 restores the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the second random number generated by the update unit 423. When the second data string restored by the restoration unit 422 is a predetermined data string, the control unit 424 controls the update unit 423 to update the generated random number.

  FIG. 5 is a flowchart showing an example of a control method of the data transfer system of FIG. First, the generation unit 411 of the data transfer device 401 generates a first transmission data sequence by scrambling the first data sequence using the first random number (step 501). In the first period, the transmission unit 413 The first transmission data string is transmitted to the data transfer device 402 (step 502).

  Next, the reception unit 421 of the data transfer device 402 receives the first transmission data sequence from the data transfer device 401 (step 503), and the update unit 423 receives the first random number included in the received first transmission data sequence. The second random number is generated by updating (step 504).

  Next, the update unit 414 of the data transfer device 401 updates the first random number to generate a second random number (step 505). Then, the generation unit 411 generates the second transmission data sequence by scrambling the second data sequence using the second random number (step 506), and in the second period, the transmission unit 413 generates the second transmission data sequence. Is transmitted to the data transfer apparatus 402 (step 507).

  Next, the reception unit 421 of the data transfer device 402 receives the second transmission data sequence from the data transfer device 401 (step 508), and the restoration unit 422 descrambles the second transmission data sequence using the second random number. Thus, the second data string is restored (step 509). Then, when the restored second data string is a predetermined data string, the updating unit 423 updates the generated random number based on an instruction from the control unit 424 (step 510).

  According to the data transfer system of FIG. 4, it is possible to suppress a decrease in transmission quality in the data transfer system that synchronizes the scrambler and the descrambler.

  FIG. 6 shows a specific example of the data transfer system of FIG. The data transfer system in FIG. 6 includes a data transfer device 601 and a data transfer device 602. The data transfer device 601 includes a transmission circuit 611, a reception circuit 612, and a training control unit 613. The data transfer device 602 includes a transmission circuit 621, a reception circuit 622, and a training control unit 623. The serial bus 603 connects the transmission circuit 611 of the data transfer apparatus 601 and the reception circuit 622 of the data transfer apparatus 602, and connects the transmission circuit 621 of the data transfer apparatus 602 and the reception circuit 612 of the data transfer apparatus 601. To do.

  The training control unit 613 includes a transmission sequence controller 651 and a reception sequence controller 652, and controls link initialization and link reinitialization of the serial bus 603. The transmission sequence controller 651 mainly controls the transmission circuit 611, and the reception sequence controller 652 mainly controls the reception circuit 612.

  The transmission circuit 611 includes a CRC generation unit 631, a pattern generation unit 632, a selector 633, an encoder 634, a scrambler 635, and a conversion unit 636. The reception circuit 612 includes a conversion unit 641, a descrambler 642, an alignment circuit 643, an elastic buffer 644, a decoder 645, a pattern reception unit 646, and a CRC checker 647. The scrambler 635 is an additive scrambler, and the descrambler 642 is an additive descrambler. The descrambler 642 includes a control unit 648.

  The configurations of the transmission circuit 621, the reception circuit 622, and the training control unit 623 of the data transfer device 602 are the same as the configurations of the transmission circuit 611, the reception circuit 612, and the training control unit 613 of the data transfer device 601.

  When the data transfer device 601 and the data transfer device 602 correspond to the data transfer device 401 and the data transfer device 402 in FIG. 4, respectively, the pattern generation unit 632 and the conversion unit 636 in the transmission circuit 611 include the generation unit 411 and the transmission unit. 413 respectively. A conversion unit and a control unit in the reception circuit 622 correspond to the reception unit 421 and the control unit 424, respectively.

  On the other hand, when the data transfer device 601 and the data transfer device 602 correspond to the data transfer device 402 and the data transfer device 401 in FIG. 4 respectively, the pattern generation unit and the conversion unit in the transmission circuit 621 are the generation unit 411 and the transmission unit. 413 respectively. Further, the conversion unit 641 and the control unit 648 in the reception circuit 612 correspond to the reception unit 421 and the control unit 424, respectively.

  First, the operation of the transmission circuit 611 will be described. Regardless of the link initialization or after the link initialization is completed, the encoder 634 encodes the data string output from the selector 633 and adds an enc-bit to the data string. The scrambler 635 generates a transmission data string by scrambling the data string output from the encoder 634. In this case, since the data string is scrambled after being encoded, the enc-bit is also scrambled.

  The conversion unit 636 converts the transmission data string from parallel data to serial data, and outputs it to the serial bus 603. As a result, the transmission data string is transmitted from the data transfer apparatus 601 to the data transfer apparatus 602.

  During link initialization, the transmission circuit 611 transmits tsos1 and tsos2 to the data transfer apparatus 602. The training control unit 613 outputs tsos1_send and tsos2_send to the pattern generation unit 632. The pattern generation unit 632 generates a data string of tsos, and the selector 633 outputs tsos to the encoder 634.

  The encoder 634 encodes tsos, the scrambler 635 scrambles the encoded tsos, and the conversion unit 636 converts the scrambled tsos into serial data and outputs the serial data to the serial bus 603. As a result, tsos is transmitted from the data transfer apparatus 601 to the data transfer apparatus 602.

  During the transmission of tsos, the transmission circuit 611 periodically transmits a training pattern called a descrambler lock pattern to the data transfer apparatus 602 in order to synchronize the scrambler 635 and the descrambler in the reception circuit 622.

  The training control unit 613 outputs a signal dsc_lock_ptn_send that instructs transmission of the descrambler lock pattern to the pattern generation unit 632. The pattern generation unit 632 generates a descrambler lock pattern data string, and the selector 633 outputs the descrambler lock pattern to the encoder 634.

  The encoder 634 encodes the descrambler lock pattern, and the scrambler 635 scrambles the encoded descrambler lock pattern. The conversion unit 636 converts the scrambled descrambler lock pattern into serial data and outputs the serial data to the serial bus 603. As a result, the descrambler lock pattern is transmitted from the data transfer apparatus 601 to the data transfer apparatus 602.

  When the link initialization is completed, the CRC generation unit 631 adds a CRC to the data string of the normal data packet and outputs it to the selector 633. The training control unit 613 outputs a signal packet_select for selecting the output of the CRC generation unit 631 to the selector 633, and the selector 633 outputs the packet to the encoder 634.

  The encoder 634 encodes the packet, the scrambler 635 scrambles the encoded packet, and the conversion unit 636 converts the scrambled packet into serial data and outputs the serial data to the serial bus 603. As a result, the packet is transmitted from the data transfer apparatus 601 to the data transfer apparatus 602.

  Regardless of the link initialization or after the link initialization is completed, the transmission circuit 611 periodically transmits skpos to the data transfer device 602. The training control unit 613 outputs skpos_send to the pattern generation unit 632. The pattern generation unit 632 generates a skpos data string, and the selector 633 outputs the skpos to the encoder 634.

  The encoder 634 encodes skpos, the scrambler 635 scrambles the encoded skpos, and the conversion unit 636 converts the scrambled skpos into serial data and outputs the serial data to the serial bus 603. As a result, skpos is transmitted from the data transfer apparatus 601 to the data transfer apparatus 602.

  As described above, in the data transfer system of FIG. 6, the LFSR initialization pattern is not used, and only the scrambled transmission data string is output to the serial bus 603. Therefore, the transmission quality is improved as compared with the data transfer system of FIG. To do.

  Next, the operation of the receiving circuit 612 will be described. The transmission circuit 621 of the data transfer apparatus 602 operates in the same manner as the transmission circuit 611 and transmits tsos, a descrambler lock pattern, and skpos to the data transfer apparatus 601. The converter 641 converts the received data string input from the serial bus 603 from serial data to parallel data, and outputs the parallel data to the descrambler 642.

  The descrambler 642 restores the non-scrambled data sequence by descrambling the scrambled received data sequence, and outputs the restored non-scrambled data sequence to the alignment circuit 643.

  The descrambler 642 generates the next LFSR value from the scrambled received data string in the unlocked state, and generates the next LFSR value from the held LFSR value in the locked state. At the start of link initialization, the descrambler 642 is not locked and is locked by receiving a descrambler lock pattern.

  During link initialization, the descrambler 642 synchronizes the scrambler in the transmission circuit 621 and the descrambler 642 based on the descrambler lock pattern, and detects the alignment of the encode blocks. Then, the descrambler 642 outputs to the alignment circuit 643 a signal align_det indicating detection of the boundary of the encoded block and data align_boundary including the boundary of the encoded block.

  The alignment circuit 643 writes the data string output from the descrambler 642 to the write side of the elastic buffer 644 based on the detected boundary of the encoded block. As a result, the read side of the elastic buffer 644 can handle data strings in units of encode blocks.

  The elastic buffer 644 outputs elbf_act to the training control unit 613 when the write operation is continuously performed from the alignment circuit 643. When receiving the elbf_act, the training control unit 613 recognizes that the descrambler 642 has been locked and the encoding block is aligned. When the link initialization is completed, the locked state of the descrambler 642 and the detected encoding block alignment are held.

  The write side of the conversion unit 641, the descrambler 642, the alignment circuit 643, and the elastic buffer 644 is an area of the clock signal rx_clk. In the elastic buffer 644, the transfer from rx_clk to the PCS clock signal pcs_clk is performed.

  The decoder 645 decodes the data string read from the elastic buffer 644 regardless of whether the link initialization is in progress or after the link initialization is completed. At this time, the decoder 645 determines the data type with reference to enc-bit, and outputs a data string such as a descrambler lock pattern, tsos, and skpos to the pattern receiving unit 646. The pattern receiving unit 646 detects tsos from the data string output by the decoder 645 and outputs tsos1_det and tsos2_det to the training control unit 613.

  When link initialization is completed, the CRC checker 647 checks the CRC of the data string output by the decoder 645 and outputs the data string as a packet. The training control unit 613 outputs rx_packet_valid.

  Regardless of link initialization or after link initialization is completed, the decoder 645 outputs decode_error to the training control unit 613 when a decoding error occurs. The CRC checker 647 outputs crc_error to the training control unit 613 when a CRC error occurs.

  The training control unit 613 can detect a synchronization error of the descrambler 642, an alignment error of the encoding block, and the like based on frequent occurrences of decoding errors or CRC errors. When it is estimated that the descrambler 642 is out of synchronization or the encoding block is out of alignment, the training control unit 613 outputs a signal lfsr_re_lock that instructs the descrambler 642 to re-execute synchronization. If link initialization is complete, link initialization is resumed.

  FIG. 7 shows an example of a descrambler lock pattern. The descrambler lock pattern in FIG. 7 includes 2K (K is an integer of 2 or more) encode blocks, and each encode block includes a plurality of bits. Each of the first half K encoded blocks is data ALL0 in which all bits are logical “0”, and each of the second half K encoded blocks is data ALL1 in which all bits are logical “1”.

  Since the exclusive OR of the data ALL0 and the LFSR value becomes the LFSR value, the LFSR value of the scrambler 635 is output to the serial bus 603 as it is when transmitting the first half K encoded blocks. On the other hand, since the exclusive OR of the data ALL1 and the LFSR value is a value obtained by inverting the LFSR value, the value obtained by inverting the LFSR value of the scrambler 635 is output to the serial bus 603 when transmitting the last half K encoded blocks. Is done.

  Therefore, the descrambler 642 can extract the LFSR value of the scrambler of the transmission circuit 621 from the scrambled data ALL0, and can detect the boundary between the data ALL0 and the data ALL1 as the boundary of the encoding block.

  At this time, the descrambler 642 checks that the scrambled data ALL1 is correctly recognized as a value obtained by inverting the LFSR value. This reduces the probability of locking the descrambler 642 at the wrong position. In order to reduce the probability of locking the descrambler 642 at a wrong position, it is desirable that the bit width of the first half K encoded blocks is sufficiently larger than the bit width of the LFSR in the descrambler 642.

For example, when K = 8 and the bit width of one encode block is 20 bits, the bit width of the first eight encode blocks is 160 bits. In addition, when the LFSR polynomial is a 23-order polynomial G (X) = X ²³ + X ²¹ + X ¹⁶ + X ⁸ + X ⁵ + X ² +1, the bit width of the LFSR is 23 bits. In this case, it is considered that the bit widths of the first eight encoding blocks are sufficiently larger than the bit width of the LFSR.

  FIG. 8 shows a configuration example of the scrambler 635 of FIG. The scrambler 635 in FIG. 8 includes an LFSR 801, an OR circuit 802, an FF 803, and an XOR circuit 804. The FF 803 holds the LFSR value, and the XOR circuit 804 outputs the exclusive OR of the LFSR value output from the FF 803 and the input data D5 as scrambled transmission data D6.

  The LFSR 801 updates the LFSR value output from the FF 803, generates the next LFSR value, and outputs it to the OR circuit 802. The OR circuit 802 outputs the logical sum of the LFSR value output from the LFSR 801 and the reset signal R to the FF 803. Except at the time of resetting, the reset signal R is set to logic “0”. As a result, the LFSR value of the FF 803 is updated to the next LFSR value.

  FIG. 9 shows a configuration example of the descrambler 642 of FIG. The descrambler 642 in FIG. 9 includes a control unit 648, an FF 901, a selector 902, an LFSR 903, an OR circuit 904, an FF 905, and an XOR circuit 906. The control unit 648 includes a detection unit 911, a detection unit 912, a determination unit 913, and an FF 914.

  The FF 905 holds the LFSR value, and the XOR circuit 906 outputs an exclusive OR of the LFSR value output from the FF 905 and the scrambled input data D7 as non-scrambled data D8. The FF 901 latches the scrambled input data D 7 and outputs it to the selector 902, thereby matching the bit width of the input data 921 of the selector 902 with the bit width of the FF 905.

  For example, when the LFSR 903 polynomial is a 23-order polynomial, the bit width of the FF 905 is 23 bits. The bit width of the input data D7 is 16 bits. Of the 16-bit input data [15: 0], bit 15 corresponds to the first received bit, and bit 0 corresponds to the last received bit. Think about the case. In this case, the end 7-bit data [6: 0] of the 16-bit data [15: 0] output from the FF 901 and the 16-bit input data [15: 0] are integrated to form a 23-bit data. Input data 921 can be generated.

  The selector 902 is controlled by the signal lfsr_lock output from the determination unit 913, selects the LFSR value output from the input data 921 or the FF 905, and outputs the selected LFSR value to the LFSR 903. The LFSR 903 updates the data output from the selector 902, generates the next LFSR value, and outputs it to the OR circuit 904. The OR circuit 904 outputs the logical sum of the LFSR value output from the LFSR 903 and the reset signal R to the FF 905. Except at the time of resetting, the reset signal R is set to logic “0”. Thereby, the LFSR value of FF905 is updated to the next LFSR value.

  The detection unit 911 is, for example, a comparator, and compares the data D8 output from the XOR circuit 906 with the data ALL0 in which all bits are logic “0”. When the data D8 matches the data ALL0, the detection unit 911 outputs a signal ptn_all0 indicating the detection of the pattern of logic “0” to the determination unit 913.

  The detection unit 912 is, for example, a comparator, and compares the data D8 output from the XOR circuit 906 with the data ALL1 whose all bits are logic “1”. When the data D8 and the data ALL1 match, the detection unit 912 outputs a signal ptn_all1 indicating the detection of the pattern of logic “1” to the determination unit 913.

  The determination unit 913 determines whether a boundary between the descrambler lock pattern and the encode block is detected based on ptn_all0 and ptn_all1 during link initialization. When the descrambler 642 is not locked, the determination unit 913 sets the signal lfsr_lock indicating the locked state of the descrambler 642 to logic “0”. As a result, the selector 902 selects the input data 921 and the LFSR 903 generates the next LFSR value from the input data 921.

  After detecting the descrambler lock pattern, the determination unit 913 sets lfsr_lock to logic “1”. Accordingly, the selector 902 selects the LFSR value output from the FF 905, and the LFSR 903 generates the next LFSR value from the LFSR value output from the FF 905. Thus, the descrambler 642 is locked by the determination unit 913 setting lfsr_lock to logic “1”.

  The determination unit 913 sets align_det to logic “0” when the boundary of the encode block is not detected, and sets align_det to logic “1” when the boundary of the encode block is detected. The FF 914 latches the data D8 output from the XOR circuit 906 and outputs it as align_boundary.

  When the data transfer device 601 and the data transfer device 602 correspond to the data transfer device 401 and the data transfer device 402 in FIG. 4, the LFSR 801 and the XOR circuit 804 in FIG. 8 correspond to the update unit 414 and the randomization unit 412, respectively. To do.

  On the other hand, when the data transfer device 601 and the data transfer device 602 correspond to the data transfer device 402 and the data transfer device 401 in FIG. 4, the LFSR 903 and the XOR circuit 906 in FIG. Correspond.

  According to the data transfer system of FIG. 6, since only the scrambled transmission data string is output to the serial bus 603 even during link initialization, the randomness of the transmission data string is increased and the transmission quality is improved. In addition, since a circuit for distinguishing between scrambled data and unscrambled data becomes unnecessary, the configuration and control of the transmission circuit and the reception circuit are simplified.

  Instead of the descrambler lock pattern shown in FIG. 7, it is also possible to use a descrambler lock pattern in which data ALL1 is set in the first half K encoded blocks and data ALL0 is set in the second half K encode blocks. .

  10A and 10B are flowcharts illustrating an example of operations performed by the determination unit 913 in FIG. When the determination unit 913 starts data determination (step 1001), the determination unit 913 shifts to an idle state, and sets lfsr_lock and align_det to logic “0” (step 1002). Then, the determination unit 913 sets a pattern counter representing the count value to 0 (step 1003).

  Next, the determination unit 913 checks the value of ptn_all0 output from the detection unit 911 (step 1004). If ptn_all0 is logic “0” (step 1004, NO), the operation after step 1003 is repeated. On the other hand, when ptn_all0 is logic “1” (step 1004, YES), the determination unit 913 increments the pattern counter by 1 (step 1005). Then, the determination unit 913 compares the pattern counter with a threshold value TH1 for the number of times ALL0 has been detected (step 1006).

  When the pattern counter is smaller than TH1 (step 1006, NO), the determination unit 913 repeats the operations after step 1004. On the other hand, when the pattern counter reaches TH1 (step 1006, YES), the determination unit 913 sets lfsr_lock to logic “1” (step 1007), sets the pattern counter to 0, and shifts to the prelock state. (Step 1008). The prelock state represents a state in which ALL0 in the first half of the descrambler lock pattern is detected.

  Next, the determination unit 913 checks the value of ptn_all1 output from the detection unit 912 (step 1009). When ptn_all1 is logic “0” (step 1009, NO), the determination unit 913 increments the pattern counter by 1 (step 1010). Then, the determination unit 913 compares the pattern counter with a threshold value TH2 for the number of times that ALL1 has not been detected (step 1011).

  When the pattern counter is smaller than TH2 (step 1011, NO), the determination unit 913 repeats the operations after step 1009. On the other hand, when the pattern counter reaches TH2 (step 1011, YES), the determination unit 913 repeats the operations after step 1002. In this case, the determination unit 913 determines that the descrambler lock pattern has not been detected, returns to the idle state, and resets the pattern counter to 0.

  When ptn_all1 is logic “1” (step 1009, YES), the determination unit 913 sets align_det to logic “1” (step 1012), sets 0 to the pattern counter, and shifts to the det state ( Step 1013). The det state represents a state in which the boundary of the encode block included in the descrambler lock pattern is detected.

  Next, the determination unit 913 checks the value of ptn_all1 (step 1014). If ptn_all1 is logic “0” (step 1014, NO), the operation from step 1002 is repeated. In this case, the determination unit 913 determines that the descrambler lock pattern has not been detected, returns to the idle state, and resets the pattern counter to 0.

  On the other hand, when ptn_all1 is logic “1” (step 1014, YES), the determination unit 913 increments the pattern counter by 1 (step 1015). Then, the determination unit 913 compares the pattern counter with a threshold value TH3 for the number of times ALL1 has been detected (step 1016).

  When the pattern counter is smaller than TH3 (step 1016, NO), the determination unit 913 repeats the operations after step 1014. On the other hand, when the pattern counter reaches TH3 (step 1016, YES), the determination unit 913 sets the pattern counter to 0 and shifts to the lock state (step 1017). The lock state represents a state in which the entire descrambler lock pattern is detected.

  When the alignment_det is set to logic “1”, the alignment circuit 643 starts writing to the elastic buffer 644. At this time, the elastic buffer 644 sets elbf_act to logic “1” to indirectly indicate that both the synchronization of the descrambler 642 and the alignment of the encode block have been completed. To notify.

  Next, the determination unit 913 checks the value of lfsr_re_lock output from the training control unit 613 (step 1018). If lfsr_re_lock is logic “1” (step 1018, YES), the operation after step 1002 is repeated. In this case, the determination unit 913 returns to the idle state and resumes link initialization.

  On the other hand, when lfsr_re_lock is logic “0” (step 1018, NO), the determination unit 913 determines whether or not to end the data determination (step 1019). When the data determination is not completed (step 1019, NO), the determination unit 913 repeats the operations after step 1018. Therefore, the determination unit 913 maintains the lock state unless the training control unit 613 instructs to re-execute synchronization.

  On the other hand, when the data determination is finished (step 1019, YES), the determination unit 913 ends the operation. For example, when the power of the descrambler 642 is turned off or when an operation stop instruction is received from the training control unit 613, it is determined that the data determination is finished.

  10A and 10B, the descrambler lock pattern can be used to simultaneously perform descrambler 642 synchronization and encode block alignment.

  In step 1006, it can be confirmed that the first half of the descrambler lock pattern has been detected by comparing the pattern counter with TH1. If a data string different from the first half of the descrambler lock pattern is received, the pattern counter can be reset and the descrambler lock pattern can be detected again.

  Further, in step 1011, by comparing the pattern counter with TH2, it is possible to redo the detection of the descrambler lock pattern after confirming that the latter half of the descrambler lock pattern has not been detected.

  Furthermore, in step 1016, it is possible to confirm that the latter half of the descrambler lock pattern has been detected by comparing the pattern counter with TH3. When a data string different from the latter half of the descrambler lock pattern is received, the pattern counter can be reset and the descrambler lock pattern can be detected again.

  FIG. 11 is a timing chart illustrating an example of an operation performed by the descrambler 642. In FIG. 11, each period from t0 to t22 corresponds to one cycle of the clock signal rx_clk.

  The state represents the state of the determination unit 913, scramble receive data [15: 0] represents 16-bit input data D7, and shft-reg output [15: 0] represents 16-bit data output by the FF 901. To express.

  The next lfsr input [22: 0] represents the 23-bit data output from the selector 902, and the next lfsr output [22: 0] represents the 23-bit data output from the LFSR 903. The lfsr-reg output [22: 0] represents the 23-bit data output from the FF 905, and the non-scramble receive data [15: 0] represents the 16-bit non-scrambled data D8.

  It is assumed that the bit width of one encode block is 20 bits, and the descrambler lock pattern includes the first half 8 data ALL0 and the second half 8 data ALL1. The LFSR in the transmission circuit 621 generates a continuous 320-bit LFSR value bit_ptn [0: 319], of which bit 0 is the first bit and bit 319 is the last bit.

  In this case, data obtained by scrambling the first eight ALL0s of the descrambler lock pattern is bit_ptn [0: 159] itself. “0: 8” or the like of scramble receive data [15: 0] represents a bit string corresponding to bit_ptn [0: 319].

On the other hand, the data obtained by scrambling the latter eight ALL1s is a value obtained by inverting bit_ptn [160: 319]. “ 160: 168 ” or the like of scramble receive data [15: 0] represents a value obtained by inverting the corresponding bit string of bit_ptn [0: 319].

  For example, TH1 in step 1006, TH2 in step 1011, and TH3 in step 1016 are determined so as to satisfy the following equation, for example.

1 ≦ TH1 ≦ (B1-B2) / B3-2 (1)
TH2 ≧ (B1-B2) / B3-TH1 + 1 (2)
1 ≦ TH3 ≦ B4 / B3-3 (3)

  B1 represents the bit width of the first K ALL0s of the descrambler lock pattern, B2 represents the bit width of the LFSR 903, B3 represents the bit width of the input data D7, and B4 represents the second half of the descrambler lock pattern. It represents the bit width of K ALL1s. When K = 8, B1 = B4 = 160, B2 = 23, and B3 = 16, the equations (1) and (3) are replaced by the following equations.

1 ≦ TH1 ≦ 6.56 (4)
1 ≦ TH3 ≦ 7 (5)

  When TH1 = 5, the expression (2) is replaced by the following expression.

TH2 ≧ 4.56 (6)

  In each period from t0 to t8 when the descrambler 642 is not yet locked, since lfsr_lock = 0, the selector 902 outputs the input data 921 to the LFSR 903. Therefore, the shift_reg output [6: 0] in the period one cycle before and the scramble receive data [15: 0] in the period are mixed in the next_lfsr input [22: 0].

  In this case, the LFSR 903 updates the next_lfsr input [22: 0] by 16 bits corresponding to the number of bits of the scramble receive data [15: 0], generates the next LFSR value, and outputs the next lfsr output [22: 0] is output. Then, the FF 905 outputs the next LFSR value generated by the LFSR 903 as the lfsr-reg output [22: 0] in the next period.

  For example, in the period t2, the LFSR 903 generates bit_ptn [18:40] by updating bit_ptn [2:24] input as the next_lfsr input [22: 0] by 16 bits, and generates the next lfsr output [22]. : 0]. Then, the FF 905 outputs bit_ptn [18:40] as the lfsr-reg output [22: 0] in the period t3.

  While receiving descrambler lock pattern ALL0, non-scramble receive data [15: 0] is ALL0, and ptn_all0 is set to logic “1”. When ptn_all0 = 1 is detected continuously for the prescribed number of times corresponding to TH1, lfsr_lock is set to logic “1”, and the determination unit 913 enters the prelock state. For example, when TH1 = 5, since pattern counter = 5 in period t8, lfsr_lock = 1 in period t9.

  When lfsr_lock = 1, the selector 902 outputs the lfsr-reg output [22: 0] to the LFSR 903. Therefore, next_lfsr input [22: 0] = lfsr-reg output [22: 0]. For example, in the period t9, bit_ptn [114: 136] output from the FF 905 as the lfsr-reg output [22: 0] is input to the LFSR 903 as the next_lfsr input [22: 0].

  Next, in the period t12, when non-scramble receive data [15: 0] becomes ALL1, ptn_all1 is set to logic “1”, and align_det is set to logic “1”. At this time, the FF 914 outputs non-scramble received data [15: 0] in the period t11 one cycle before as align_boundary.

  When the descrambler 642 is correctly locked, the alignment_boundary is an ALL0 pattern or a pattern including only one switching between “0” and “1” such as “00..001111.11”. In this example, the alignment_boundary in the period t12 is a bit string {7′h00, 9′h1ff} including 7 bits “0” and 9 bits “1”.

{7′h00, 9′h1ff} = “0000000111111111” (7)

  In this case, the switching position between “0” and “1” included in the alignment_boundary indicates the boundary of the encoding block. Thereafter, in the period t13, the determination unit 913 enters the det state.

  In the det state, when ptn_all1 = 1 is continuously detected for a specified number of times corresponding to TH3, the determination unit 913 enters the lock state. For example, when TH3 = 4, pattern counter = 4 in the period t17, so that the determination unit 913 enters the locked state in the period t18. Thereafter, in a period t21, a training pattern such as tsos is input to the descrambler 642.

  12A and 12B are flowcharts illustrating an example of operations performed by the reception sequence controller 652 of FIG. The reception sequence controller 652 can be in three states: stage 0 to stage 2. Stage 0 and stage 1 are in a state of link initialization, and stage 2 is a state in which link initialization is completed.

  When starting the link initialization, the reception sequence controller 652 sets lfsr_re_lock and rx_packet_valid to logic “0”, and proceeds to stage 0 (step 1201).

  Next, the reception sequence controller 652 checks the value of elbf_act output from the elastic buffer 644 (step 1202). If elbf_act is logic “1” (step 1202, YES), the reception sequence controller 652 determines whether or not to synchronize the descrambler 642 again (step 1203).

  At this time, the reception sequence controller 652 counts the number of times the decoder 645 has output decode_error and the number of times that the CRC checker 647 has output crc_error. The reception sequence controller 652 determines that the synchronization of the descrambler 642 is executed again if any of the numbers is equal to or greater than the predetermined number of times, and the synchronization of the descrambler 642 is determined if any of the numbers is less than the predetermined number of times. Is determined not to be executed again.

  When synchronization of the descrambler 642 is executed again (step 1203, YES), the reception sequence controller 652 sets lfsr_re_lock to logic “1” (step 1204) and checks the value of elbf_act (step 1205).

  When lfsr_re_lock is set to logic “1”, the descrambler 642 sets align_det to logic “0”. The alignment circuit 643 stops writing to the elastic buffer 644, and the elastic buffer 644 sets elbf_act to logic “0”. Therefore, the reception sequence controller 652 can recognize that the resynchronization instruction has been transmitted to the descrambler 642 by detecting the change in elbf_act.

  When elbf_act is logic “1” (step 1205, NO), the reception sequence controller 652 repeats the operation of step 1205. On the other hand, when elbf_act is logic “0” (step 1205, YES), the reception sequence controller 652 sets lfsr_re_lock to logic “0” (step 1206), and checks the value of elbf_act (step 1207).

  When descrambler 642 resumes synchronization and sets align_det to logic “1”, alignment circuit 643 resumes writing to elastic buffer 644 and elastic buffer 644 sets elbf_act to logic “1”. . Therefore, the reception sequence controller 652 can recognize that the resynchronization of the descrambler 642 has been completed by detecting the change in elbf_act.

  When elbf_act is logic “0” (step 1207, NO), the reception sequence controller 652 repeats the operation of step 1207. On the other hand, when elbf_act is logic “1” (step 1207, YES), the reception sequence controller 652 checks the values of tsos1_det and tsos2_det output from the pattern reception unit 646 (step 1208). In the state of stage 0 and when tsos1_det or tsos2_det is logic “1” (step 1208, YES), the reception sequence controller 652 proceeds to stage 1 (step 1209).

  Next, the reception sequence controller 652 checks the value of tsos2_det (step 1210). In the state of stage 1 and when tsos2_det is logic “1” (step 1210, YES), the reception sequence controller 652 finishes link initialization and starts receiving packets (step 1211). Then, the reception sequence controller 652 moves to stage 2 and sets rx_packet_valid to logic “1”.

  Next, the reception sequence controller 652 checks the value of tsos1_det (step 1212). When tsos1_det is logic “0” (step 1212, NO), the reception sequence controller 652 determines whether or not to synchronize the descrambler 642 again as in step 1203 (step 1213).

  When synchronization of the descrambler 642 is not executed again (step 1213, NO), the reception sequence controller 652 determines whether or not to end the packet reception (step 1214). When the reception of the packet is not finished (step 1214, NO), the reception sequence controller 652 repeats the operations after step 1212. On the other hand, when the reception of the packet is ended (step 1214, YES), the reception sequence controller 652 ends the operation.

  In step 1202, when elbf_act is logic “0” (step 1202, NO), the reception sequence controller 652 performs the operation after step 1207. If the synchronization of the descrambler 642 is not executed again at step 1203 (step 1203, NO), the reception sequence controller 652 performs the operations after step 1206.

  In step 1208, if both tsos1_det and tsos2_det are logic “0” or in the state of stage 1 (step 1208, NO), the reception sequence controller 652 performs the operation from step 1210 onward. In step 1210, when tsos2_det is logic “0” or in the state of stage 0 (step 1210, NO), the reception sequence controller 652 repeats the operations after step 1202.

  If tsos1_det is logic “1” in step 1212 (step 1212, YES), the reception sequence controller 652 repeats the operations in and after step 1201. In step 1213, when the descrambler 642 is synchronized again (YES in step 1213), the reception sequence controller 652 performs the operations in and after step 1201.

  13A to 13C are flowcharts illustrating an example of operations performed by the transmission sequence controller 651 in FIG. During link initialization, the transmission sequence controller 651 switches between tsos1 and tsos2 for transmission according to the state of the reception sequence controller 652.

  When the state of the reception sequence controller 652 is stage 0, tsos1 is transmitted, and when it is stage 1, tsos2 is transmitted. Immediately after the reception sequence controller 652 shifts to stage 2, M (M is an integer of 2 or more) tsos2 are transmitted to guarantee transmission of tsos2 to the data transfer apparatus 602.

  First, the transmission sequence controller 651 sets skpos_send counter and dsc_lock_ptn counter to 0 (step 1301). The skpos_send counter is a count value indicating the transmission timing of skpos, and the dsc_lock_ptn counter is a count value indicating the transmission timing of the descrambler lock pattern.

  Next, the transmission sequence controller 651 starts link initialization, and sets packet_select, tsos2_send, dsc_lock_ptn_send, and skpos_send to logic “0” (step 1302). The transmission sequence controller 651 sets tsos1_send to logic “1”. Thereby, the pattern generation unit 632 generates tsos1 and the transmission circuit 611 transmits tsos1 to the data transfer device 602.

  Next, the transmission sequence controller 651 checks whether or not the transmission circuit 611 has transmitted one encode block (step 1303). When the transmission circuit 611 is transmitting one encode block (step 1303, NO), the transmission sequence controller 651 repeats the operation of step 1303.

  On the other hand, when the transmission circuit 611 transmits one encode block (step 1303, YES), the transmission sequence controller 651 increments skpos_send counter by 1 (step 1304). Then, the transmission sequence controller 651 checks whether or not the transmitted encoded block is at the end of tsos (step 1305). If the transmitted encoded block is not at the end of tsos (step 1305, NO), the transmission sequence controller 651 repeats the operations after step 1303.

  On the other hand, when the transmitted encoded block is the end of tsos (step 1305, YES), the transmission sequence controller 651 increments dsc_lock_ptn counter by 1 (step 1306). Then, the transmission sequence controller 651 compares the skpos_send counter with the threshold value TH4 (step 1307).

  If skpos_send counter is greater than TH4 (step 1307, YES), the transmission sequence controller 651 sets skpos_send to logic “1” (step 1308). As a result, the pattern generation unit 632 generates skpos, and the transmission circuit 611 transmits skpos to the data transfer device 602. However, when the tsos or descrambler lock pattern is being transmitted, skpos is transmitted after waiting for the completion of the transmission.

  Next, the transmission sequence controller 651 checks whether or not the transmission circuit 611 has transmitted skpos (step 1309). When the transmission circuit 611 is transmitting skpos (step 1309, NO), the transmission sequence controller 651 repeats the operation of step 1309.

  On the other hand, when the transmission circuit 611 transmits skpos (step 1309, YES), the transmission sequence controller 651 sets skpos_send to logic “0” and sets skpos_send counter to 0 (step 1310). Then, the transmission sequence controller 651 compares the dsc_lock_ptn counter with the threshold value TH5 (step 1311).

  If dsc_lock_ptn counter is larger than TH5 (step 1311, YES), the transmission sequence controller 651 sets dsc_lock_ptn_send to logic “1” (step 1312). Thereby, the pattern generation unit 632 generates a descrambler lock pattern, and the transmission circuit 611 transmits the descrambler lock pattern to the data transfer device 602.

  Next, the transmission sequence controller 651 checks whether or not the transmission circuit 611 has transmitted a descrambler lock pattern (step 1313). When the transmission circuit 611 is transmitting the descrambler lock pattern (step 1313, NO), the transmission sequence controller 651 repeats the operation of step 1313.

  On the other hand, when the transmission circuit 611 transmits the descrambler lock pattern (step 1313, YES), the transmission sequence controller 651 sets dsc_lock_ptn_send to logic “0” (step 1314). Then, the transmission sequence controller 651 sets dsc_lock_ptn counter to 0.

  Next, the transmission sequence controller 651 checks the state of the reception sequence controller 652 (step 1315). When the state of the reception sequence controller 652 is stage 0 (step 1315, NO), the transmission sequence controller 651 repeats the operations after step 1302.

  On the other hand, when the state of the reception sequence controller 652 is stage 1 or stage 2 (step 1315, YES), the transmission sequence controller 651 sets tsos1_send to logic “0” (step 1316). Then, the transmission sequence controller 651 sets tsos2_send to logic “1”. Thereby, the pattern generation unit 632 generates tsos2, and the transmission circuit 611 transmits tsos2 to the data transfer device 602.

  Next, the transmission sequence controller 651 checks the state of the reception sequence controller 652 (step 1317). When the state of the reception sequence controller 652 is stage 0 or stage 1 (step 1317, NO), the transmission sequence controller 651 repeats the operations after step 1303.

  On the other hand, when the state of the reception sequence controller 652 is stage 2 (step 1317, YES), the transmission sequence controller 651 checks whether or not the transmission circuit 611 has transmitted M tsos2 (step 1318). When the transmission circuit 611 has not transmitted M tsos2 (step 1318, NO), the transmission sequence controller 651 repeats the operation of step 1318.

  On the other hand, when the transmission circuit 611 transmits M tsos2 (step 1318, YES), the transmission sequence controller 651 ends link initialization and starts packet transmission (step 1319). Then, the transmission sequence controller 651 sets tsos2_send to logic “0”, and sets packet_select to logic “1”.

  Next, the transmission sequence controller 651 determines whether or not to end the packet transmission (step 1320). If the packet transmission is not finished (step 1320, NO), the transmission sequence controller 651 checks whether or not the reception sequence controller 652 has resumed link initialization (step 1321). When the reception sequence controller 652 resumes link initialization (step 1321, YES), the transmission sequence controller 651 repeats the operations after step 1302.

  On the other hand, if the reception sequence controller 652 has not resumed link initialization (step 1321, NO), the transmission sequence controller 651 checks whether or not the transmission circuit 611 has transmitted one encode block (step 1322). ). When the transmission circuit 611 is transmitting one encode block (step 1322, NO), the transmission sequence controller 651 repeats the operations after step 1320.

  On the other hand, when the transmission circuit 611 transmits one encode block (step 1322, YES), the transmission sequence controller 651 increments skpos_send counter by 1 (step 1323). Then, the transmission sequence controller 651 compares the skpos_send counter with the threshold value TH4 (step 1324). When skpos_send counter is equal to or lower than TH4 (step 1324, NO), the transmission sequence controller 651 repeats the operations after step 1320.

  On the other hand, when skpos_send counter is larger than TH4 (step 1324, YES), the transmission sequence controller 651 checks whether or not the transmission circuit 611 can transmit skpos (step 1325). When the packet is being transmitted, it is determined that the transmission of the skpos is impossible. When the packet is not being transmitted or when the transmission of the packet is completed, it is determined that the transmission of the skpos is possible.

  When transmission of skpos is impossible (step 1325, NO), the transmission sequence controller 651 repeats the operation of step 1325. On the other hand, when transmission of skpos is possible (step 1325, YES), the transmission sequence controller 651 sets skpos_send to logic “1” (step 1326). Then, the transmission sequence controller 651 sets packet_select to logic “0”.

  Next, the transmission sequence controller 651 checks whether or not the transmission circuit 611 has transmitted skpos (step 1327). When the transmission circuit 611 is transmitting skpos (step 1327, NO), the transmission sequence controller 651 repeats the operation of step 1327.

  On the other hand, when the transmission circuit 611 transmits skpos (step 1327, YES), the transmission sequence controller 651 sets skpos_send to logic “0” and packet_select to logic “1” (step 1328). Then, the transmission sequence controller 651 sets skpos_send counter to 0, and repeats the operations from step 1320 onward.

  If the skpos_send counter is equal to or lower than TH4 in step 1307 (step 1307, NO), the transmission sequence controller 651 performs the operation from step 1311 onward. If dsc_lock_ptn counter is equal to or lower than TH5 in step 1311 (step 1311, NO), the transmission sequence controller 651 performs the operation after step 1315. In step 1320, when the transmission of the packet is ended (step 1320, YES), the transmission sequence controller 651 ends the operation.

  FIG. 14 is a timing chart showing an example of the operation of the transmission sequence controller. In FIG. 14, each period of u0, u2 to u3, u5, u6, u8, u9, u11 to u13, u15 to u17, u19, u21, and u22 corresponds to a time for transmitting 16 encoded blocks. On the other hand, each of the periods u1, u4, u7, u10, u14, u18, and u20 corresponds to a time for transmitting a larger number of encode blocks, and is shortened from the actual time by cutting in the middle of the period. Has been.

  TX represents the operation of the transmission sequence controller 651, RX represents the operation of the reception sequence controller 652, and non-encode send data represents the data output from the selector 633 of the transmission circuit 611. Non-encoded send data TSOS1, TSOS2, and SKPOS represent tsos1, tsos2, and skpos composed of 16 encoded blocks. dsc_lock_ptn represents a descrambler lock pattern composed of 16 encoded blocks, and includes 8 data ALL0 in the first half and 8 data ALL1 in the second half.

  In this example, TH4 in step 1307 and step 1324 is 1500, TH5 in step 1311 is 15, and M in step 1318 is 16.

  In each period from u0 to u9 during link initialization, since the state of the reception sequence controller 652 is stage 0, tsos1_send is set to logic “1” and TSOS1 is transmitted. Since skpos_send counter = 1501> TH4 at the end of period u1, skpos_send is set to logic “1” and SKPOS is transmitted in period u2 after transmission of TSOS1 is completed.

  Further, since dsc_lock_ptn counter = 16> TH5 in the period u5, dsc_lock_ptn_send is set to logic “1”, and dsc_lock_ptn is transmitted. Similarly, in the period u8, dsc_lock_ptn counter = 16, so dsc_lock_ptn is transmitted.

  Next, in each period from u10 to u16, since the state of the reception sequence controller 652 is stage 1, tsos1_send is set to logic “0”, tsos2_send is set to logic “1”, and TSOS2 is transmitted. . Since skpos_send counter = 1501 at the end of period u10, SKPOS is transmitted in period u11 after completion of transmission of TSOS2. Further, since dsc_lock_ptn counter = 16 in the period u15, dsc_lock_ptn is transmitted.

  Next, in the period u17 and the period u18 immediately after the reception sequence controller 652 shifts to the stage 2, 16 TSOS2s are transmitted. Then, in the period u19 in which the transmission of the 16 TSOSs 2 is completed, the transmission sequence controller 651 completes the link initialization and starts transmitting the packets packet (1) to packet (N + 1). Thereafter, since skpos_send counter = 1501 at the end of the period u20, SKPOS is transmitted in the period u21 after waiting for the completion of transmission of the packet (N).

  FIG. 15 shows a configuration example of an information processing system corresponding to the data transfer system of FIG. The information processing system in FIG. 15 includes a central processing unit (CPU) 1501, a memory control unit (MCU) 1502, and a memory 1503. The information processing system further includes an input / output unit (IOU) 1504, adapters 1505 to 1507, and a read only memory (ROM) 1508.

The MCU 1502 controls access from the CPU 1501 (processor) and the IOU 1504 to the memory 1503, and the adapters 1505 to 1507 perform data communication with peripheral devices. The adapter 1506 communicates with the ROM 1508, and the adapter 1507 communicates with other devices via a local area network (LAN). The IOU 1504 controls the adapters 1505 to 1507. In this case, the serial bus 603 in FIG. 6 can be used for connection between the following devices.
(A) Connection between CPU 1501 and MCU 1502 (b) Connection between MCU 1502 and IOU 1504 (c) Connection between IOU 1504 and adapter 1505 (d) Connection between IOU 1504 and adapter 1506 (e) Connection between IOU 1504 and adapter 1507 (f) Connection between adapter 1506 and ROM 1508 Connection

  The data transfer device 601 and the data transfer device 602 are mounted as communication large-scale integrated circuits (LSIs) in devices located at both ends of the serial bus 603.

  The configuration of the data transfer system in FIGS. 1, 4, and 6 is merely an example, and some components may be omitted or changed according to the use or conditions of the data transfer system. For example, in the data transfer system of FIG. 6, when the data transfer apparatus 601 performs only a transmission operation, the reception circuit 612 and the reception sequence controller 652 can be omitted. Similarly, when the data transfer device 602 performs only the reception operation, the transmission circuit 621 can be omitted.

  The configurations of the scrambler of FIGS. 2 and 8 and the descrambler of FIGS. 3 and 9 are merely examples, and some components may be omitted or changed according to the use or conditions of the data transfer system.

  The configuration of the information processing system in FIG. 15 is merely an example, and some components may be omitted or changed according to the use or conditions of the information processing system. The data transfer systems of FIGS. 1, 4, and 6 can also be applied to a large-scale information processing system including a plurality of CPUs.

  The descrambler lock pattern in FIG. 7 is merely an example, and another descrambler lock pattern may be used according to the configuration or conditions of the data transfer system. For example, the number of encoding blocks in the first half and the second half may be different, and a predetermined data string other than ALL0 or ALL1 may be used as the descrambler lock pattern.

  The flowcharts of FIGS. 5, 10A, 10B, 12A, 12B, and 13A to 13C are merely examples, and some processes may be omitted or changed depending on the configuration or conditions of the data transfer system. Good.

  The timing charts of FIGS. 11 and 14 are merely examples, and the timing charts change according to the configuration or conditions of the data transfer system. Another training pattern may be used instead of tsos or skpos.

  TH1 to TH3 in Expressions (1) to (6) are merely examples, and different threshold values may be used according to the descrambler lock pattern.

  Although the disclosed embodiments and their advantages have been described in detail, those skilled in the art can make various modifications, additions and omissions without departing from the scope of the present invention as explicitly set forth in the claims. Let's go.

Regarding the embodiment described with reference to FIGS. 1 to 15, the following additional notes are disclosed.
(Appendix 1)
In the first period, a first transmission data sequence including the first random number, which is generated by scrambling the first data sequence using the first random number, is received from the data transmission device, and in the second period, A receiving unit that receives, from the data transmission device, a second transmission data sequence including the second random number generated by scrambling the second data sequence using a second random number obtained by updating the first random number When,
An update unit that updates the first random number included in the first transmission data sequence received by the reception unit and generates the second random number;
A restoration unit that restores the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the second random number generated by the update unit;
A control unit that controls the update unit to update the generated random number when the second data sequence restored by the restoration unit is a predetermined data sequence;
A data transfer device comprising:
(Appendix 2)
The receiving unit receives a plurality of transmission data sequences including the second transmission data sequence from the data transmission device in each of a plurality of periods including the second period,
The restoration unit restores a plurality of data strings including the second data string from the plurality of transmission data strings by descrambling the plurality of transmission data strings;
The controller is
A first detection unit for detecting the predetermined data sequence from the plurality of data sequences restored by the restoration unit;
The first detection unit counts the number of times that the predetermined data string is detected, and when the number of times that the predetermined data string is detected reaches the first predetermined number, a control signal that instructs to update the generated random number A determination unit for outputting to the update unit;
The data transfer device as set forth in appendix 1, wherein:
(Appendix 3)
The control unit further includes a second detection unit that detects a data sequence different from the predetermined data sequence from the plurality of data sequences restored by the restoration unit,
The determination unit counts the number of times the second detection unit does not detect the different data sequence after the number of times the predetermined data sequence is detected reaches the first predetermined number of times, and determines the different data sequence. The supplementary note 2, wherein when the number of times of not detecting reaches a second predetermined number of times, the control signal is canceled and the number of times that the first detecting unit detects the predetermined data string is reset. Data transfer device.
(Appendix 4)
The determination unit counts the number of times the second detection unit detects the different data sequence after the number of times the predetermined data sequence is detected reaches the first predetermined number of times, and detects the different data sequence. The data transfer according to claim 2 or 3, wherein when the number of times does not reach the third predetermined number of times, the control signal is canceled and the number of times that the first detection unit detects the predetermined data string is reset. apparatus.
(Appendix 5)
The data transfer apparatus according to appendix 4, wherein the reception unit receives a scrambled training pattern from the data transmission apparatus after the number of times the different data strings are detected reaches the third predetermined number of times.
(Appendix 6)
A data transfer system comprising a first data transfer device and a second data transfer device,
The first data transfer device includes:
A generating unit that generates a first data string and a second data string;
A first updating unit for updating the first random number to generate a second random number;
By scrambling the first data sequence using the first random number, a first transmission data sequence including the first random number is generated, and by scrambling the second data sequence using the second random number. A randomizing unit for generating a second transmission data sequence including the second random number;
A transmission unit that transmits the first transmission data sequence to the second data transfer device in a first period, and transmits the second transmission data sequence to the second data transfer device in a second period;
The second data transfer device includes:
A receiving unit that receives the first transmission data sequence from the first data transfer device in the first period and receives the second transmission data sequence from the first data transfer device in the second period;
A second updating unit for updating the first random number included in the first transmission data sequence received by the receiving unit and generating the second random number;
A restoration unit for restoring the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the second random number generated by the second update unit;
A control unit that controls the second update unit so as to update the generated random number when the second data sequence restored by the restoration unit is a predetermined data sequence;
A data transfer system characterized by that.
(Appendix 7)
The receiving unit receives a plurality of transmission data sequences including the second transmission data sequence from the first data transfer device in each of a plurality of periods including the second period,
The restoration unit restores a plurality of data strings including the second data string from the plurality of transmission data strings by descrambling the plurality of transmission data strings;
The controller is
A first detection unit for detecting the predetermined data sequence from the plurality of data sequences restored by the restoration unit;
The first detection unit counts the number of times that the predetermined data string is detected, and when the number of times that the predetermined data string is detected reaches the first predetermined number, a control signal that instructs to update the generated random number A determination unit for outputting to the second update unit;
The data transfer system according to appendix 6, characterized by comprising:
(Appendix 8)
The control unit further includes a second detection unit that detects a data sequence different from the predetermined data sequence from the plurality of data sequences restored by the restoration unit,
The determination unit counts the number of times the second detection unit does not detect the different data sequence after the number of times the predetermined data sequence is detected reaches the first predetermined number of times, and determines the different data sequence. 8. The supplementary note 7, wherein when the number of times of not detecting reaches a second predetermined number of times, the control signal is canceled and the number of times that the first detecting unit detects the predetermined data string is reset. Data transfer system.
(Appendix 9)
The determination unit counts the number of times the second detection unit detects the different data sequence after the number of times the predetermined data sequence is detected reaches the first predetermined number of times, and detects the different data sequence. The data transfer according to appendix 7 or 8, wherein when the number of times does not reach the third predetermined number of times, the control signal is canceled and the number of times the first detection unit detects the predetermined data string is reset. system.
(Appendix 10)
The data transfer according to claim 9, wherein the receiving unit receives the scrambled training pattern from the first data transfer device after the number of times the different data strings are detected reaches the third predetermined number of times. system.
(Appendix 11)
A control method of a data transfer system comprising a first data transfer device and a second data transfer device,
The first data transfer device generates a first transmission data sequence including the first random number by scrambling the first data sequence using a first random number,
In the first period, the first data transfer device transmits the first transmission data string to the second data transfer device,
The second data transfer device receives the first transmission data string from the first data transfer device;
The second data transfer device updates the first random number included in the received first transmission data sequence to generate the second random number;
The first data transfer device updates the first random number to generate the second random number;
The first data transfer device generates a second transmission data sequence including the second random number by scrambling the second data sequence using the second random number,
In the second period, the first data transfer device transmits the second transmission data string to the second data transfer device,
The second data transfer device receives the second transmission data string from the first data transfer device;
The second data transfer device restores the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the generated second random number,
The second data transfer device updates the generated random number when the restored second data string is a predetermined data string;
A method for controlling a data transfer system.
(Appendix 12)
The first data transfer device generates a plurality of transmission data sequences including the second transmission data sequence by scrambling a plurality of data sequences including the second data sequence,
In each of a plurality of periods including the second period, the first data transfer device transmits the plurality of transmission data strings to the second data transfer device,
The second data transfer device receives the plurality of transmission data strings from the first data transfer device;
The second data transfer device descrambles the plurality of transmission data sequences to restore the plurality of data sequences from the plurality of transmission data sequences,
The second data transfer device detects the predetermined data sequence from the restored plurality of data sequences,
Counting the number of times the second data transfer device has detected the predetermined data string;
The second data transfer device updates the generated random number when the number of times the predetermined data string is detected reaches the first predetermined number of times;
The control method according to appendix 11, wherein:
(Appendix 13)
The second data transfer device counts the number of times that the predetermined data string is not detected after the number of times the predetermined data string is detected reaches the first predetermined number of times,
When the second data transfer device does not detect the different data string reaches a second predetermined number, the control signal is canceled and the number of times the predetermined data string is detected is reset;
The control method according to supplementary note 12, characterized by:
(Appendix 14)
The second data transfer device detects the different data string from the plurality of data strings after the number of times the predetermined data string is detected reaches the first predetermined number of times;
Counting the number of times the second data transfer device has detected the different data strings;
If the number of times that the second data transfer device has detected the different data sequence does not reach the third predetermined number of times, the control signal is canceled and the number of times the predetermined data sequence is detected is reset;
14. The control method according to appendix 12 or 13, characterized in that.
(Appendix 15)
15. The supplementary note 14, wherein the second data transfer device receives a scrambled training pattern from the first data transfer device after the number of times the different data strings are detected reaches the third predetermined number of times. Control method.

101, 102, 401, 402, 601, 602 Data transfer device 103, 603 Serial bus 111, 611 Transmission circuit 112, 612 Reception circuit 113, 123, 613, 623 Training control unit 121, 621 Transmission circuit 122, 622 Reception circuit 131 , 631 CRC generation unit 132, 632 Pattern generation unit 133, 135, 202, 302, 633, 902 Selector 134, 635 Scrambler 136, 634 Encoder 137, 141, 636, 641 Conversion unit 142, 643 Alignment circuit 143 Alignment detection unit 144, 644 Elastic buffer 145, 645 Decoder 146, 642 Descrambler 147, 646 Pattern receiver 148, 647 CRC checker 151, 651 Transmission sequence Controller 152,652 receive sequence controller 201,301,801,903 LFSR
203, 303, 802, 904 OR circuit 205, 305, 804, 906 XOR circuit 204, 304, 803, 901, 905, 914 FF
411 generation unit 412 randomization unit 413 transmission unit 414, 423 update unit 421 reception unit 422 restoration unit 424, 648 control unit 911, 912 detection unit 913 determination unit 921 input data 1501 CPU
1502 MCU
1503 Memory 1504 IOU
1505-1507 Adapter 1508 ROM

Claims (6)

In the first period, a first transmission data sequence including the first random number, which is generated by scrambling the first data sequence using the first random number, is received from the data transmission device, and in the second period, A receiving unit that receives, from the data transmission device, a second transmission data sequence including the second random number generated by scrambling the second data sequence using a second random number obtained by updating the first random number When,
An update unit that updates the first random number included in the first transmission data sequence received by the reception unit and generates the second random number;
A restoration unit that restores the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the second random number generated by the update unit;
A control unit that controls the update unit to update the generated random number when the second data sequence restored by the restoration unit is a predetermined data sequence;
A data transfer device comprising: The receiving unit receives a plurality of transmission data sequences including the second transmission data sequence from the data transmission device in each of a plurality of periods including the second period,
The restoration unit restores a plurality of data strings including the second data string from the plurality of transmission data strings by descrambling the plurality of transmission data strings;
The controller is
A first detection unit for detecting the predetermined data sequence from the plurality of data sequences restored by the restoration unit;
The first detection unit counts the number of times that the predetermined data string is detected, and when the number of times that the predetermined data string is detected reaches the first predetermined number, a control signal that instructs to update the generated random number A determination unit for outputting to the update unit;
The data transfer apparatus according to claim 1, further comprising: The control unit further includes a second detection unit that detects a data sequence different from the predetermined data sequence from the plurality of data sequences restored by the restoration unit,
The determination unit counts the number of times the second detection unit does not detect the different data sequence after the number of times the predetermined data sequence is detected reaches the first predetermined number of times, and determines the different data sequence. 3. The number of times that the first detection unit detects the predetermined data string is reset by releasing the control signal when the number of times of not detecting reaches a second predetermined number of times. Data transfer device.   The determination unit counts the number of times the second detection unit detects the different data sequence after the number of times the predetermined data sequence is detected reaches the first predetermined number of times, and detects the different data sequence. 4. The data according to claim 2, wherein when the number of times does not reach the third predetermined number of times, the control signal is canceled and the number of times that the first detection unit detects the predetermined data string is reset. Transfer device. A data transfer system comprising a first data transfer device and a second data transfer device,
The first data transfer device includes:
A generating unit that generates a first data string and a second data string;
A first updating unit for updating the first random number to generate a second random number;
By scrambling the first data sequence using the first random number, a first transmission data sequence including the first random number is generated, and by scrambling the second data sequence using the second random number. A randomizing unit for generating a second transmission data sequence including the second random number;
A transmission unit that transmits the first transmission data sequence to the second data transfer device in a first period, and transmits the second transmission data sequence to the second data transfer device in a second period;
The second data transfer device includes:
A receiving unit that receives the first transmission data sequence from the first data transfer device in the first period and receives the second transmission data sequence from the first data transfer device in the second period;
A second updating unit for updating the first random number included in the first transmission data sequence received by the receiving unit and generating the second random number;
A restoration unit for restoring the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the second random number generated by the second update unit;
A control unit that controls the second update unit so as to update the generated random number when the second data sequence restored by the restoration unit is a predetermined data sequence;
A data transfer system characterized by that. A control method of a data transfer system comprising a first data transfer device and a second data transfer device,
The first data transfer device generates a first transmission data sequence including the first random number by scrambling the first data sequence using a first random number,
In the first period, the first data transfer device transmits the first transmission data string to the second data transfer device,
The second data transfer device receives the first transmission data string from the first data transfer device;
The second data transfer device updates the first random number included in the received first transmission data sequence to generate the second random number;
The first data transfer device updates the first random number to generate the second random number;
The first data transfer device generates a second transmission data sequence including the second random number by scrambling the second data sequence using the second random number,
In the second period, the first data transfer device transmits the second transmission data string to the second data transfer device,
The second data transfer device receives the second transmission data string from the first data transfer device;
The second data transfer device restores the second data sequence from the second transmission data sequence by descrambling the second transmission data sequence using the generated second random number,
The second data transfer device updates the generated random number when the restored second data string is a predetermined data string;
A method for controlling a data transfer system.