JP2000269372A - Bga package and its manufacture - Google Patents

Bga package and its manufacture

Info

Publication number
JP2000269372A
JP2000269372A JP6801699A JP6801699A JP2000269372A JP 2000269372 A JP2000269372 A JP 2000269372A JP 6801699 A JP6801699 A JP 6801699A JP 6801699 A JP6801699 A JP 6801699A JP 2000269372 A JP2000269372 A JP 2000269372A
Authority
JP
Japan
Prior art keywords
copper foil
thickness
bga package
wiring pattern
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6801699A
Other languages
Japanese (ja)
Inventor
Hiroshi Takamichi
博 高道
Takeshi Kasai
毅 葛西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal SMI Electronics Device Inc
Original Assignee
Sumitomo Metal SMI Electronics Device Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal SMI Electronics Device Inc filed Critical Sumitomo Metal SMI Electronics Device Inc
Priority to JP6801699A priority Critical patent/JP2000269372A/en
Publication of JP2000269372A publication Critical patent/JP2000269372A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To realize high density of a wiring pattern and improve adherence between ball pads and a resin board, by specifying the thicknesses of a first conducting layer for forming a wiring pattern and a second conducting layer for forming ball pads, and the surface roughness of the surfaces of the first and second conducting layers. SOLUTION: Copper foils 4, 5 are laminated on both surfaces of a prepreg 1, and a base board 6 is formed by vacuum press. Through holes 2 are formed on the base board 6 and filled with conductive resin 3. After that, the copper foils 4, 5 are etched, a wiring pattern 7 is formed on a chip component mounting surface 1a side, and ball pads 8 are formed on a mother board bonding surface 1b side. A copper foil having a thickness of d1 less than thickness d2 of the copper foil 5 laminated on the mother board bonding surface 1b and/or a copper foil having surface roughness of a sticking surface 4a smaller than that of a sticking surface 5a of the copper foil 5 are used as the copper foil 4 laminated on the chip component mounting surface 1a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はBGAパッケージに
関し、より詳細には主にICチップ搭載用のパッケージ
として用いられ、樹脂基板のチップ部品搭載面に配線パ
ターンを有し、該配線パターンの配置面と反対側のマザ
ーボード接合面に、ボールパッドを有するタイプのBG
Aパッケージ及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA package, and more particularly to a BGA package, which is mainly used as a package for mounting an IC chip. BG with a ball pad on the motherboard bonding surface opposite to
A package and a method of manufacturing the A package.

【0002】[0002]

【従来の技術】半導体装置における高密度化、高速化の
要請を受けて多端子化が可能なBGA(Ball Grid Arra
y )が最近では注目を集めている。BGAはマイクロプ
ロセッサやASIC等のように多端子化が要求されてい
るICの実装に最適である。
2. Description of the Related Art In response to demands for higher density and higher speed in semiconductor devices, a BGA (Ball Grid Arra) capable of increasing the number of terminals has been developed.
y) has recently attracted attention. The BGA is most suitable for mounting an IC such as a microprocessor or an ASIC which requires multiple terminals.

【0003】最近までは、BGAのなかでも信頼性の点
からセラミック製BGAが注目を浴びていたが、低コス
ト化の点からプラスチックパッケージにその重点が移行
してきている。
Until recently, ceramic BGAs have attracted attention among BGAs from the viewpoint of reliability, but the focus has shifted to plastic packages from the viewpoint of cost reduction.

【0004】プラスチック製BGAには、両面に銅箔を
貼ってパターン形成された導体層を備えたBT(Bismal
eimide Triazine )樹脂やポリイミド樹脂等からなる1
層または多層の高耐熱性樹脂からなる樹脂基板が用いら
れており、該樹脂基板に放熱性を高めるためのヒートス
ラグが接合されたキャビティダウンタイプや、あるいは
前記ヒートスラグが接合されておらず、外部接続端子の
配置面と反対側の面にチップ部品が搭載される構成のキ
ャビティアップタイプ等がある。
[0004] A plastic BGA has a BT (Bismal) having a conductor layer formed by patterning copper foil on both sides.
eimide Triazine) 1 consisting of resin, polyimide resin, etc.
A resin substrate made of a layer or a multi-layered high heat-resistant resin is used, and a cavity down type in which a heat slug is joined to the resin substrate to enhance heat dissipation, or the heat slug is not joined, There is a cavity-up type or the like in which a chip component is mounted on a surface opposite to a surface on which external connection terminals are arranged.

【0005】該キャビティアップタイプのBGAの一例
を図10(a)に示す。樹脂基板22のICチップ21
搭載面(チップ部品搭載面30)には配線パターン23
が形成され、配線パターン23の配置面と反対側のマザ
ーボード接合面31にはボールパッド24が多数形成さ
れ、これらボールパッド24と配線パターン23とは配
線用のスルーホール26を介して接続され、またICチ
ップ21の下面は放熱用のスルーホール27を介してボ
ールパッド24に接続され、これらボールパッド24上
にはハンダボール25が溶着されている。配線パターン
23はボンディング用パッド23a、ボンディングワイ
ヤ28を介してICチップ21上に形成されたパッド
(図示せず)に接続されている。そしてICチップ2
1、ボンディングワイヤ28、配線パターン23の大部
分を含む部分はモールド樹脂29により被覆されてい
る。
FIG. 10A shows an example of the cavity-up type BGA. IC chip 21 of resin substrate 22
The wiring pattern 23 is provided on the mounting surface (chip component mounting surface 30).
Are formed on the motherboard bonding surface 31 on the side opposite to the surface on which the wiring patterns 23 are arranged, and a large number of ball pads 24 are formed. These ball pads 24 and the wiring patterns 23 are connected via wiring through holes 26, The lower surface of the IC chip 21 is connected to ball pads 24 via through holes 27 for heat radiation, and solder balls 25 are welded on these ball pads 24. The wiring pattern 23 is connected to pads (not shown) formed on the IC chip 21 via bonding pads 23a and bonding wires 28. And IC chip 2
1, a portion including the bonding wire 28 and most of the wiring pattern 23 is covered with a mold resin 29.

【0006】また、図10(a)に示したBGAの配線
パターン23やボールパッド24は、図10(b)に示
すように樹脂基板22の両主面に貼着された厚さが同じ
であり、樹脂基板22との貼着面の表面粗さが同じであ
る銅箔33、34にエッチング処理等を施すことによっ
て形成される。
The BGA wiring pattern 23 and the ball pad 24 shown in FIG. 10A have the same thickness adhered to both main surfaces of the resin substrate 22 as shown in FIG. 10B. In addition, it is formed by performing an etching process or the like on the copper foils 33 and 34 having the same surface roughness of the bonding surface with the resin substrate 22.

【0007】[0007]

【発明が解決しようとする課題】近年、電子機器の高性
能化や小型化が急速に進展しており、それに伴ってIC
チップも高集積化し、チップ部品搭載面30における配
線パターン23の高密度化の要請が高まってきている。
In recent years, the performance and miniaturization of electronic equipment have been rapidly progressing, and ICs have been
Chips have also become highly integrated, and demands for higher density wiring patterns 23 on chip component mounting surface 30 have been increasing.

【0008】配線パターン23の高密度化は、配線パタ
ーン23を形成するための導体層である銅箔33の厚さ
や、銅箔33の樹脂基板22との貼着面の表面粗さに大
きく関連しており、前記厚さを薄くするに従って、また
前記表面粗さを小さくするに従って、配線パターン23
の高密度化を図ることができる。
The increase in the density of the wiring pattern 23 is largely related to the thickness of the copper foil 33 which is a conductor layer for forming the wiring pattern 23 and the surface roughness of the surface of the copper foil 33 to be bonded to the resin substrate 22. As the thickness is reduced and the surface roughness is reduced, the wiring pattern 23
Density can be increased.

【0009】一方、ボールパッド24を有するマザーボ
ード接合面31側では、ボールパッド24を形成するた
めの導体層である銅箔34と樹脂基板22との密着性が
重視されるので、チップ部品搭載面30側とは逆に、銅
箔34の厚さは厚く、また銅箔34の樹脂基板22との
貼着面の表面粗さは大きい方が良い。このように、チッ
プ部品搭載面30側とマザーボード接合面31側とにお
ける銅箔の厚さや表面粗さの要求は相反している。
On the other hand, on the mother board bonding surface 31 side having the ball pad 24, the adhesion between the copper foil 34, which is a conductor layer for forming the ball pad 24, and the resin substrate 22 is emphasized. Contrary to the 30 side, the thickness of the copper foil 34 is preferably large, and the surface roughness of the surface of the copper foil 34 to be bonded to the resin substrate 22 is preferably large. As described above, the requirements for the thickness and surface roughness of the copper foil on the chip component mounting surface 30 side and the motherboard bonding surface 31 side are contradictory.

【0010】ところが、従来においては、図10(b)
に示したように、チップ部品搭載面30側及びマザーボ
ード接合面31側それぞれに貼着される銅箔33、34
の厚さは同じであり、樹脂基板22との貼着面の表面粗
さも同じであるため、チップ部品搭載面30における配
線パターン23の高密度化、及びマザーボード接合面3
1におけるボールパッド24と樹脂基板22との高密着
性を同時に達成することが難しかった。
However, in the prior art, FIG.
, Copper foils 33 and 34 adhered to the chip component mounting surface 30 side and the motherboard bonding surface 31 side, respectively.
Are the same, and the surface roughness of the bonding surface with the resin substrate 22 is the same. Therefore, the density of the wiring patterns 23 on the chip component mounting surface 30 is increased, and the motherboard bonding surface 3
1, it was difficult to simultaneously achieve high adhesion between the ball pad 24 and the resin substrate 22.

【0011】本発明は上記課題に鑑みなされたものであ
って、チップ部品搭載面における配線パターンの高密度
化、及びマザーボード接合面におけるボールパッドと樹
脂基板との密着性の向上を同時に図ることのできるBG
Aパッケージを提供することを目的としている。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and aims at simultaneously increasing the density of a wiring pattern on a chip component mounting surface and improving the adhesion between a ball pad and a resin substrate on a mother board joint surface. BG that can be
A package is intended to be provided.

【0012】[0012]

【課題を解決するための手段及びその効果】上記目的を
達成するために本発明に係るBGAパッケージ(1)
は、樹脂基板のチップ部品搭載面に配線パターンを有
し、該配線パターンの配置面と反対側のマザーボード接
合面に、ボールパッドを有するBGAパッケージにおい
て、前記配線パターンを形成するための第1の導体層の
厚さが、前記ボールパッドを形成するための第2の導体
層の厚さよりも薄いもの、及び/又は前記第1の導体層
における前記樹脂基板との貼着面の表面粗さが、前記第
2の導体層における前記樹脂基板との貼着面の表面粗さ
よりも小さいものであることを特徴としている。
Means for Solving the Problems and Their Effects To achieve the above object, a BGA package according to the present invention (1)
A first pattern for forming the wiring pattern in a BGA package having a wiring pattern on a chip component mounting surface of a resin substrate and a ball pad on a motherboard bonding surface opposite to the wiring pattern placement surface; The thickness of the conductor layer is smaller than the thickness of the second conductor layer for forming the ball pad, and / or the surface roughness of the surface of the first conductor layer to be adhered to the resin substrate is reduced. The surface roughness of the second conductor layer is smaller than the surface roughness of the surface to be adhered to the resin substrate.

【0013】上記BGAパッケージ(1)によれば、前
記第1の導体層の厚さと前記第2の導体層の厚さ、及び
/又は前記第1の導体層の表面粗さと前記第2の導体層
の表面粗さが、前記チップ部品搭載面側、前記マザーボ
ード接合面側それぞれに適したものになっており、前記
配線パターンの高密度化、及び前記ボールパッドと前記
樹脂基板との密着性の向上を同時に図ることができる。
According to the BGA package (1), the thickness of the first conductor layer and the thickness of the second conductor layer, and / or the surface roughness of the first conductor layer and the second conductor The surface roughness of the layer is suitable for each of the chip component mounting surface side and the motherboard bonding surface side, and the density of the wiring pattern is increased, and the adhesion between the ball pad and the resin substrate is improved. Improvement can be achieved at the same time.

【0014】また、本発明に係るBGAパッケージ
(2)は、上記BGAパッケージ(1)において、前記
第1の導体層の厚さが、5〜18μmの範囲内にあるこ
とを特徴としている。
The BGA package (2) according to the present invention is characterized in that, in the BGA package (1), the thickness of the first conductor layer is in the range of 5 to 18 μm.

【0015】上記BGAパッケージ(2)によれば、前
記配線パターンを形成するための前記第1の導体層の厚
さが、5〜18μmの範囲内にあり、より一層の前記配
線パターンの高密度化を図るのに適した厚さとなってい
る。
According to the BGA package (2), the thickness of the first conductor layer for forming the wiring pattern is in the range of 5 to 18 μm, and the density of the wiring pattern is further increased. The thickness is suitable for realizing.

【0016】また、本発明に係るBGAパッケージ
(3)は、上記BGAパッケージ(1)又は(2)にお
いて、前記第1の導体層における前記樹脂基板との貼着
面の表面粗さ(RZ )が、2.5〜5.0μmの範囲内
にあることを特徴としている。
In the BGA package (3) according to the present invention, in the BGA package (1) or (2), the surface roughness (R Z) of the surface of the first conductor layer to be adhered to the resin substrate is provided. ) Is in the range of 2.5 to 5.0 μm.

【0017】上記BGAパッケージ(3)によれば、前
記配線パターンを形成するための前記第1の導体層の前
記表面粗さ(RZ )が、2.5〜5.0μmの範囲内に
あり、より一層の前記配線パターンの高密度化を図るこ
とができる。
According to the BGA package (3), the surface roughness (R Z ) of the first conductor layer for forming the wiring pattern is in the range of 2.5 to 5.0 μm. The density of the wiring pattern can be further increased.

【0018】また、本発明に係るBGAパッケージ
(4)は、上記BGAパッケージ(1)〜(3)のいず
れかにおいて、前記第2の導体層の厚さが、12〜35
μmの範囲内にあることを特徴としている。
Further, in the BGA package (4) according to the present invention, in any one of the BGA packages (1) to (3), the thickness of the second conductor layer is 12 to 35.
It is characterized by being within the range of μm.

【0019】上記BGAパッケージ(4)によれば、前
記ボールパッドを形成するための前記第2の導体層の厚
さが、12〜35μmの範囲内にあり、より一層前記第
2の導体層と前記樹脂基板との密着性の向上を図るのに
適した厚さとなっている。
According to the BGA package (4), the thickness of the second conductor layer for forming the ball pad is in the range of 12 to 35 μm, and the thickness of the second conductor layer is further increased. The thickness is suitable for improving the adhesion to the resin substrate.

【0020】また、本発明に係るBGAパッケージ
(5)は、上記BGAパッケージ(1)〜(4)のいず
れかにおいて、前記第2の導体層における前記樹脂基板
との貼着面の表面粗さ(RZ )が、5.0〜10.0μ
mの範囲内にあることを特徴としている。
In the BGA package (5) according to the present invention, in any one of the BGA packages (1) to (4), the surface roughness of the bonding surface of the second conductor layer to the resin substrate is provided. (R Z ) is 5.0 to 10.0 μm
m.

【0021】上記BGAパッケージ(5)によれば、前
記ボールパッドを形成するための前記第2の導体層の前
記表面粗さ(RZ )が、5.0〜10.0μmの範囲内
にあり、より一層の前記樹脂基板との密着性の向上を図
ることができる。
According to the BGA package (5), the surface roughness (R Z ) of the second conductor layer for forming the ball pad is in the range of 5.0 to 10.0 μm. Thus, the adhesion to the resin substrate can be further improved.

【0022】また、本発明に係るBGAパッケージの製
造方法(1)は、樹脂基板のチップ部品搭載面に配線パ
ターンを形成するための第1の銅箔を貼着する工程と、
前記配線パターンの配置面と反対側のマザーボード接合
面に、ボールパッドを形成するための第2の銅箔を貼着
する工程とを含むBGAパッケージの製造方法におい
て、これら工程前に、前記第1の銅箔の厚さが、前記第
2の銅箔の厚さよりも薄くなるように、及び/又は前記
第1の銅箔における前記樹脂基板との貼着面の表面粗さ
が、前記第2の銅箔における前記樹脂基板との貼着面の
表面粗さよりも細かくなるように、前記第1の銅箔及び
/又は前記第2の銅箔に厚さ調整加工及び/又は表面処
理加工を施す工程を含んでいることを特徴としている。
Further, the method (1) for manufacturing a BGA package according to the present invention comprises the steps of: adhering a first copper foil for forming a wiring pattern on a chip component mounting surface of a resin substrate;
Adhering a second copper foil for forming a ball pad to the motherboard bonding surface opposite to the wiring pattern arrangement surface, wherein the step of attaching the second copper foil forms a ball pad. The thickness of the copper foil is smaller than the thickness of the second copper foil, and / or the surface roughness of the bonding surface of the first copper foil with the resin substrate is the second copper foil. The first copper foil and / or the second copper foil are subjected to a thickness adjustment process and / or a surface treatment process so as to be finer than the surface roughness of the bonding surface of the copper foil to the resin substrate. It is characterized by including a process.

【0023】上記BGAパッケージの製造方法(1)に
よれば、前記第1の導体層の厚さと前記第2の導体層の
厚さ、及び/又は前記第1の導体層の表面粗さと前記第
2の導体層の表面粗さを、前記チップ部品搭載面側、前
記マザーボード接合面側それぞれに適したものに設定す
ることができ、前記配線パターンの高密度化、及び前記
ボールパッドと前記樹脂基板との密着性の向上を同時に
図ることのできるBGAパッケージを作製することがで
きる。
According to the BGA package manufacturing method (1), the thickness of the first conductor layer and the thickness of the second conductor layer, and / or the surface roughness of the first conductor layer and the second 2, the surface roughness of the conductor layer can be set to a value suitable for each of the chip component mounting surface side and the mother board bonding surface side. A BGA package that can simultaneously improve the adhesion to the BGA can be manufactured.

【0024】[0024]

【発明の実施の形態】以下、本発明に係るBGAパッケ
ージ及びその製造方法を図面に基づいて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a BGA package according to the present invention and a method for manufacturing the same will be described with reference to the drawings.

【0025】図1は、実施の形態(1)に係るBGAパ
ッケージの製造工程の一部を示す模式的断面図であり、
図中1はBTレジンからなるプリプレグを示しており、
プリプレグ1はガラス布等の基材に樹脂を含浸させ、半
硬化させたシート状材料である。
FIG. 1 is a schematic sectional view showing a part of the manufacturing process of the BGA package according to the embodiment (1).
1 in the figure shows a prepreg made of BT resin,
The prepreg 1 is a sheet-like material in which a base material such as a glass cloth is impregnated with a resin and semi-cured.

【0026】まず、プリプレグ1の両主面それぞれに銅
箔4、5を積層し、真空プレスすることによって、ベー
ス基板6を作製する(図1(a)(b))。次に、ベー
ス基板6にスルーホール2を形成する。一般にはドリル
が使用されるが、材料によってはレーザービームで加工
することも可能である。スルーホール2形成後、導電性
樹脂3で穴埋めする(図1(c))。その後、銅箔4、
5をエッチングすることにより、チップ部品搭載面1a
側には配線パターン7を形成し、マザーボード接合面1
b側にはボールパッド8を形成する(図1(d))。
First, copper foils 4 and 5 are laminated on both main surfaces of the prepreg 1 and are vacuum-pressed to produce a base substrate 6 (FIGS. 1A and 1B). Next, the through hole 2 is formed in the base substrate 6. Generally, a drill is used, but it is also possible to process with a laser beam depending on the material. After the through holes 2 are formed, the holes are filled with the conductive resin 3 (FIG. 1C). Then, copper foil 4,
5, the chip component mounting surface 1a is etched.
Wiring pattern 7 is formed on the
The ball pad 8 is formed on the b side (FIG. 1D).

【0027】このとき、チップ部品搭載面1aに積層さ
れる銅箔4としては、その厚さd1が、マザーボード接
合面1bに積層される銅箔5の厚さd2 よりも薄いも
の、及び/又は貼着面4aの表面粗さが、銅箔5の貼着
面5aの表面粗さよりも小さいものを使用する。
At this time, the copper foil 4 laminated on the chip component mounting surface 1a has a thickness d 1 smaller than the thickness d 2 of the copper foil 5 laminated on the motherboard bonding surface 1b; The copper foil 5 has a surface roughness smaller than the surface roughness of the bonding surface 5a.

【0028】また、銅箔4としては、その厚さd1 が3
〜18μmの範囲内にあり、貼着面4aの表面粗さが
2.5〜7.0μmの範囲内にあることが望ましく、よ
り好ましくは、厚さd1 が5〜18μmの範囲内にあ
り、貼着面4aの表面粗さが2.5〜5.0μmの範囲
内にあることである。
The copper foil 4 has a thickness d 1 of 3
1818 μm, the surface roughness of the sticking surface 4 a is desirably in the range of 2.5-7.0 μm, and more preferably, the thickness d 1 is in the range of 5-18 μm. The surface roughness of the sticking surface 4a is in the range of 2.5 to 5.0 μm.

【0029】また、銅箔5としては、その厚さd2 が1
0〜35μmの範囲内にあり、貼着面5aの表面粗さが
5.0〜12.0μmの範囲内にあることが望ましく、
より好ましくは、厚さd2 が12〜35μmの範囲内に
あり、貼着面5aの表面粗さが5.0〜10.0μmの
範囲内にあることである。
The copper foil 5 has a thickness d 2 of 1
It is preferably in the range of 0 to 35 μm, and the surface roughness of the sticking surface 5 a is preferably in the range of 5.0 to 12.0 μm,
More preferably, there thickness d 2 is in the range of 12~35Myuemu, surface roughness of the bonded face 5a is with the scope of 5.0~10.0Myuemu.

【0030】上記実施の形態(1)に係るBGAパッケ
ージによれば、銅箔4の厚さd1 と銅箔5の厚さd2
及び/又は銅箔4の貼着面4aの表面粗さと銅箔5の貼
着面5aの表面粗さが、チップ部品搭載面1a側、マザ
ーボード接合面1b側それぞれに適したものになってお
り、配線パターン7の高密度化、及びボールパッド8と
プリプレグ1との密着性の向上を同時に図ることができ
る。
According to the BGA package according to the embodiment (1), the thickness d 1 of the copper foil 4 and the thickness d 2 of the copper foil 5,
And / or the surface roughness of the bonding surface 4a of the copper foil 4 and the surface roughness of the bonding surface 5a of the copper foil 5 are suitable for the chip component mounting surface 1a and the motherboard bonding surface 1b, respectively. Thus, the density of the wiring pattern 7 can be increased, and the adhesion between the ball pad 8 and the prepreg 1 can be improved at the same time.

【0031】なお、上記実施の形態(1)ではプリプレ
グ1の両主面に銅箔4、5が貼着された2層構造を例に
とって説明したが、別の実施の形態ではプリプレグを2
枚、3枚積層させて3層構造、4層構造とすることもも
ちろん可能である。
In the above embodiment (1), a two-layer structure in which copper foils 4 and 5 are adhered to both main surfaces of prepreg 1 has been described as an example.
Of course, it is also possible to form a three-layer structure or a four-layer structure by stacking three or three sheets.

【0032】図2は、実施の形態(2)に係るBGAパ
ッケージの製造工程の一部を示す模式的断面図であり、
図中9は材料を銅とする導体回路層10が形成された樹
脂製のコア材を示している。コア材9の両主面それぞれ
にプリプレグ11、12を介して、銅箔13、14を積
層し、真空プレスすることによってベース基板15を作
製している。
FIG. 2 is a schematic sectional view showing a part of the manufacturing process of the BGA package according to the embodiment (2).
In the drawing, reference numeral 9 denotes a resin core material on which a conductive circuit layer 10 made of copper is formed. Copper foils 13 and 14 are laminated on both main surfaces of the core material 9 via prepregs 11 and 12, respectively, and are vacuum-pressed to produce a base substrate 15.

【0033】ベース基板15作製後、図1に示したのと
同様にして、銅箔13、14をエッチングすることによ
り、チップ部品搭載面11a側には配線パターン16を
形成し、マザーボード接合面12a側にはボールパッド
17を形成する。
After the base substrate 15 is formed, the copper foils 13 and 14 are etched in the same manner as shown in FIG. 1 to form a wiring pattern 16 on the chip component mounting surface 11a side, and the mother board bonding surface 12a A ball pad 17 is formed on the side.

【0034】このとき、チップ部品搭載面11aに積層
される銅箔13としては、その厚さd3 が、マザーボー
ド接合面12aに積層される銅箔14の厚さd4 よりも
薄いもの、及び/又は貼着面13aの表面粗さが、銅箔
14の貼着面14aの表面粗さよりも細かいものを使用
する。
At this time, the copper foil 13 laminated on the chip component mounting surface 11a has a thickness d 3 smaller than the thickness d 4 of the copper foil 14 laminated on the motherboard bonding surface 12a, and The surface roughness of the bonding surface 13a is smaller than the surface roughness of the bonding surface 14a of the copper foil 14.

【0035】また、厚さd3 、貼着面13aの表面粗
さ、厚さd4 、及び貼着面14aの表面粗さの望ましい
範囲は、上記実施の形態(1)で示した範囲と同じであ
る。
Desirable ranges of the thickness d 3 , the surface roughness of the sticking surface 13a, the thickness d 4 , and the surface roughness of the sticking surface 14a are the same as the ranges described in the above embodiment (1). Is the same.

【0036】チップ部品搭載面1a側、マザーボード接
合面1b側それぞれに応じた銅箔13、14の作製方法
について説明する。
The method of producing the copper foils 13 and 14 corresponding to the chip component mounting surface 1a and the motherboard bonding surface 1b will be described.

【0037】厚さd3 が薄く、貼着面13aの表面粗さ
が細かい銅箔13は、電解銅めっきによって、粒状の結
晶構造になるように析出させた原箔に対し、細かい粒子
を球付けすることによって作製される。従って、球付け
の大きさの表面粗さしかない。
The copper foil 13 having a small thickness d 3 and a small surface roughness of the sticking surface 13a is obtained by adding fine particles to the original foil deposited by electrolytic copper plating so as to have a granular crystal structure. It is produced by attaching. Therefore, there is only a surface roughness of the size of a ball.

【0038】図3は、上記作製方法によって作製された
銅箔の表面を光学顕微鏡で観察した顕微鏡写真であり、
極微細な粗化粒子が均一に形成されており、表面粗さR
Z は2.5μmである。なお、図3(a)は1600倍
であり、図3(b)は3200倍である。また、図4は
銅箔の表面構造を示す模式的断面図である。
FIG. 3 is a photomicrograph of the surface of the copper foil produced by the above-described production method, which was observed with an optical microscope.
Ultra-fine roughened particles are uniformly formed, and the surface roughness R
Z is 2.5 μm. 3A is 1600 times, and FIG. 3B is 3200 times. FIG. 4 is a schematic sectional view showing the surface structure of the copper foil.

【0039】厚さd4 が厚く、貼着面14aの表面粗さ
が大きい銅箔14は、電解銅めっきによって、柱状の結
晶構造になるように析出させた原箔に対し、細かい粒子
を球付けすることによって作製される。従って、厚さd
4 が厚ければ厚い程、表面粗さは大きくなる。
The copper foil 14 having a large thickness d 4 and a large surface roughness of the sticking surface 14 a is obtained by depositing fine particles on the original foil deposited by electrolytic copper plating so as to have a columnar crystal structure. It is produced by attaching. Therefore, the thickness d
The thicker 4 is, the greater the surface roughness.

【0040】図5は、上記作製方法によって作製された
銅箔の表面を光学顕微鏡で観察した顕微鏡写真であり、
粗化粒子が素地山の頂に形成されており、表面粗さRZ
は5.1μmである。なお、図5(a)は1600倍で
あり、図5(b)は3200倍である。また、図6は銅
箔の表面構造を示す模式的断面図である。
FIG. 5 is a photomicrograph of the surface of the copper foil produced by the above-described production method, which was observed with an optical microscope.
Roughened particles are formed on the top of the base mountain, and the surface roughness R Z
Is 5.1 μm. Note that FIG. 5A is 1600 times and FIG. 5B is 3200 times. FIG. 6 is a schematic sectional view showing the surface structure of the copper foil.

【0041】[0041]

【実施例及び比較例】図2に示した方法により、図7に
示した4層構造のBGAを作製した。具体的製造条件を
下記に示す。
EXAMPLES and COMPARATIVE EXAMPLES The four-layered BGA shown in FIG. 7 was produced by the method shown in FIG. Specific manufacturing conditions are shown below.

【0042】 プリプレグ11、12の大きさ: 200mm×300mm×厚さ0.2mm プリプレグ11、12の材料:BTレジン 配線パターン16を形成するための銅箔13の厚さ: 9μm 銅箔13の貼着面13aの表面粗さRZ : 2.5μm ボールパッド17を形成するための銅箔14の厚さ: 12μm 銅箔14の貼着面14aの表面粗さRZ : 6.3μm ハンダボール18の径: 0.76mm 銅箔13、14を真空プレスするときの条件 温度: 190℃、2時間 圧力: 25kg/cm2 真空引き: 100torr以下50分 チップ部品搭載面11aに圧着された銅箔13に、導体
幅/間隔が100/100μm、70/70μm、50
/50μmの3種のパターニングをテストフィルムを用
いて行なった。その結果、50/50μmの細かいパタ
ーンまで形成することができた。
Size of prepregs 11 and 12: 200 mm × 300 mm × thickness 0.2 mm Material of prepregs 11 and 12: BT resin Thickness of copper foil 13 for forming wiring pattern 16: 9 μm Pasting copper foil 13 Surface roughness R Z of the attaching surface 13a: 2.5 μm Thickness of the copper foil 14 for forming the ball pad 17: 12 μm Surface roughness R Z of the attaching surface 14a of the copper foil 14: 6.3 μm Solder ball 18 Diameter of 0.76 mm Conditions when vacuum pressing copper foils 13 and 14 Temperature: 190 ° C., 2 hours Pressure: 25 kg / cm 2 Vacuum evacuation: 100 torr or less 50 minutes Copper foil 13 bonded to chip component mounting surface 11a The conductor width / interval is 100/100 μm, 70/70 μm, 50
Three types of / 50 μm patterning were performed using a test film. As a result, a fine pattern of 50/50 μm could be formed.

【0043】ボールパッド17上に溶着されたハンダボ
ール18を図8に示すように、矢印T方向へ引っ張るこ
とによって、ボールパッド17と樹脂基板(プリプレ
グ)12との密着性を調べた。その結果、平均強度が
1.5kgのときにハンダボール18がボールパッド1
7から剥れた。
The adhesion between the ball pad 17 and the resin substrate (prepreg) 12 was examined by pulling the solder ball 18 welded on the ball pad 17 in the direction of arrow T as shown in FIG. As a result, when the average strength is 1.5 kg, the solder ball 18 is
Peeled from 7.

【0044】ボールパッド17と樹脂基板12との密着
性が高い場合には、図9(a)に示すようにハンダボー
ル18だけがボールパッド17から剥れる(いわゆるボ
ール切れが生じる)が、前記密着性が低い場合には、図
9(b)に示すようにボールパッド17が樹脂基板(プ
リプレグ)12から剥れてしまった。
When the adhesion between the ball pad 17 and the resin substrate 12 is high, only the solder ball 18 is peeled off from the ball pad 17 as shown in FIG. When the adhesion was low, the ball pad 17 was separated from the resin substrate (prepreg) 12 as shown in FIG.

【0045】表1に、銅箔13の厚さ、及び貼着面13
aの表面粗さ(RZ )を変えて、前記3種のパターニン
グを行なった時の結果を示す。
Table 1 shows the thickness of the copper foil 13 and the bonding surface 13
The results obtained when the above three types of patterning were performed while changing the surface roughness (R Z ) of a.

【0046】[0046]

【表1】 表1から明らかなように、銅箔13の厚さが5〜18μ
mの範囲内であり、銅箔13の貼着面13aの表面粗さ
Z が2.5〜5.0μmの範囲内であるとき、50/
50μmの細かいパターンを形成することができた。
[Table 1] As is clear from Table 1, the thickness of the copper foil 13 is 5 to 18 μm.
m, and the surface roughness R Z of the bonding surface 13a of the copper foil 13 is in the range of 2.5 to 5.0 μm.
A fine pattern of 50 μm could be formed.

【0047】表2に、銅箔14の厚さ、及び貼着面14
aの表面粗さ(RZ )を変えて、密着性を調べた時の結
果を示す。
Table 2 shows the thickness of the copper foil 14 and the bonding surface 14
The results obtained when the adhesion was examined by changing the surface roughness (R Z ) of a.

【0048】[0048]

【表2】 表2から明らかなように、銅箔14の厚さが12〜35
μmの範囲内であり、銅箔14の貼着面14aの表面粗
さ(RZ )が5.0〜10.0μmの範囲内であると
き、密着性が高い。
[Table 2] As is clear from Table 2, the thickness of the copper foil 14 is 12 to 35.
in the range of [mu] m, when the surface roughness of the bonding surface 14a of the copper foil 14 (R Z) is in the range of 5.0~10.0Myuemu, high adhesion.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態(1)に係るBGAパッケ
ージの製造工程の一部を示す模式的断面図である。
FIG. 1 is a schematic cross-sectional view showing a part of a manufacturing process of a BGA package according to Embodiment (1) of the present invention.

【図2】実施の形態(2)に係るBGAパッケージの製
造工程の一部を示す模式的断面図である。
FIG. 2 is a schematic cross-sectional view showing a part of the manufacturing process of the BGA package according to the embodiment (2).

【図3】銅箔の表面を光学顕微鏡で観察した顕微鏡写真
である。
FIG. 3 is a micrograph of the surface of a copper foil observed with an optical microscope.

【図4】銅箔の表面構造を示す模式的断面図である。FIG. 4 is a schematic sectional view showing a surface structure of a copper foil.

【図5】銅箔の表面を光学顕微鏡で観察した顕微鏡写真
である。
FIG. 5 is a micrograph of the surface of a copper foil observed with an optical microscope.

【図6】銅箔の表面構造を示す模式的断面図である。FIG. 6 is a schematic sectional view showing a surface structure of a copper foil.

【図7】図2に示した方法により作製したBGAの一例
を示した模式的断面図である。
FIG. 7 is a schematic cross-sectional view showing an example of a BGA manufactured by the method shown in FIG.

【図8】ボールパッド近傍を拡大して示した模式的断面
図である。
FIG. 8 is an enlarged schematic sectional view showing the vicinity of a ball pad.

【図9】ボールパッド近傍を拡大して示した模式的断面
図である。
FIG. 9 is an enlarged schematic cross-sectional view showing the vicinity of a ball pad.

【図10】従来のキャビティアップタイプのBGAの一
例を示した模式的断面図である。
FIG. 10 is a schematic sectional view showing an example of a conventional cavity-up type BGA.

【符号の説明】[Explanation of symbols]

1、11、12 プリプレグ 1a、11a チップ部品搭載面 1b、12a マザーボード接合面 4、5、13、14 銅箔 7、16 配線パターン 8、17 ボールパッド 1, 11, 12 Pre-preg 1a, 11a Chip component mounting surface 1b, 12a Motherboard joint surface 4, 5, 13, 14 Copper foil 7, 16 Wiring pattern 8, 17 Ball pad

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 樹脂基板のチップ部品搭載面に配線パタ
ーンを有し、該配線パターンの配置面と反対側のマザー
ボード接合面に、ボールパッドを有するBGAパッケー
ジにおいて、 前記配線パターンを形成するための第1の導体層の厚さ
が、前記ボールパッドを形成するための第2の導体層の
厚さよりも薄いもの、及び/又は前記第1の導体層にお
ける前記樹脂基板との貼着面の表面粗さが、前記第2の
導体層における前記樹脂基板との貼着面の表面粗さより
も小さいものであることを特徴とするBGAパッケー
ジ。
1. A BGA package having a wiring pattern on a chip component mounting surface of a resin substrate and having a ball pad on a motherboard bonding surface opposite to a surface on which the wiring pattern is arranged, for forming the wiring pattern. Thickness of the first conductor layer is smaller than thickness of the second conductor layer for forming the ball pad, and / or the surface of the first conductor layer to which the resin substrate is adhered. A BGA package, wherein the roughness is smaller than the surface roughness of the surface of the second conductor layer to be bonded to the resin substrate.
【請求項2】 前記第1の導体層の厚さが、5〜18μ
mの範囲内にあることを特徴とする請求項1記載のBG
Aパッケージ。
2. The method according to claim 1, wherein the thickness of the first conductor layer is 5 to 18 μm.
2. The BG according to claim 1, wherein the BG is within a range of m.
A package.
【請求項3】 前記第1の導体層における前記樹脂基板
との貼着面の表面粗さ(RZ )が、2.5〜5.0μm
の範囲内にあることを特徴とする請求項1又は請求項2
記載のBGAパッケージ。
3. A surface roughness (R Z ) of a surface of the first conductor layer to be adhered to the resin substrate is 2.5 to 5.0 μm.
3. The method according to claim 1, wherein
The BGA package as described.
【請求項4】 前記第2の導体層の厚さが、12〜35
μmの範囲内にあることを特徴とする請求項1〜3のい
ずれかの項に記載のBGAパッケージ。
4. The thickness of the second conductor layer is 12 to 35.
The BGA package according to claim 1, wherein the BGA package is in a range of μm.
【請求項5】 前記第2の導体層における前記樹脂基板
との貼着面の表面粗さ(RZ )が、5.0〜10.0μ
mの範囲内にあることを特徴とする請求項1〜4のいず
れかの項に記載のBGAパッケージ。
5. The surface roughness (R Z ) of the surface of the second conductor layer to be bonded to the resin substrate is 5.0 to 10.0 μm.
The BGA package according to claim 1, wherein the BGA package is within a range of m.
【請求項6】 樹脂基板のチップ部品搭載面に配線パタ
ーンを形成するための第1の銅箔を貼着する工程と、前
記配線パターンの配置面と反対側のマザーボード接合面
に、ボールパッドを形成するための第2の銅箔を貼着す
る工程とを含むBGAパッケージの製造方法において、 これら工程前に、前記第1の銅箔の厚さが、前記第2の
銅箔の厚さよりも薄くなるように、及び/又は前記第1
の銅箔における前記樹脂基板との貼着面の表面粗さが、
前記第2の銅箔における前記樹脂基板との貼着面の表面
粗さよりも細かくなるように、前記第1の銅箔及び/又
は前記第2の銅箔に厚さ調整加工及び/又は表面処理加
工を施す工程を含んでいることを特徴とするBGAパッ
ケージの製造方法。
6. A step of adhering a first copper foil for forming a wiring pattern on a chip component mounting surface of a resin substrate, and a step of attaching a ball pad to a motherboard bonding surface opposite to the wiring pattern placement surface. A step of attaching a second copper foil for forming the BGA package, the thickness of the first copper foil being greater than the thickness of the second copper foil before these steps. Thin and / or the first
The surface roughness of the bonding surface of the copper foil with the resin substrate,
Thickness adjustment processing and / or surface treatment on the first copper foil and / or the second copper foil so as to be smaller than the surface roughness of the bonding surface of the second copper foil with the resin substrate. A method for manufacturing a BGA package, comprising a step of performing processing.
JP6801699A 1999-03-15 1999-03-15 Bga package and its manufacture Pending JP2000269372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6801699A JP2000269372A (en) 1999-03-15 1999-03-15 Bga package and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6801699A JP2000269372A (en) 1999-03-15 1999-03-15 Bga package and its manufacture

Publications (1)

Publication Number Publication Date
JP2000269372A true JP2000269372A (en) 2000-09-29

Family

ID=13361622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6801699A Pending JP2000269372A (en) 1999-03-15 1999-03-15 Bga package and its manufacture

Country Status (1)

Country Link
JP (1) JP2000269372A (en)

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