JP2000269355A - Cmos semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS semiconductor device together with its manufacturing method wherein the transistor characteristics for each of P and N channel MOS transistors, where nitrogen is introduced in a gate insulating film, is improved. SOLUTION: The CMOS semiconductor device comprises P and N channel MOS transistors wherein nitrogen is introduced in a gate insulating film, with the gate insulating film and gate electrode formed on a silicon substrate. Here, the concentration peak of the nitrogen introduced in the gate insulating film is not present at the interface between a gate insulating film 17 and silicon substrate 11 for the P channel MOS transistor (the concentration peak of nitrogen is deviated toward a gate electrode side from the interface to the silicon substrate), while it is at the interface between a gate insulating film 19 and the silicon substrate 11 for N channel MOS transistor. The mutual conductances of the P and N channel MOS transistors are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS semiconductor device in which a P-channel MOS transistor and an N-channel MOS transistor coexist, and more particularly to a CMOS semiconductor device in which the reliability of both MOS transistors is improved and characteristic deterioration is prevented, and a method of manufacturing the same. .

[0002]

2. Description of the Related Art In response to recent demands for lower voltage and lower power consumption of semiconductor devices, a technique has been proposed in which a gate insulating film of a MOS transistor is made thinner and impurities are introduced into polycrystalline silicon serving as a gate. Have been.
However, according to the description of Japanese Patent Application Laid-Open No. 10-209449, as the thickness of the gate insulating film is reduced, the insulation of the gate insulating film is deteriorated due to the occurrence of traps due to the increase in the FN tunnel current. In addition, impurities such as boron having a large diffusion coefficient introduced into the polycrystalline silicon penetrate the gate oxide film and penetrate into the channel region of the silicon substrate, thereby changing the threshold voltage of the MOS transistor or reducing the reliability of the gate oxide film. The problem that the property is deteriorated arises. Therefore, by introducing nitrogen into the gate insulating film, it is effective to suppress the above-described traps and improve the insulating property of the gate insulating film, and to suppress the diffusion of boron into the silicon substrate by the introduced nitrogen. It is supposed to be. In the technique disclosed in the above publication, the nitrogen concentration peak in the gate insulating film is located at the interface between the gate insulating film and the silicon substrate, so that both the improvement of the insulating property and the suppression of the diffusion of boron are achieved. It has been suggested that it can be satisfied.

However, when the concentration peak of nitrogen in the gate oxide film is set at the interface between the gate oxide film and the silicon substrate as in this technique, the nitrogen also penetrates into the silicon substrate and reduces the conductance of the P-channel MOS transistor. It becomes a factor of deterioration. Such a problem is taken up in Japanese Patent Application Laid-Open No. Hei 10-242461. In the technique described in this second publication, the nitrogen concentration peak in the gate oxide film is shifted from the interface with the silicon substrate to the gate electrode side. A technique has been proposed which prevents nitrogen from penetrating into a silicon substrate by suppressing the deterioration of the conductance of a P-channel MOS transistor. That is, according to the technique disclosed in the second publication, a silicon film is formed on a first gate oxide film obtained by oxidizing a silicon substrate, then the silicon film is nitrided, and the silicon oxide film is oxidized. This is a technique for forming two gate oxide films in a stacked state. According to this technique, nitrogen has a concentration peak at a position on the gate electrode side from the interface between the second gate oxide film and the first gate oxide film obtained by oxidizing the silicon film, that is, the interface between the gate insulating film and the silicon substrate. Therefore, it is possible to suppress nitrogen from entering the silicon substrate and suppress deterioration of the conductance of the transistor.

[0004]

However, in the technique described in the second publication, a step of oxidizing a silicon substrate to form a first gate oxide film, a step of forming a silicon film thereon, A step of nitriding the film and a step of oxidizing the silicon oxide film are required, which complicates the step of forming the gate insulating film.
Further, as described in this publication, Si / SiO
_{When a} gate oxynitride film having a distribution of keeping nitrogen away from the _two interfaces was formed, it was confirmed that the characteristics of the N-channel MOS transistor deteriorated in the gate insulating film of the N-channel MOS transistor. In other words, when the gate insulating film becomes very thin, even in an N-channel MOS transistor, when an N ⁺ gate electrode is formed by introducing arsenic or phosphorus as an N-type impurity into the gate electrode, the N-channel MOS transistor becomes similar to the P-channel MOS transistor. Since diffusion of impurities from the gate electrode to the silicon substrate occurs, nitrogen is introduced into the gate insulating film to prevent the diffusion. In this case,
If the nitrogen concentration peak is shifted from the interface between the silicon substrate and the gate insulating film toward the gate electrode side as in the second publication, characteristics such as the conductance of the N-channel MOS transistor will be degraded.

As described above, when the techniques of the first and second publications are applied to a semiconductor device having a CMOS structure, the peak concentration of nitrogen in the gate insulating films of the P-channel MOS transistor and the N-channel MOS transistor is reduced. Because of the lack of position matching, the transistor characteristics of the P-channel MOS transistor can be improved, but the same transistor characteristics of the N-channel MOS transistor cannot be improved.
It is difficult to realize a semiconductor device having a CMOS structure in which the transistor characteristics of each of the S transistor and the N-channel MOS transistor are improved.

An object of the present invention is to provide a CMOS semiconductor device having improved transistor characteristics in each of a P-channel MOS transistor and an N-channel MOS transistor, and a method of manufacturing the same.

[0007]

According to the present invention, there is provided a P-channel MO in which a gate insulating film and a gate electrode are formed on a silicon substrate and nitrogen is introduced into the gate insulating film.
In a CMOS semiconductor device including an S transistor and an N channel MOS transistor, the concentration peak of nitrogen introduced into the gate insulating film is reduced by the P channel MOS transistor.
In the transistor, it does not exist at the interface between the gate insulating film and the silicon substrate, and in the N-channel MOS transistor, it is near the interface between the gate insulating film and the silicon substrate. In particular, the P-channel MO
The gate insulating film of the S transistor has a position where the nitrogen concentration peak is closer to the gate electrode than the interface with the silicon substrate and closer to the gate electrode than the N-channel MOS transistor. It is characterized by.

In a preferred embodiment of the CMOS semiconductor device of the present invention, the gate insulating film of the N-channel MOS transistor has a multilayer structure having a silicon oxide film as an upper layer and a silicon oxynitride film as a lower layer. Also,
The gate insulating film of the P-channel MOS transistor has at least a part thereof an upper silicon oxynitride film;
It is configured as a multilayer structure including a lower silicon oxide film.

The manufacturing method of the present invention is characterized in that the nitrogen concentration peak does not exist at the interface with the silicon substrate in the P-channel MOS transistor formation region and the N-channel MOS transistor formation region defined on the silicon substrate. Forming a gate insulating film, and removing the first gate insulating film in the N-channel MOS transistor forming region by masking the first gate insulating film in the P-channel MOS transistor forming region. Forming a second gate insulating film having a nitrogen concentration peak at the interface with the silicon substrate in the N-channel MOS transistor formation region. Here, the manufacturing order of the first gate insulating film and the second gate insulating layer may be reversed. Further, the first method for manufacturing a gate insulating film includes a step of forming a silicon oxynitride film by oxynitriding the silicon substrate, and a step of oxidizing the silicon substrate to form a layer below the silicon oxynitride film. It is preferable to include a step of forming a silicon oxide film. The second gate insulating film may include a step of oxidizing the silicon substrate to form a silicon oxide film, and a step of oxynitriding the silicon substrate to form a silicon oxynitride film under the silicon oxide film. It is preferable to include a forming step.

In the CMOS semiconductor device of the present invention, the gate insulating film of the P-channel MOS transistor has a structure in which the concentration peak of nitrogen is closer to the gate electrode than the interface with the silicon substrate, and the gate insulating film of the N-channel MOS transistor is formed. In this case, the nitrogen concentration peak is located near the interface with the silicon substrate, so that the P-channel MOS
It is possible to simultaneously improve the transistor characteristics of the transistor and the N-channel MOS transistor. That is, according to the study of the present inventors, the nitrogen atoms in the gate insulating film terminate the dangling bonds of silicon existing near the interface between the gate insulating film and the silicon substrate, and the connection between the gate insulating film and the silicon substrate. It suppresses carrier scattering due to interface states, and improves the transconductance of an N-channel MOS transistor. On the other hand, in a P-channel MOS transistor, when nitrogen atoms are present at or near the interface between the gate insulating film and the silicon substrate, the scattering of carriers becomes conspicuous due to the electric field generated by the nitrogen atoms, and the mutual conductance is deteriorated. . Therefore, in a P-channel MOS transistor, it is preferable to bias the nitrogen concentration peak toward the gate electrode side up to a region where the electric field due to nitrogen atoms does not affect the channel region of the silicon substrate.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. 1 to 4 are sectional views showing an embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, an N-type impurity and a P-type impurity are selectively introduced into a P-type silicon substrate 11 to form an N-well 12 and a P-well 13. Further, an element isolation insulating film 14 is formed by a LOCOS method for selectively oxidizing the surface of the silicon substrate 11, a P-channel MOS transistor formation region 15 is formed in the N well 12 region, and a P channel MOS transistor formation region 15 is formed in the P well 13 region. An N-channel MOS transistor formation region 16 is defined. Next, as shown in FIG. 1B, after the surface of the silicon substrate 11 is cleaned with dilute hydrofluoric acid diluted 1: 100, the silicon substrate 11 is heated in a NO gas (monoxide gas) atmosphere at 700 ° C., 10 Torr and 10 sec. NO annealing and 10
As described later in detail, a silicon oxynitride film and a silicon oxide film are formed on the surface of the silicon substrate 11 in each of the transistor formation regions by dry oxidation in an O ₂ gas (oxygen gas) atmosphere at 00 ° C., 100 Torr, and 100 seconds. A 25 ° gate insulating film 17 having a laminated structure is formed.
This gate insulating film 17 is configured as it is as a gate insulating film of the P-channel MOS transistor.

Next, as shown in FIG.
A polycrystalline silicon film 18 is formed to a thickness of 50 to 200 ° by a CVD method at 0 ° C. and 0.5 Torr. Although not shown, a photoresist is applied on the polycrystalline silicon film 18, exposed, developed and patterned, and then the polycrystalline silicon film 18 is selectively etched and removed using the photoresist. As shown in FIG. 1D, the P-channel MOS transistor forming region 15 is covered and the N-channel MOS transistor forming region 16 is covered.
Is formed as an exposed mask.

Subsequently, as shown in FIG. 2A, using the mask of the polycrystalline silicon film, the N 2
The gate insulating film 17 in the channel MOS transistor formation region is removed by etching. Next, as shown in FIG. 2B, the exposed surface of the silicon substrate 11 in the N-channel MOS transistor formation region 16 is exposed to a temperature of 1000 ° C.
Dry oxidation at 50 Torr and 100 sec is performed, followed by NO annealing at 1000 ° C. and 50 Torr and 150 sec to form a 25 ° gate insulating film 19 having a laminated structure of a silicon oxide film and a silicon oxynitride film as described in detail later. I do. This gate insulating film 19 is configured as a gate insulating film of an N-channel MOS transistor.

Thereafter, as shown in FIG. 2 (c), the polycrystalline silicon film 18 is removed,
the polycrystalline silicon film 20 at 1000
To a film thickness of Next, the polycrystalline silicon film 20
After a photoresist (not shown) is applied on the upper surface and exposed and developed for patterning, the polysilicon film 20 is etched using the photoresist as a mask,
The gate electrodes 21 and 22 of the channel and N-channel MOS transistors are formed. Thereafter, since the process is the same as the well-known technology, detailed description is omitted, but one of the P-channel MOS transistor formation region and the N-channel MOS transistor formation region is masked, and the other is a P-type impurity. N-type impurities are ion-implanted, and the source / drain regions 23 and 24 of each transistor are implanted.
To form At the same time as this step, impurities are introduced into the gate electrodes 21 and 22 of each MOS transistor. As a result, as shown in FIG.
S transistor 25 and N channel MOS transistor 2
6 is manufactured.

Here, in the step shown in FIG. 1B, that is, in the step of forming the gate insulating film 17 of the P-channel MOS transistor, first, as shown in FIG. 3A, a natural oxide film is formed by dilute hydrofluoric acid. Silicon substrate 1 removed and cleaned
A silicon oxide film containing nitrogen by NO annealing in a NO gas atmosphere, that is, a silicon oxynitride film 1
71 are formed. At this time, the silicon oxynitride film 171
As can be seen from the figure, the nitrogen concentration peak at the interface between the silicon oxynitride film 171 and the silicon substrate 11. Next, as shown in FIG. 3B, the surface of the silicon substrate 11 in contact with the silicon oxynitride film 171 is oxidized by dry oxidation in an O ₂ gas atmosphere to form a silicon oxide film 172. At this time, the formed silicon oxide film 172 is oxidized while containing the nitrogen introduced into the silicon substrate 11 at the time of the formation of the silicon oxynitride film 171, and contains the corresponding nitrogen. As a result, the formed gate insulating film 17 has a two-layer structure of the upper silicon oxynitride film 171 and the lower silicon oxide film 172. In addition, the nitrogen concentration in the gate insulating film 17 is such that the nitrogen concentration distribution when the silicon oxynitride film 171 is formed is raised as it is, and as shown in FIG. It is located at the interface between silicon oxynitride film 171 and silicon oxide film 172. As a result, the nitrogen concentration peak shifts toward the upper layer side from the interface between the gate insulating film 17 and the silicon substrate 11, in other words, toward the gate electrode 21 side of the finally formed P-channel MOS transistor. Becomes

On the other hand, in the step shown in FIG. 2B, that is, in the step of forming the gate insulating film 19 of the N-channel MOS transistor, first, as shown in FIG. A nitrogen-free silicon oxide film 191 is formed on the removed and cleaned surface of the silicon substrate 11 by dry oxidation in an O ₂ gas atmosphere. Next, as shown in FIG. 4B, when nitrogen is introduced into the silicon oxide film 191 by NO annealing in an NO gas atmosphere, the surface of the silicon substrate 11 that is in contact with the silicon oxide film 191 is changed. Oxynitridation forms silicon oxynitride film 192. At this time, the formed silicon oxynitride film 192 has a nitrogen concentration distribution having a nitrogen concentration peak at or near the interface with the silicon substrate 11. As a result, the formed gate insulating film 19 is formed.
Has a two-layer structure of an upper silicon oxide film 191 and a lower silicon oxynitride film 192. Therefore, the formed gate insulating film 19 has a nitrogen concentration peak due to the nitrogen concentration distribution in the silicon oxynitride film 192.
The distribution shown in the figure is located near the interface between the gate insulating film 19 and the silicon substrate 11.

As described above, in the process of forming the gate insulating films 17 and 19 of the P-channel MOS transistor 25 and the N-channel MOS transistor 26, NO annealing with NO gas and dry oxidation with O ₂ gas are performed, respectively. In the P-channel MOS transistor 25, a gate insulating film having a nitrogen concentration peak on the side of the gate electrode in the gate insulating film 17 is formed only by reversing the order of these processing steps while performing the same processing steps. With the N-channel MOS transistor 26, a gate insulating film having a nitrogen concentration peak near the interface between the gate insulating film 19 and the silicon substrate 11 can be formed.

CMOS manufactured by the above manufacturing method
P-channel MOS transistor and N in semiconductor device
In order to measure each transistor characteristic of the channel MOS transistor, here, the transconductance (Gm),
As a comparative example, the gate insulating film 1 of each MOS transistor
A CMOS transistor in which the structures of Nos. 7 and 19 were completely reversed from the structure of the above embodiment was prepared. That is, FIG.
The mask of the polycrystalline silicon film 18 formed in the step (d) is formed in the N-channel MOS transistor forming region 16, and the subsequent steps are formed so as to be performed in the P-channel MOS transistor forming step. According to this manufacturing method, in a P-channel MOS transistor, a gate insulating film in which the nitrogen concentration peak in the gate insulating film is located near the interface between the gate insulating film and the silicon substrate is formed. In an N-channel MOS transistor, the gate insulating film is formed. It is possible to form a gate insulating film in which the concentration peak of nitrogen in the inside is shifted toward the gate electrode. Here, the concentration of the nitrogen concentration peak in each gate insulating film in each of the MOS transistors of the embodiment and the comparative example was set to 0.5 to 5%. The gate electrode has a gate length of 1
μm and the gate width is 10 μm.

FIGS. 5A and 5B show the results of comparing the mutual conductance of each MOS transistor of the CMOS semiconductor device of the embodiment and each MOS transistor of the CMOS semiconductor device of the comparative example. In these figures, the horizontal axis represents the gate voltage of each transistor. However, in order to correct the difference in the threshold voltage of each transistor, the horizontal axis represents the threshold voltage Vg from the gate voltage Vg.
This shows a voltage obtained by subtracting t. The vertical axis represents the transconductance Gm. In order to correct the value of the transconductance due to the difference in the thickness of the gate insulating film of each transistor, the transconductance Gm has the film thickness Tox.
Is multiplied by. In each figure, a black circle indicates the gate insulating film 19 in which the nitrogen concentration peak in the gate insulating film is located at the interface between the gate insulating film and the silicon substrate, and a white circle indicates the nitrogen concentration peak in the gate insulating film. The gate insulating film 17 deviated toward the gate electrode is shown.

In this measurement result, FIG.
This is a comparison result of the channel MOS transistors. In a region where the gate voltage is equal to or higher than a predetermined voltage, the gate insulating film 1 indicated by a white circle
7, the transconductance is improved as compared with the gate insulating film 19 of the black circle. That is, the P peak of the present embodiment in which the nitrogen concentration peak is closer to the gate electrode side in the gate insulating film than in the comparative example where the nitrogen concentration peak is located at the interface between the gate insulating film and the silicon substrate. Channel MOS
It can be seen that the transconductance of the transistor has been improved. On the other hand, FIG. 5B shows a comparison result of an N-channel MOS transistor, and in a region where the gate voltage is equal to or higher than a predetermined voltage, contrary to the P-channel MOS transistor.
The transconductance of the black circle gate insulating film 19 is better than that of the white circle gate insulating film 17. That is, the N-channel of the present embodiment of the gate insulating film in which the nitrogen concentration peak is located near the interface between the gate insulating film and the silicon substrate is higher than the comparative example in which the nitrogen concentration peak is closer to the gate electrode. It can be seen that the transconductance of the MOS transistor has been improved.

As described above, in the CMOS semiconductor device of the present invention, the gate insulating film 17 of the P-channel MOS transistor 25 has a structure in which the nitrogen concentration peak is closer to the gate electrode side than the interface with the silicon substrate, and the N-channel MO
In the gate insulating film 19 of the S transistor 26, by setting the nitrogen concentration peak near the interface with the silicon substrate, the transistor characteristics of the P-channel MOS transistor 25 and the N-channel MOS transistor 26 can be simultaneously improved. It becomes possible. According to experiments and measurements made by the present inventors, the above-described improvement of the transconductance is particularly remarkable when the thickness of the gate insulating film is in the range of 20 to 40 °. It has been confirmed that it can be obtained. It has also been confirmed that a remarkable improvement can be obtained when the concentration peak of nitrogen in the gate insulating film is in the range of 0.5 to 5%. Accordingly, in order to realize a low voltage and low power consumption of the CMOS semiconductor device, a thin gate insulating film and a configuration in which impurities are introduced into the gate electrode are adopted, and the gate insulating film is insulated by FN tunnel current. In the case where a structure in which nitrogen is introduced into the gate insulating film to improve the operability and suppress the diffusion of the impurity from the gate electrode to the silicon substrate is employed, the P-channel MOS transistor and the N-channel MOS transistor each have Improve transistor characteristics and improve C
It is possible to improve the overall characteristics of the MOS semiconductor device.

Although the gate insulating film 17 of the P-channel MOS transistor 25 has an example of a two-layer structure of an upper silicon oxynitride film 171 and a lower silicon oxide film 172, the silicon oxynitride film 171 has been described. It is also possible to adopt a three-layer structure in which silicon oxide films are formed on the upper layer and the lower layer, respectively. As a step of forming this gate insulating film, first, as shown in FIG. 6A, dry oxidation with O ₂ is performed to form a first silicon oxide film 173 on the surface of the silicon substrate, and then FIG. As shown in b), the first silicon oxide film 173 and the silicon substrate 1
A silicon oxynitride film 171 is formed at the interface with the silicon nitride film 171. Thereafter, as shown in FIG. 6C, dry oxidation using O ₂ is performed again to form a second silicon oxide film 172 under the silicon oxynitride film 171. In the gate insulating film 17A thus formed, when forming a gate insulating film having the same thickness as the gate insulating film 17 of the above-described embodiment,
The thickness of the silicon oxynitride film 171 can be reduced, and the distribution of nitrogen is limited to a narrow region within the thickness of the silicon oxynitride film, so that the distribution of nitrogen to the silicon substrate 11 and the gate electrode side is further reduced. This is advantageous in that the transistor characteristics of the P-channel MOS transistor can be further improved by suppressing it.

In the manufacturing method shown in FIG. 6, the process for forming the first silicon oxide film 173 and the silicon oxynitride film 171 thereunder is performed for forming the gate insulating film 19 of the N-channel MOS transistor. It is also possible to carry out in the same procedure as the process, which is effective in simplifying the control of the process. Therefore, although depending on the relationship with the thickness of the gate insulating film of the N-channel MOS transistor, the process of FIG. 1B is shared by the gate insulating films of the P-channel MOS transistor and the N-channel MOS transistor. And the two-layered first silicon oxide film 173 and silicon oxynitride film 171 on the gate insulating film 17A of the P-channel MOS transistor
If the gate insulating film 19 of the OS transistor has been formed, thereafter, only the second silicon oxide film 172 under the gate insulating film 17A of the P-channel MOS transistor is formed, and the gate insulating films 17A and 19 of each transistor are formed.
Can be manufactured, and the manufacturing process can be shortened.

In the gate insulating film 19 of the N-channel MOS transistor, an upper silicon oxide film 191 is formed.
Although a two-layer structure of the silicon oxynitride film 192 and the lower silicon oxynitride film 192 has been described, a single layer of the silicon oxynitride film 192 may be used.

Further, in the above-described embodiment, first, a gate insulating film of a P-channel MOS transistor is formed in each forming region of a P-channel MOS transistor and an N-channel MOS transistor, and thereafter, a gate insulating film of an N-channel MOS transistor forming region is formed. Is removed, and the gate insulating film of the N-channel MOS transistor is formed again in the N-channel MOS transistor forming region. The gate insulating film of the N-channel MOS transistor is formed first, and then the gate insulating film of the P-channel MOS transistor is formed. A step of forming a film is also possible. In the above embodiment, the gate insulating film of the P-channel MOS transistor formed earlier is removed by etching in the region where the N-channel MOS transistor is formed, and the polycrystalline silicon is used as a mask when the gate insulating film of the N-channel MOS transistor is formed again. Although a silicon film is used, another material can be used as a mask as long as the material has heat resistance and etching resistance in the processing step.

Here, in the present invention, the following processing steps can be adopted in the processing steps of the above embodiment. In the above embodiment, a dry oxidation process using O ₂ gas is used as a process for forming a silicon oxide film, but a wet oxidation (oxidation in an H ₂ O atmosphere) process may be used. However, when the silicon oxide film is formed after the silicon oxynitride film is formed first as in the step of FIG. 1B, nitrogen atoms are separated from the silicon oxynitride film formed earlier in the wet oxidation treatment. Therefore, dry oxidation treatment as in the above embodiment is preferable.
In any case of the dry oxidation treatment and the wet oxidation treatment, the atmosphere is not limited to 100% H ₂ O or O ₂ gas, but may be a mixed gas with an inert gas such as nitrogen or argon. . Alternatively, HCl, Cl ₂ ,
CCl ₄ , C ₂ HCl ₃ , CH ₂ Cl ₂ , C ₂ H ₂ Cl
A compound containing a halogen element such as ₂ , C ₂ H ₃ Cl ₃ may be added.

On the other hand, the processing step for forming the silicon oxynitride film is not limited to NO in the above embodiment,
N ₂ O (nitrous oxide) may be used. However, NO is preferable in that the introduction of nitrogen is easy and the thickness of the gate insulating film is easily reduced. Note that N ₂ O
Is cheaper and safer than NO, and if this is important, N ₂ O can be used. Also in this silicon oxynitriding process, NO and N ₂ O
Or a mixed gas with an inert gas such as nitrogen or argon. Further, in both cases of the silicon oxide film forming process and the silicon oxynitride film forming process, the film forming apparatus can use an infrared lamp heating furnace or a resistance heating furnace.

[0028]

As described above, according to the present invention, in the gate insulating film of the P-channel MOS transistor, the nitrogen concentration peak is closer to the gate electrode side than the interface with the silicon substrate. In the gate insulating film, the transistor characteristic of each of the P-channel MOS transistor and the N-channel MOS transistor can be simultaneously improved by adopting a structure in which the nitrogen concentration peak is located near the interface with the silicon substrate. Accordingly, in order to realize a low voltage and low power consumption of the CMOS semiconductor device, a thin gate insulating film and a configuration in which impurities are introduced into the gate electrode are adopted, and the gate insulating film is insulated by FN tunnel current. In the case where a structure in which nitrogen is introduced into the gate insulating film to improve the operability and suppress the diffusion of the impurity from the gate electrode to the silicon substrate is employed, the P-channel MOS transistor and the N-channel MOS transistor each have It is possible to improve the transistor characteristics and the overall characteristics of the CMOS semiconductor device.

[Brief description of the drawings]

FIG. 1 is a first sectional view showing a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a second sectional view illustrating the manufacturing process of the embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of a gate insulating film of a P-channel MOS transistor and its nitrogen concentration distribution.

FIG. 4 is a diagram showing a manufacturing process of a gate insulating film of an N-channel MOS transistor and its nitrogen concentration distribution.

FIG. 5 shows a P-channel MOS transistor and an N-channel M
FIG. 8 is a diagram comparing the mutual conductance due to the difference in the structure of the gate insulating film of the OS transistor.

FIG. 6 is a diagram showing another manufacturing process of the gate insulating film of the P-channel MOS transistor and its nitrogen concentration distribution.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 N well 13 P well 14 Element isolation insulating film 15 P channel MOS transistor formation region 16 N channel MOS transistor formation region 17, 17A Gate insulating film (P channel MOS transistor) 18 Polycrystalline silicon film 19 Gate insulating film ( N-channel MOS transistor) 20 Polycrystalline silicon film 21, 22 Gate electrode 23, 24 Source / drain region 25 P-channel MOS transistor 26 N-channel MOS transistor 171 Silicon oxide film 172 Silicon oxynitride film 173 Silicon oxide film 191 Silicon oxynitride film 192 Silicon oxide film

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) BF65 BH04 BJ01 BJ10

Claims (11)

[Claims] 1. A CMOS semiconductor device including a P-channel MOS transistor and an N-channel MOS transistor, wherein a gate insulating film and a gate electrode are formed on a silicon substrate, and nitrogen is introduced into the gate insulating film. The concentration peak of nitrogen introduced into the gate insulating film is not present at the interface between the gate insulating film and the silicon substrate in the P-channel MOS transistor, and is not present in the N-channel MOS transistor. A CMOS semiconductor device, which is located near an interface of a silicon substrate. 2. The gate insulating film of the P-channel MOS transistor according to claim 1, wherein the nitrogen concentration peak is located closer to the gate electrode than the interface with the silicon substrate. 12. The CMOS semiconductor device according to claim 1. 3. The method according to claim 1, wherein the nitrogen concentration peak of the gate insulating film of the P-channel MOS transistor is closer to the gate electrode than the nitrogen concentration peak of the gate insulating film of the N-channel MOS transistor. 3. The CMOS semiconductor device according to claim 1, wherein: 4. The gate insulating film of the N-channel MOS transistor has a single layer of a silicon oxynitride film or a multilayer structure having a silicon oxide film as an upper layer and a silicon oxynitride film as a lower layer. Item 4. The CMOS semiconductor device according to any one of Items 1 to 3. 5. The P-channel MOS transistor according to claim 1, wherein said gate insulating film has a multilayer structure including an upper silicon oxynitride film and a lower silicon oxide film in at least a part thereof. 5. The CMOS semiconductor device according to any one of 4. 6. The concentration of the nitrogen concentration peak is from 0.5 to
The CMO according to any one of claims 1 to 5, which is 5%.
S semiconductor device. 7. The gate insulating film has a thickness of 20 to 40.
The CMOS according to any one of claims 1 to 6, wherein?
Semiconductor device. 8. A P-channel M defined on a silicon substrate.
Forming a first gate insulating film in which a nitrogen concentration peak does not exist at an interface with the silicon substrate in an OS transistor formation region and an N-channel MOS transistor formation region; Removing the first gate insulating film in the N-channel MOS transistor forming region by masking the first gate insulating film; and forming a nitrogen concentration peak in the N-channel MOS transistor forming region with the silicon substrate. Forming a second gate insulating film existing near the interface. 9. A P-channel M defined on a silicon substrate
Forming a second gate insulating film having a nitrogen concentration peak at an interface with the silicon substrate in an OS transistor formation region and an N-channel MOS transistor formation region; By masking the second gate insulating film, the P-channel M
Removing the second gate insulating film in the OS transistor forming region; and forming a first gate insulating film in the P channel MOS transistor forming region where a nitrogen concentration peak does not exist at the interface with the silicon substrate. And a method for manufacturing a CMOS semiconductor device. 10. The first gate insulating film includes a step of forming a silicon oxynitride film by oxynitriding the silicon substrate, and a step of oxidizing the silicon substrate to form a layer below the silicon oxynitride film. 10. The CMO according to claim 8, further comprising a step of forming a silicon oxide film.
A method for manufacturing an S semiconductor device. 11. The second gate insulating film includes a step of oxidizing the silicon substrate to form a silicon oxide film, and a step of oxidizing and nitriding the silicon substrate to form a silicon oxide film under the silicon oxide film. 11. The method of manufacturing a CMOS semiconductor device according to claim 8, further comprising a step of forming a nitride film.