JP2000267650A - Picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a picture display device to perform a high-speed arithmetic operation, and to prevent a waiting state of a processor from occurring due to operating state of a picture memory, by controlling matrix connections so that drawing-operated data are written in the memory presenting the state in which data have already been outputted for display. SOLUTION: This picture display device is provided with graphic controllers(GC) 61-63 which are connected to a CPU 51 managing the control of the whole device via a common bus 55 and perform prescribed drawings, video RAMs(VRAM) 81-84, and a multiplexer(MUX) 70 for switching correspondences between these plural GC and the VRAMs. And CPU 51 communicates with CG 61-63, and outputs drawing data to GC which have completed drawing operation. Namely, for example, CG 61 receives drawing data from CPU 51 and recognizes VRAM 84, which has already completed displaying, as memory for own drawing for this time, and clears the whole memory area of VRAM 84 before starting frame-drawing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device such as a drawing device for graphically displaying image data on a display device such as a CRT.

[0002]

2. Description of the Related Art With the recent development of computer graphics (CG) technology, there has been a demand for a device for processing image data at high speed and displaying the processed image at high speed. In order to perform this kind of high-speed processing, for example, a method of performing image generation processing in parallel by a plurality of processors has been proposed. However, even with this method, there is a problem in that, when a plurality of generated images are displayed on a screen, processing is concentrated on a specific processor due to the switching process, and the load becomes heavy.

Therefore, the following display method has been proposed as a processing method for solving this problem and efficiently displaying parallel images. FIG. 9 shows Japanese Patent Laid-Open Publication No.
1 is a block diagram illustrating an image display processing method disclosed in Japanese Patent Publication No. 80; The system shown in FIG. 1 is a processor 1, a modeling coordinate transformation processor 1 of a first system among M systems.
1, a first-system view coordinate conversion processor 12, a first-system device coordinate conversion processor 13, a first-system physical pixel position generation processor 14, a first-system image memory 15, and have the same configuration as the above processor group. Second system processing part 21
And M-th processing units 31 to 35 having the same configuration, a multiplexer (MUX) 6 for switching frames from these processing units, and C
The display processing is executed by providing the monitor device 7 using an RT or the like.

The operation of the system shown in FIG. 9 will be described below.
The processor 1 distributes display elements for each display frame to the modeling coordinate transformation processors 11, 21, and 31 in the first stage. These modeling coordinate conversion processors perform translation, rotation, enlargement / reduction of display elements, and then convert these display elements into view coordinate conversion processors 12, 22, and 3.
Output to 2. These field-of-view coordinates conversion processors perform field-of-view coordinates conversion such as parallel projection and perspective projection for projecting display elements on a two-dimensional display surface.

The device coordinate conversion processors 13, 23,
33 determines the display position (device coordinate conversion) to match the size of the display screen, and the physical pixel position generation processors 14, 24, and 34 convert the device coordinate conversion data to the physical size of the display screen ( (Number of pixels). This processing result is stored in the image memory 15,
25 and 35.

The above image memory has a resolution (for example, 1280) corresponding to the resolution of the monitor device 7 connected thereto.
× 1024), and the display pixel position data output from the physical pixel position generation processors 14, 24, and 34 is recorded at a display position address of this image memory in a one-to-one correspondence. Then, the data recorded in the image memory is output to the multiplexer 6 as a video signal synchronized with the display raster position signal.

[0007] The multiplexer 6 comprises image memories 15 and 2
After switching the video signals from 5, 35 on a frame basis so that the latest video signal is selected and output,
Output to the monitor device 7. Here, the frame unit is
One plane surface (for example, 128
0 × 1024). As described above, the configuration according to the above conventional method is a frame parallel processing.

[0008]

However, in the conventional system, since a plurality of processors have the above configuration,
In each of the plurality of processors, it is not possible to perform an operation on a part of the screen area and combine and display them. Further, since each processor and the image memory are configured as a pair, there is a problem that the processor that performs the writing operation on the image memory being displayed enters a waiting state.

Furthermore, the above-mentioned conventional method does not take into consideration the time required for frame processing or the flicker that occurs when the same memory is used for display and writing, and has a configuration in which processing for that is performed. Therefore, when the corresponding image memory is outputting to the multiplexer for display, there is a problem that writing cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a processor that performs a write operation to an image memory, can perform the operation at high speed, and operates the image memory. Accordingly, an object of the present invention is to provide an image display device in which the processor does not enter a waiting state.

Another object of the present invention is to provide an image display apparatus which does not cause flicker in the visual display of image data.

[0012]

In order to achieve the above object, the present invention relates to an image display apparatus for visually displaying input image data. Drawing processing means;
A plurality of image memories for storing the data after the drawing operation; and a connecting means for connecting the plurality of drawing processing means and the plurality of image memories to each other in a matrix. The present invention provides an image display device that controls the matrix connection so that the data after the drawing operation is written in a memory whose operation state display indicates a state where data output for display has already been completed.

[0013] Preferably, the operation status display is a time stamp corresponding to a new or old time when data is written to the plurality of image memories. Preferably, the number of the image processing units and the number of the image memories are the same, or the number of the image memories is larger than the number of the image processing units.

Preferably, the image display device according to the present invention comprises:
Further, 1 for storing image data common to the visible display.
Alternatively, it is equipped with a buffer memory of a larger size. The buffer memory is shared by the plurality of drawing processing units. Further, the buffer memory is provided corresponding to the plurality of drawing processing units.

Preferably, the image display device according to the present invention comprises:
Further, a display color reference table corresponding to the plurality of image memories is provided.

Preferably, the plurality of drawing processing means include:
The frame related to the drawing frame data is divided into a plurality of windows, and the drawing calculation is executed for each window. The plurality of image memories correspond to the plurality of windows.

More preferably, the plurality of drawing processing means divides a frame related to the drawing frame data into a plurality of frames, and performs the drawing calculation on the divided frames. Further, the plurality of image memories correspond to the plurality of frames.

Preferably, the plurality of drawing processing means include:
A process of dividing the frame related to the drawing frame data into a plurality of windows and performing the drawing operation on a window basis; dividing the frame related to the drawing frame data into a plurality of frames; The processing for performing the operation is executed in parallel.

Preferably, the visible display is performed after the storage of the data after the drawing operation is completed and before the next drawing operation is started.

[0020]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of the image display device according to Embodiment 1 of the present invention. The device shown in the figure is a central processing unit (hereinafter, simply referred to as a CPU) 51 for controlling the entire device, and a graphic controller (hereinafter, referred to as a CPU) connected to the CPU 51 via a common bus 55 to perform predetermined drawing. GC) 61-63, video RAM for storing image data (drawing data)
(Hereinafter referred to as VRAM) 81 to 84, and a plurality of G
A multiplexer (M) for switching the correspondence between C and VRAM, that is, switching which GC and output of VRAM correspond.
UX) 70.

A selector (hereinafter, referred to as SEL) 90 of the present apparatus switches which output from the plurality of VRAMs 81 to 84 is to be displayed on a monitor 170, which will be described later. Lookup table & digital / analog converter (hereinafter simply referred to as LUT
& D / A) 100 performs color conversion and a process of converting a digital signal to an analog signal. The converted signal is input to, for example, a monitor 170 constituted by a CRT or the like. When the monitor 170 has a digital interface, the conversion to an analog signal by the LUT & D / A 100 is unnecessary.

On the other hand, the controller 110
U51, GC61-63, and VRAM81-84 output data from these VRAM to monitor 170
A synchronization signal or the like to be output at a timing synchronized with.

Next, the operation of the image display device according to the present embodiment will be described in detail. CPU of the image display device
51, when drawing data is input, first, which GC
61 to 63 manage which VRAMs 81 to 84 and which VRAMs 81 to 84 are performing raster display. After this recognition, the CPU 51 sets the GCs 61 to 63
And outputs drawing data to the GC that has completed the drawing calculation.

After receiving the drawing data, the GC checks the processing status of the plurality of GCs, and further recognizes which GC and the VRAM are paired, and then checks the time stamp of the VRAM. Thereafter, if this GC confirms that the time stamp of the released VRAM is the oldest time stamp, the GC stores the VRAM in its own GC.
And the drawing process is started.

For example, when the CPU 51 determines that the drawing data can be transferred to the GC 61, and actually transfers the drawing data, the GC checks the time stamp of the VRAM and transfers it to the VRAM (for example, the VRAM 81) during raster display. Write time stamp 0. Also, the VRAM that has finished displaying
(For example, VRAMs 83 and 84) are written with time stamps -1 and -2, respectively.

On the other hand, during drawing (for example, when the GC 62
In the case where the drawing data is currently being written using M82), the VRAM 82 is provided with a time stamp 1. Thereafter, the GC 61 receives drawing data from the CPU 51 and recognizes the VRAM 84 that has already been displayed as its own drawing memory. Then, if necessary, the entire memory area of the VRAM 84 is cleared, and then the frame drawing is started.

Since one GC processes one drawing frame data, each GC has a buffer memory such as a FIFO and is configured to be able to input drawing data from the CPU without delay. Also, MUX70
Is a multiplexer for matrix-connecting the GC and the VRAM, and this multiplexer can freely change the connection between the GC and the VRAM.

When the GC completes the drawing process, the VRA
By giving a time stamp to M and releasing it, V
When the RAM is connected to the display side, the display ends,
If there is a VRAM having the next time stamp, it means that it is in a writable state.

That is, since the VRAM is open (separated) except for the one being drawn and the one being displayed, the GC receiving the drawing command from the CPU 51
In general, a procedure of deleting the data from the VRAM holding the oldest data and starting drawing of the display screen newly is adopted.

Further, the status of drawing or displaying the GC is indicated by the controller 110.
The controller 110 collects the status status of each of these GCs, and can confirm these statuses in response to a request from the CPU 51. The contents are displayed as GC operation status display (during drawing or end of drawing), and as VRAM operation status display, "VRAM display completed", "VRAM not displayed",
If there are multiple timestamps for “VRAM display in progress” and “VRAM display complete”,
Enter the time stamp of the display completion order.

The VRAM is a frame memory for recording and displaying drawing data from the GC, and is usually constituted by a dual port type GRAM (RAM dedicated to image display). The VRAM has a DRA inside.
A refresh controller is required because of the M configuration. Therefore, in this device, the controller 110
Refresh processing, or by using a VRAM with a built-in refresh controller, the intended refresh processing is performed.

In this apparatus, the number of GCs and the number of VRAMs are equal, or the number of VRAMs is larger than that of the GC (in this case, for example, the structure shown in FIG. 1 is used). The display can be updated without accessing the VRAM being displayed.

The outputs from the VRAMs 81 to 84 are subjected to display output switching by the SEL 90. This switching is performed after the VRAM drawing is completed and before the frame drawing is started. As a result, the switching noise of the display screen is not displayed. Note that even if this switching is performed during display, the display plane configuration of the VRAM is the same, so that the switching change can be made almost invisible by visual observation.

As described above, according to the present embodiment, based on the graphic controller (GC) and the operation state display of the VRAM, which output of the plurality of VRAMs is displayed on the monitor. Since the switching is performed and the GC and the VRAM for display are not paired, the calculation load of the GC is averaged, and the display calculation is performed without waiting for the GC in the VRAM in the operation state of displaying. Can be performed, and as a result, the speed of drawing can be increased.

Further, by configuring the apparatus such that the number of GCs and VRAMs is the same or the number of VRAMs is larger than that of GC, the display can be updated without accessing the VRAM being displayed. .

Embodiment 2 Hereinafter, Embodiment 2 of the present invention will be described. FIG. 2 is a block diagram showing a configuration of the image display device according to the second embodiment. In the image display device according to the present embodiment shown in FIG. 1, the same components as those in the image display device according to the first embodiment shown in FIG. Are omitted, and the characteristic features of the present embodiment will be described.

The apparatus according to the first embodiment has a configuration in which each VRAM also has a shared memory, that is, a display area of a memory used for display that is infrequently updated on display and used for display that can be shared. ing. However, in the device according to the second embodiment, the calculation load of the GC is reduced by sharing the frame memory.

The image display device shown in FIG.
In the configuration according to the first embodiment, a frame buffer memory 120 is newly connected on the common bus 55. The frame buffer memory 120 stores map data, various font data, and the like as common data when drawing. These data are stored in the CPU 51 in advance as data that can be shared.
Is data input to the frame buffer memory 120, and the frame buffer memory 120
The self itself is also under the control of the CPU 51.

As described above, by the frame buffer memory 120 controlled by the CPU 51, each GC can transmit the common data to the VRAM by prop transfer, for example, with a light load such as scaling operation such as enlargement or offset. Can be transferred.

As described above, according to the present embodiment, the CPU controls the frame buffer memory, and the buffer memory uses the same load as the VRAM with a light load such as scaling operation such as enlargement and offset. By transferring the data, it is possible to concentrate on the calculation of the change, so that high-speed drawing is possible.

Embodiment 3 Hereinafter, Embodiment 3 of the present invention will be described. FIG. 3 is a block diagram showing a configuration of the image display device according to the third embodiment. In the image display device according to the present embodiment shown in FIG. 1, the same components as those in the image display device according to the first embodiment shown in FIG. Are omitted, and the following description focuses on features that are characteristic of the present embodiment.

In the image display device according to the second embodiment, the CPU 51 manages the shared memory and performs drawing. In the third embodiment, the drawing is performed by GC. That is, the image display device according to the third embodiment has a configuration in which the GCs 61 to 63 and the newly added GC shared memory 130 are connected via the common bus 56 as shown in FIG. Here, after outputting the common drawing data, the CPU 51 sends normal drawing data to the GC.

Each of the GCs first performs C
It is determined whether there is common data in the data output by the PU 51. And if there is common data, it is
Output to shared memory 130. The GC calculates
While referring to this GC shared memory 130, each VRAM
Performs drawing calculation output to.

As described above, in the apparatus according to the present embodiment, if there is common data in the data from the CPU, the common data is stored in the GC shared memory, and the GC uses this G when performing the drawing operation.
By performing drawing calculation output to each VRAM while referring to the C shared memory, more efficient high-speed drawing becomes possible.

Embodiment 4 Hereinafter, Embodiment 4 of the present invention will be described. FIG. 4 is a block diagram showing a configuration of the image display device according to the present embodiment. FIG.
Shows a main part of the image display device according to the present embodiment, and the same components as those in the image display device according to the first embodiment shown in FIG. In the following, a description thereof will be omitted, and a portion that is characteristic of the present embodiment will be mainly described.

That is, in FIG. 4, V
The configuration after the RAMs 81 to 84 is shown, and the components of the input stage to them are the same as those of the image display device according to the first embodiment, and the illustration thereof is omitted. In the image display device according to the first embodiment, as shown in FIG. 1, a look-up table (LUT & D / A) 100
However, when the display color of the display screen is dynamically changed, a single look-up table is not sufficient.

Therefore, in the image display device according to the present embodiment, as shown in FIG. 4, the same number of lookup tables (LUTs) 101 to 104 as the VRAMs 81 to 84 are provided, and these LUTs are provided by the GC or the CPU. Perform write update. Here, the number of LUTs is a number necessary for dynamically changing the display color of the display screen. In the subsequent stage, a selector (SEL) 140 that finally selects the LUT required for the display is provided. Is located.

Note that, unlike the image display device according to the first embodiment, in the image display device according to the present embodiment, the look-up table and the digital / analog conversion unit are separated from each other. The digital / analog conversion unit (D / A) 150 is newly provided at the subsequent stage.

As described above, according to the present embodiment, the same number of lookup tables (LUs) as VRAMs are used.
T) is provided, and these LUs are
By writing and updating T, the LUT can be selected at high speed, and the display color of the display screen can be dynamically changed.

Embodiment 5 Hereinafter, a fifth embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration of the image display device according to the fifth embodiment. In the image display device according to the present embodiment shown in FIG. 3, the same components as those in the image display device according to the third embodiment shown in FIG. Is omitted. Therefore, the following description focuses on features that are characteristic of the present embodiment.

The image display device according to the third embodiment shown in FIG. 3 has a single GC which is commonly controlled and used by each GC.
The shared memory 130 is used. When this configuration is adopted, there is a possibility that contention for access on the same bus occurs between GCs. Therefore, in the device according to the present embodiment, a memory that is paired with each GC is provided in case the contents of the shared memory change in various ways, and this problem is avoided.

More specifically, as shown in FIG. 5, the GC 61-63 and the GC temporary memory 161 are connected to the common bus 56.
163 are connected, and these GC temporary memories are stored in the GCs before writing to the VRAMs 81 to 84.
Used for common operation and data storage.

As described above, in the present embodiment, the memories for temporarily storing the drawing data which are paired with the respective GCs are provided, and these memories are used for the common operation of the GCs before the writing to the VRAM. Or for data storage, access conflicts between GCs on the same bus can be avoided.

Embodiment 6 FIG. Hereinafter, Embodiment 6 of the present invention will be described. FIG. 6 is a block diagram showing a configuration of the image display device according to the sixth embodiment. In the image display device according to the present embodiment shown in FIG. 1, the same components as those in the image display device according to the first embodiment shown in FIG. Are omitted, and the following description focuses on features that are characteristic of the present embodiment.

In the image display device according to the first embodiment, VRAMs 81 to 84 are stored in frame units (display images).
It operates on the basis of. On the other hand, the device according to the sixth embodiment divides a frame into windows and performs arithmetic processing. That is, the device shown in FIG.
7 has a CPU 191 that instructs the GC 201 and 202 connected to the common bus 57 to divide the frame display, and a CPU 192 that instructs the GC 204 and 205 connected to the common bus 57 to divide the frame display.

These GCs 201, 202, 204, 2
In step 05, upon receiving an instruction from the CPU, the frame is divided into window units and a predetermined drawing operation is performed. The drawing data calculated by each GC is stored in the VRAMs 171 to 174 provided corresponding to each GC in a window-divided format. On the other hand, the common bus 57
The GCs 203 and 206 are connected to a window RAM (WINDRAM) 18 provided at the subsequent stage of the VRAMs 171 to 174, for instructing which of the drawing data stored in each VRAM is to be prioritized in window units.
1,182.

As described above, according to the present embodiment, it is possible to divide a frame into a plurality of windows by using a dedicated GC and perform arithmetic processing on a window-by-window basis, thereby enabling parallel processing of drawing arithmetic. Therefore, the drawing operation can be executed at a higher speed.

Embodiment 7 FIG. Hereinafter, a seventh embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration of the image display device according to the seventh embodiment. Note that, in the image display device according to the present embodiment shown in the same figure, the same components as those in the image display device according to the sixth embodiment shown in FIG. Is omitted. Therefore, the following description focuses on features that are characteristic of the present embodiment.

In the apparatus shown in FIG. 7, the common bus 58 is connected to the CPU 191 and the GCs 211 and 212, and the common bus 59 is connected to the CPU 192 and the GCs 213 and 214. With this configuration, the GC 211, 21
2 divides one frame into two according to an instruction from the CPU 191, and similarly, the GCs 213 and 214
One frame is divided into two in accordance with an instruction from 92.
That is, in the apparatus according to the present embodiment, the display area is reduced by this frame division (simple vertical or horizontal division).
2, 213 and 214 are designated.

The VRAMs 221 and 222 are separately provided so that two frames constitute one frame, and the VRAMs 223 and 224 have the same configuration. Then, the SELs 231 and 232
The frame output divided into areas from M221 to 224 is selected, and it is set as one frame, and SEL9 of the next stage is selected.
Output to 0.

In the apparatus shown in FIG. 7, the GC 211,
Although 212 and GCs 213 and 214 divide each frame into two, the number of divisions is not limited to this, and may be two or more. In that case, according to the number of divisions, GC
And increase the number of VRAMs.

As described above, according to the present embodiment, one frame is divided into two or more parts, and the display area is reduced to perform the drawing processing, whereby the processing can be sped up. .

Embodiment 8 FIG. Hereinafter, an eighth embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration of the image display device according to the eighth embodiment. It should be noted that the image display device according to the present embodiment shown in FIG. 7 includes an image display device according to the sixth embodiment shown in FIG. 6 and an image display device according to the seventh embodiment shown in FIG. Since the device has a configuration in which the image display device according to the sixth and seventh embodiments is combined, the same components as those of the image display devices according to the sixth and seventh embodiments are denoted by the same reference numerals,
Here, the description is omitted. Therefore, the following description focuses on features that are characteristic of the present embodiment.

CPUs 191 and 192 of the apparatus shown in FIG.
Is responsible for the drawing process for each frame.
GC 241 connected to the common bus 191 via the common bus 58
A window 242 performs a region process on each of the divided display surfaces according to an instruction from the CPU. VRAM2
Reference numerals 51 and 252 store the drawing data processed by the GC for the divided display surface of the window described above.

The window divided in this way is called VR
The signals are sent from the AMs 251 and 252 to the combiner (MIX) 261 where the windows are combined. GC243, 244 also connected to the common bus 58, and VRAMs 253, 254, MIX2
62 also performs the same processing as described above for another window.

That is, the VRAMs 253 and 254 store the drawing data for the divided display surfaces of different windows, and the MIX 262 combines these different window display surfaces. And a window RAM (WINDRAM)
Reference numeral 181 combines the window display surfaces output from the MIXs 261 and 262. The GC 203 connected to the common bus 58 rewrites the window RAM 181.

It should be noted that the GCs 245 to 248 and the VRAM 25
5-258, MIX 263, 264, window RAM
182 and the GC 206 perform the same operation as the above-described components corresponding to these components with respect to another window, and therefore, the description thereof is omitted here.

As described above, according to the present embodiment, a frame divided into two or more frames is divided into a plurality of windows, arithmetic processing is performed for each window, and the display area is reduced so that the drawing processing is performed. by doing,
Since frame-window parallel processing of the drawing operation is possible, the drawing operation can be executed at higher speed.

[0069]

As described above, the present invention relates to an image display device for visually displaying input image data.
A plurality of drawing processing means for performing drawing calculation on the drawing frame data of the image data; a plurality of image memories for storing the data after the drawing calculation; and a plurality of drawing processing means and the plurality of image memories. Connection means for performing matrix connection, wherein the connection means stores the data after the drawing operation in a memory in which an operation state display of the plurality of image memories indicates a state in which data output for display has already been completed. By controlling the matrix connection so that is written, the drawing processing means can perform a drawing calculation for display without waiting in the image memory in an operation state of displaying, and can speed up drawing.

Since the operation status display is a time stamp corresponding to the new or old time when data was written to the plurality of image memories, it is easy to know the time when data was written to the memory. it can.

Further, the number of the image processing means and the number of the image memories are the same, or the number of the image memories is larger than the number of the image processing means, thereby accessing the image memory being displayed. The display can be updated without the need.

The image display device according to the present invention further comprises one or more buffer memories for storing image data common to the above-mentioned visible display, so that it is possible to concentrate on the calculation of the change. Become.

Further, by sharing the buffer memory with the plurality of drawing processing means, more efficient high-speed drawing becomes possible. Further, by providing these buffer memories corresponding to the plurality of drawing processing units, it is possible to avoid access conflicts and perform high-speed drawing.

The image display device according to the present invention further includes a display color reference table corresponding to the plurality of image memories, so that the reference table (LUT) can be selected instantaneously, and the display color of the display screen can be dynamically changed. Can be changed.

Further, the plurality of drawing processing means divides the frame related to the drawing frame data into a plurality of windows, and executes the drawing calculation for each of these windows, thereby enabling parallel processing of the drawing calculation. The drawing operation can be executed at higher speed. Further, by associating the plurality of image memories with the plurality of windows, the processing can be speeded up.

Further, the plurality of drawing processing means divides the frame related to the drawing frame data into a plurality of frames, and performs the drawing calculation on the divided frames, whereby high-speed drawing calculation processing can be performed. By associating the plurality of image memories with the plurality of frames, high-speed processing can be performed.

Further, the plurality of drawing processing means according to the image display device of the present invention divides a frame related to the drawing frame data into a plurality of windows, and performs the drawing calculation for each window. By dividing the frame related to the drawing frame data into a plurality of frames and performing the above-described drawing calculation on the divided frames in parallel, a higher-speed drawing calculation can be performed by the frame-window parallel processing.

Then, by performing the visible display after the storage of the data after the drawing operation is completed and before the next drawing operation is started, the display flicker can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an image display device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an image display device according to Embodiment 3 of the present invention.

FIG. 4 is a block diagram showing a configuration of an image display device according to Embodiment 4 of the present invention.

FIG. 5 is a block diagram showing a configuration of an image display device according to Embodiment 5 of the present invention.

FIG. 6 is a block diagram showing a configuration of an image display device according to Embodiment 6 of the present invention.

FIG. 7 is a block diagram illustrating a configuration of an image display device according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of an image display device according to Embodiment 8 of the present invention.

FIG. 9 is a block diagram showing a conventional image display processing method.

[Explanation of symbols]

51, 191, 192 CPU, 55-58 ... common bus, 61-63, 201-206, 211-214 ... graphic controller (GC), 81-84, 22
1-224, 251-254 ... Video RAM (VRA
M), 70... Multiplexer (MUX), 90, 140
... Selector (SEL), 100, 101-104 ... Look-up table & digital / analog conversion unit (L
UT & D / A), 150 ... Digital / analog conversion unit (D / A), 161-163 ... GC temporary memory, 170 ... Monitor, 181,182 ... Window RA
M (WINDRAM), 261-264 ... synthesizer (MI
X)

Claims (13)

[Claims] 1. An image display device for visually displaying input image data, comprising: a plurality of drawing processing means for performing a drawing operation on drawing frame data of the image data; An image memory; and a connection unit for connecting the plurality of image processing units and the plurality of image memories to each other in a matrix. The connection unit includes an operation state display of the plurality of image memories that is already displayed. An image display device for controlling the matrix connection so that the data after the drawing operation is written to a memory indicating a state where data output has been completed. 2. The image display device according to claim 1, wherein the operation status display is a time stamp corresponding to a new or old time when data is written to the plurality of image memories. 3. The image display device according to claim 1, wherein the number of the image processing units and the number of the image memories are the same, or the number of the image memories is larger than the number of the image processing units. 4. The image display device according to claim 1, further comprising one or more buffer memories for storing image data common to the visible display. 5. The buffer memory according to claim 4, wherein the buffer memory is shared by the plurality of drawing processing units.
The image display device as described in the above. 6. The image display device according to claim 4, wherein said buffer memory is provided corresponding to said plurality of drawing processing units. 7. The image display device according to claim 1, further comprising a display color reference table corresponding to the plurality of image memories. 8. The image display according to claim 1, wherein said plurality of drawing processing means divides a frame related to said drawing frame data into a plurality of windows, and executes said drawing operation in units of said windows. apparatus. 9. The image display device according to claim 8, wherein said plurality of image memories correspond to said plurality of windows. 10. The image according to claim 1, wherein the plurality of drawing processing units divide a frame related to the drawing frame data into a plurality of frames, and perform the drawing operation on the divided frames. Display device. 11. The image display device according to claim 10, wherein said plurality of image memories correspond to said plurality of frames. 12. The plurality of drawing processing means divides a frame related to the drawing frame data into a plurality of windows, performs the drawing operation on a window basis, and converts the frame related to the drawing frame data into a plurality of windows. 2. The image display device according to claim 1, wherein a process of dividing into frames and performing the drawing operation on the divided frames is performed in parallel. 13. The image display apparatus according to claim 1, wherein the visual display is performed after storage of the data after the drawing operation is completed and before the next drawing operation is started.