JP2000261329A - Viterbi identifying method, lead channel semiconductor device and magnetic disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize application with a small circuit scale by executing a processing at every two clock processing, comparing the groups of metrics whose difference of metrics is estimated to be small at first among plural metrics which are modulo-normalized and selecting the minimum metric. SOLUTION: In comparison circuits 17-1 and 17-2 for the binary code of a complement system using modulo normalization, first comparison is executed. In the case of metric P1 < metric P2 and metric P3 < metric P4, output becomes '1' in an AND circuit 18-1 only and outputs become '0' in other AND circuits 18-2 to 18-4. The output signal of a comparison circuit 17-3 can the sent to a post stage with the output of the AND circuit 18-1. In the case of P1<P3, the output of an AND circuit 18-5 becomes '1' and the output of an AND circuit 18-6 becomes '0'. Output '1' appears in an OR circuit 20-1 only and the metric P1 is selected as the minimum metric.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing method for recording or transmitting digital data. More specifically, the present invention is suitable for implementing high-speed Viterbi identification when reading or receiving a digital signal. It relates to signal processing.

[0002]

2. Description of the Related Art As the operation speed of a computer increases, application software that requires a large-capacity memory is used, and the density of a magnetic disk device is increased, and the transfer speed of a recording signal is increased. Are increasingly demanding. In response to such technical problems, partial response class 4 (hereinafter referred to as PR4)
The PRML method combining Viterbi identification, which is one of the maximum likelihood decoding, and its development form have attracted attention. These technical features are described in, for example, "PRML and Coding Techniques" of the Journal of the Japan Society of Applied Magnetics, 17-2, 4 August, 1994. Recording code levels +1 and -1 are recorded on the recording medium in correspondence with the recording codes 1 and 0. PR4M for high density recording
The signal processing of EPR4ML, which is an extension of L, is advantageous. In the EPR4ML, a single recorded positive pulse signal +1 is read, and D is used as a 1-bit delay operator at the time of reading so that a response expressed as 1 + D−D ² −D ³ is obtained.
PR4 equalization. Further, after this equalization processing, a Viterbi discriminator, which is one of the maximum likelihood discriminations (ML processing), is provided for discriminating the original recording code.

Normally, the operation of the Viterbi discriminator is premised on processing for each bit. However, since it becomes difficult to process each bit with a signal having a high transfer rate, parallelization of a Viterbi discriminator has been proposed. For example: K. Ye
eung and J.M. M. Rabaey in 1995 IE
EE International Solid-Sta
A 210 Mb / s Radix-4 Bit-lev at te Circuits Conference
el Pipelined Viterbi Decod
er published a Viterbi discriminator that processes every two clocks. FIG. 1A shows an example of one part (for two clocks) of a trellis diagram when the Viterbi discriminator in four states is processed for each clock. In each state, it is necessary to compare the values of two metrics corresponding to two trellises and select the smaller one. On the other hand, in order to process with two clocks, as shown in (b), the minimum one is selected from the four metrics in each state. Although the circuit scale is large, it is necessary processing for speeding up.

The minimum value metric selected in each state becomes a new surviving path metric. Similarly, the surviving path metrics are updated at the next clock. As a result, the value of the path metric increases toward minus infinity over time. But,
If the metrics can be compared in each state, the smallest one can be selected, so there is no need to particularly store the accumulated value. By utilizing this fact, a metric calculation circuit is designed.

In a first example, a predetermined value is added to a path metric value in each state at a predetermined period to limit the path metric value to a value within a predetermined value, so that a bit representing the path metric is expressed. The number is kept constant. However, this method requires an adder circuit in each state.

In a second example, a method has been proposed in which path metrics are represented by a relatively large number of bits, and when the metrics exceed a limit that can be represented by the number of bits, carry-out bits are ignored and processed. I have. This is called modulo normalization. For example, C.I. Shung, P .; Si
egel, G .; Ungerboeck, H .; Thap
ar was the International Co in 1990
"VLSI Architecture fo" at an international conference called "mmunication Conference".
r Metric Normalization of
He Viterbi Algorithm, ”mentions the effectiveness of modulo normalization.
The fact that this modulo normalization is used in a prototype of a PRML LSI using an 8/10 code is an IEEE standard.
Trans. on Magnetics, Vol. 31, No. 2, March 1995, pp. 1208-1214 (Design and P by J. Rae et al.)
eformance of aVLSI 120Mb / s
Trellis-Coded Partial Resp
once channel).

However, examples of these modulo normalizations are as follows:
It only mentions comparing two metrics in each state.

Since the present invention aims at handling a high-speed transfer signal, the present invention is directed to a case where Viterbi identification is performed in parallel, and provides a suitable method of a modulo normalization method at that time and an application device thereof. Things.

[0009] The signal processing of the PR channel system and
The Viterbi identification operation and the like are processing operations having positive and negative signal values. Therefore, when digital signal processing is performed for this processing, the sample value is usually represented by a binary code in a two's complement format. Since the following embodiment is also described using the two's complement binary code, this code format will be introduced with reference to FIG. 2 and its modulo normalization will be described. FIG. 2A shows the case of 4 bits.
The binary code corresponding to the plus or minus the actual signal level is shown. FIG. 2B illustrates the modulo normalization in an easy-to-understand manner. In the modulo normalization, it is sufficient to consider that the actual signal levels are arranged on the circumference. Addition is clockwise and subtraction is counterclockwise. Since the carry bit is ignored, the minimum signal level automatically leads to the maximum signal level. Metrics can always be handled with a fixed number of bits.
If a plurality of metric values are made to correspond to the positions on the circumference, the one moving in the clockwise direction will be smaller.

[0010]

The present invention uses modulo normalization and compares a plurality of metrics in each state in a Viterbi discriminator that processes two clocks. When selecting the smallest metric, the difference between the metrics is calculated. A means for first comparing a set of metrics estimated to be small and a means for selecting a minimum metric using the result of the comparing means are used.

[0011]

FIG. 3 is a signal processing system diagram in a magnetic disk device according to an embodiment of the present invention. The signal processing system includes an interface and an error correction unit IEC, and a read channel (Re).
ad channel), and a recording / reproducing device unit RWD. Reference numeral 1 denotes an interface circuit for transmitting and receiving information data between a magnetic disk drive and a computer (not shown). Reference numeral 2 denotes a check code insertion circuit that calculates a check code for error correction for information data of a predetermined length to be recorded and inserts the check code.
Reference numeral 3 denotes a randomizing circuit that adds a predetermined random series of data to the information data and randomizes data to be recorded as much as possible so that a fixed signal pattern is not repeated. Reference numeral 4 denotes a recording encoding circuit that performs encoding suitable for a recording medium. Numeral 5 denotes a recording medium that records a recording-encoded recording signal by a recording magnetic head 6W.
This is a recording amplifier circuit for amplifying to a signal amplitude necessary for recording on a recording medium. The signal recorded on the recording medium 7 is read by the read magnetic head 6R. Reference numeral 8 denotes a reproduction amplifier circuit for amplifying the read signal to a predetermined amplitude for subsequent processing. Reference numeral 9 denotes a digital filter circuit for performing EPR4 equalization suitable for high-density recording. Reference numeral 10 denotes a Viterbi identification circuit according to the present invention which employs two-clock parallel processing suitable for high-speed transfer and further employs path metric operation by modulo normalization. It is characterized by realizing high-speed transfer and preventing an increase in circuit scale. The Viterbi discrimination circuit eliminates the influence of the recording medium noise and the noise of the reproduction amplification means, and obtains a reproduction signal with few code errors. Reference numeral 11 denotes a decoding circuit that performs a reverse conversion of the recording encoding from the reproduction signal. Reference numeral 12 denotes an inverse randomizing circuit for restoring the randomization processed on the recording side. Reference numeral 13 denotes an error correction circuit that performs error correction on remaining code errors.

As described above, since the magnetic disk device always uses a suitable recording coding for recording on a recording medium, a decoding means which is a process reverse to the recording coding is used at the time of reading. . Viterbi identification is a signal means inside recording encoding / decoding. Generally, the term “Viterbi decoding” is also used, but here, Viterbi identification is used to avoid confusion.

Since the EPR4 equalization and the Viterbi identification method are known, the outline thereof will be described here. When Viterbi identification is performed on an EPR4 equalized output signal, as shown in FIG. 4, it is necessary to perform an operation on branch metrics described below for eight states. Each state is associated with a 3-bit recording code C (n-3), C (n-2), C (n-1). Let the equalized output corresponding to time T (n) be y (n). At this time, for example, whether the state has transitioned to the state 0 at the time T (n) from the state 0 at the time T (n-1),
Either the state has transited from the state 4 at the time T (n-1). To determine this, it is first necessary to determine the metric value for each path given by:

｛M0 (n-1) + bm00, M4 (n
-1) + bm40} where Mk (n-1) is the time T (n-1) of state k
, The smaller the value, the time T (n
-1) indicates that there is a high possibility that the state was k. The second term bmij indicates the branch metric from state i to state j. bmij is the square value (y (n) -Y (n) of the difference between the expected equalized output Y (n) when there is no noise and the actually obtained equalized output y (n) at the time of the state transition. )) Given by ² . Next, the path is determined by selecting the smaller one of the two metrics, and the metric value is changed to the path metric M0 in the state 0 at the time T (n).
(N). That is, M0 (n) = min ｛M0 (n-1) + bm00, M
4 (n-1) + bm40}.

At this time, if a path from state 4 to state 0 is selected, for example, the past path sequence of state 4 at time T (n-1) and the current path include T
The path sequence in state 0 of (n) is stored in the path memory in state 0. In this pass, that is, the pass from state 4 to state 0, the expected recording code is 0,
The path value is stored as 0. The surviving path sequence stored in this way is the maximum likelihood path sequence in which the path metric in state 0 is minimized.

The expected equalized output Y (n) of the EPR4 has a recording code indicating a state of C (n-3), C (n-2), C (n-
When transitioning from 1) to C (n−2), C (n−1), C (n), Y (n) = (− 1) ^{1−C (n)} + (− 1) ^{1−C ( n-1)} + (-
1) It is given by ^{C (n-2)} + (-1) ^{C (n-3)} . For example, from state 0 to state 0, time T
Since the expected output Y (n) without noise at (n) is 0, bm00 = (y (n) -0) ² . Similarly, since the expected equalized output from the state 4 to the state 0 is −1, it is given by the branch metric bm40 = (y (n) − (− 1)) ² . Here, since y (n) ² is a common term in all states, the calculation is performed by removing this. That is,
bm00 = 0 and bm40 = 2y (n) +1.

In the initial state, the path metric values of all the states are set to 0, and the above operations are sequentially executed. In each state, the maximum likelihood path is stored for L bits (L is about 20 to 30). At each time, the most previous path, that is, the value before L bits is compared, and the number of the same code value is counted in 8 states. , The more
It is distinguished from the recording code before L bits. As a result, it is possible to minimize the influence of noise and select the most likely recording code sequence from the equalized output.

Now, the branch metrics are, for example, b
Since m00 = 0 and bm40 = 2y (n) +1, if the smaller one is selected, it becomes 0 or a negative value. Over time, it will approach minus infinity. To address this, the Viterbi identification circuit 10 uses the modulo normalization described in the background section. When the output signal of the equalization circuit 9 is represented by 1 bit indicating the sign of the signal and 5 bits indicating the amplitude, that is, 6 bits in total, the Viterbi identification circuit 10 calculates by increasing the portion indicating the amplitude portion by several bits. . For example, the operation is performed with a total of 8 bits by adding 2 bits. Even in the method of adding a constant value as in the first conventional example, since the Viterbi discriminator is configured to increase the number of bits by 1 or 2 for the metric operation, this is not a particularly large change.

Since the Viterbi discriminator 10 of the present invention is premised on the parallelization of two-clock processing, in each state, metrics corresponding to four trellis lines are compared in each state, as shown in FIG. For example, in state 0 at time T (n + 1), four metrics corresponding to state transitions from state 0, state 2, state 4, and state 6 at time T (n-1) are compared and selected. That is, M0 (n + 1) = min ｛M0 (n-1) + bmt0
0, M2 (n-1) + bmt20, M4 (n-1) +
bmt40, M6 (n-1) + bmt60}. bmt indicates a branch metric of a state transition over two clocks.

The embodiment discloses a method in which these metric values are represented by binary codes in a two's complement format, and are compared and selected when using modulo normalization.

FIGS. 6A and 6B show examples of comparators for two metrics C1 and C2 represented by two's complement binary codes and using modulo normalization. FIG. 6 (a)
If the sign SS is detected using the subtraction circuit 14,
And C2 are obtained. An operation example will be described with 4 bits for simplicity. For example, C1 = 011
1, when C2 = 0110, that is, when C1> C2, to calculate the subtraction (C1-C2), first invert all signals of C2 (that is, as 1001) and add 0001. , And then add C1.
As a result, it becomes 0001. Its sign SS is 0.
When C1 = 0111 and C2 = 1011, C1 <C2 with reference to the line circumference in FIG. Subtraction (C1-C
The sign SS of the result of 2) is SS = 1. in this way,
The comparison result of C1 and C2 is obtained by the sign SS of the subtraction circuit.

However, the comparison circuit is generally smaller in circuit scale than the subtraction circuit. FIG. 6B is a configuration diagram based on a comparison circuit. The operation will be described. However, it is assumed that Ci includes a 1-bit code part Si and an a-bit amplitude part Ai. However, i = 1, 2. Sign S
1 and S2 are input to the EX-OR circuit 15-1, and S1
= S2, that is, the output is 0 for the same sign, and 1 for the different sign. On the other hand, the comparator 16 has a normal a
When A1 <= A2, the output is 1, A1
When> A2, the output is set to 0. EX-OR circuit 15-
1 and the output of the comparator 16 are further outputted to the EX-OR circuit 15-.
2 is input. As a result, when C1 <= C2, the output becomes 1, and when C1> C2, the output becomes 0, and the two signal values are compared.

In the same example as above, C1 = 0111, C
Since 2 = 0110 and the same sign, the output of the circuit 15-1 is 0, and the normal comparison between 111 and 110 is 111
> 110, the output of circuit 16 is 0, resulting in:
The output of the circuit 15-2 becomes 0, indicating that C1> C2. Also, C1 = 0111 and C2 = 1011
, The output of the circuit 15-1 is 1, 1
Since the normal comparison of 11 and 011 is 111> 110, the output of the circuit 16 is 0, and as a result, the circuit 15-2
Is 1, which indicates that C1 <C2.

Now, for example, C1 = 0011 and C2 = 1
By comparing 100, it is determined that the output is 0 in both of FIGS. 6A and 6B, and that C1> C2. However, C1 goes clockwise ahead of C2 on the line circumference,
If it reaches 1, the result of the operation will give an incorrect decision. If the difference between C1 and C2 exceeds half the circumference of the line circle shown in FIG. 2, it can be seen that the comparison result between C1 and C2 has a possibility of being erroneous. At this time, C1 is said to have overflowed.

Therefore, in modulo normalization, it is important to set the number of bits so that the difference between two compared values does not exceed the maximum value of the amplitude. However, if a sufficient number of bits are used to prevent overflow in any case, the circuit scale and the number of delay stages for computation become large. Is important.

The two-clock processing Viterbi discriminator 10 needs to compare four signal values in each state and select the minimum signal value. Again, the problem when comparing four signal values of A, B, C, and D using the line circumference shown in FIG. 2 will be described with reference to FIG. FIG. 7A shows A> B
>C> D, and the difference between A and D does not exceed half a circumference. In this case, no matter what order the comparison is made, no overflow occurs, so that a correct comparison result is obtained. For example, since D <A and C <B, D and C are further compared to determine that D is the smallest from D <C. However, as shown in FIG. 7B, when D becomes smaller and the difference between A and D exceeds half a circle, the order of comparison becomes important. For example, first, when A and D and B and C are compared, A <D and C <B are obtained. Therefore, A and C are compared. Since C <A, C is the smallest. Is incorrectly determined. However, first, when A and B and C and D are compared, results of B <A and D <C are obtained. Next, B and D are compared, and D is obtained from the result of D <B.
Is correctly determined to be smallest.

From the above, when comparing four metrics, it is necessary to first compare those which are expected to have a small difference in metric values, and then compare those which are smaller in each comparison. , It can be seen that it is hardly affected by overflow in modulo normalization.

For example, as described above, the time T (n +
In state 0 in 1), the following four metrics are compared and selected. That is, M0 (n + 1) = min ｛M0 (n-1) + bmt0
0, M2 (n-1) + bmt20, M4 (n-1) +
bmt40, M6 (n-1) + bmt60}. FIG. 8 is a rewrite of the trellis of FIG. 5 assuming that the time T (n) also exists virtually, and the time T (n +
Only those that transition to state 0 in 1) are shown. By calculating the respective branch metrics with the equalized output signals as y (n) and y (n + 1), bmt00 = 0, bmt20 = 2y (n) + 1 + 2y (n + 1) +1, bmt40 = 2y (n) +1, bmt60 = 4y (n) + 4 + 2y (n + 1) +1.

The comparison of the metrics involves not only the branch metrics but also the path metrics Mi (n-1) of each state i one time before.

There is one true state t corresponding to the recording code sequence, and the path metric Mt (n-1) of the true state t
Has the smallest value due to the nature of the path metrics. The state t is represented by recording codes Ct (n−3) and Ct (n−
2), expressed as Ct (n-1), that is, the path metric Mtt in a state tt close to that, that is, a state in which the Hamming distance is small from Ct (n-3), Ct (n-2), Ct (n-1).
In many cases, (n-1) is the next smaller value. Here, the Hamming distance means that the state i is the recording code Ci (n-3), Ci (n-2), Ci (n-1).
And the state j is similarly represented by the recording codes Cj (n−3), Cj
When represented by j (n−2) and Cj (n−1), 0 is used when the code corresponding to each time is the same, and 1 when the code is different.
Can be defined as the sum of three bits. That is, since the state 0 is 000 and the state 1 is 001, the Hamming distance between the state 0 and the state 1 is 1. State 7 is 111
Therefore, the Hamming distance is 3 from the state 0. The path metric has a larger value as the Hamming distance is farther from the true state. In other words, the difference between the path metrics Mi (n-1) and Mj (n-1) in the two states i and j has a strong correlation with the Hamming distance Hij in the two states, and the Hamming distance Hij Is smaller, it can be estimated that the difference is smaller. State 0, state 2, and state 4 have a Hamming distance of 1, and state 6 has a Hamming distance of 2. On the other hand, state 2,
The Hamming distance between state 4 and state 6 is 1.

Considering the difference between the states of the branch metrics given above and the Hamming distance between the states, the metric ｛M0 (n
-1) + bmt00} and the metric {M6 (n-1) + bmt60} corresponding to the state transition from state 6 first, the difference between the metrics is large,
Overflow is likely to occur. Therefore, {M0 (n-1) + bmt00} corresponding to the state transition from the state 0 and {M2 (n-1) + b corresponding to the state transition from the state 2
mt40}, {M4 corresponding to state transition from state 4}
(N-1) + bmt40} and {M6 (n-1) + bmt60} corresponding to the state transition from state 6 first, or the metric corresponding to the state transition from state 0 and the state transition from state 4 Metrics corresponding to
Metrics corresponding to state transition from state 2 and state 6
Finding the state transition with the smallest metric by complementing the metrics corresponding to the state transitions from the first, and then comparing the metrics corresponding to the respective smaller state transitions in complement form
It is suitable for the metric calculation of hexadecimal codes. In other words, regarding metrics corresponding to state transitions from two states having a small Hamming distance, first comparison is performed.
Requested.

It has been found that the state of the branch metrics and path metrics described above is the same in each state at time T (n + 1) in FIG. Therefore, in the states 0, 1, 2, and 3 at the time T (n + 1), the same comparison order as in the state 0 is preferable. Further, the time T
In the same way, in the state d (d = 4, 5, 6, 7) of (n + 1), {M1 (n−1) + bmt1d} corresponding to the state transition from state 1 and the state transition from state 3 {M3 (n-1) + bmt3d} corresponding to state transition, {M5 (n-1) + bm corresponding to state transition from state 5
t5d} and {M7 (n
-1) + bmt7d} is compared first, or the metric corresponding to the state transition from the state 1 and the metric corresponding to the state transition from the state 5, the metric corresponding to the state transition from the state 3 and the state from the state 7 Preferably, the metrics corresponding to the transitions are compared first.

FIG. 9 shows a circuit configuration according to the present invention for selecting the minimum value from four metrics in each state in Viterbi identification of the two-clock processing shown in FIG. Pi
(I = 1, 2, 3, 4) indicates the inputs of the four metrics to be compared. Comparison circuits 17-1 to 17-6
Is a comparison circuit CC using modulo normalization in the two's complement binary code shown in FIG. Reference numeral 18 denotes an AND circuit. 19 is an inverting circuit, 20-1 to 20-4 are O
R circuits, 21-1 to 21-4 are switch circuits,
When the output of each corresponding OR circuit is 1, the corresponding metric is selected. As will be described later, since only one of the OR circuits 21-1 to 21-4 becomes 1, one minimum metric is selected. In FIG. 9, the inverting circuit 19 is given a representative number, and the other numbers are omitted.

What is important here is which metric is assigned to Pi, and is determined as follows from the above examination. In the state u (u = 0, 1, 2, 3), P1 = M0 (n-1) + bmt0u P2 = M4 (n-1) + bmt4u P3 = M2 (n-1) + bmt2u P4 = M6 (n-1) + bmt6u Alternatively, P1 = M0 (n-1) + bmt0u P2 = M2 (n-1) + bmt2u P3 = M4 (n-1) + bmt4u P4 = M6 (n-1) + bmt6u In the state d (d = 4, 5, 6, 7), P1 = M1 (n-1) + bmt1d P2 = M5 (n-1) + bmt5d P3 = M3 (n-1) + bmt3d P4 = M7 (n-1) ) + Bmt7d or P1 = M1 (n−1) + bmt1d P2 = M3 (n−1) + bmt3d P3 = M5 (n−1) + bmt5d P4 = M7 (n−1) + bmt7d

In the comparison circuits 17-1 and 17-2,
First, the first comparison is performed, for example, P1 <P2, P3 <P
If it is 4, only the AND circuit 18-1 becomes the output 1 and
The outputs of all the other AND circuits 18-2 to 18-4 become 0. The output of the AND circuit 18-1 is the AND circuit 1
8-5 and 18-6 as gate signals, and the comparison circuit 17
-3 output signal can be sent to the subsequent stage. The output of the comparison circuit 17-3 is directly input to the AND circuit 18-5, and the inverted signal thereof is input to the AND circuit 18-6. Therefore, for example, if P1 <P3, the output of the AND circuit 18-5 is 1 and the output of the AND circuit 18-6 is 0
Becomes As a result, output 1 appears only in OR circuit 20-1, and metric P1 is selected as the minimum metric.

In the case of other comparison results, one minimum metric is selected by the same operation.

As described above, the two-clock processing Viterbi discriminator 10
In the case where modulo normalization is used, 4
A preferred method for selecting the minimum metric from one metric has been presented.

In the description of FIG. 9, it has been described that P1 and P2 and P3 and P4 are compared first. However, as can be seen from the figure, other comparisons are actually input simultaneously. Logically, the order of comparison is important. However, if a circuit for latching the output of the OR circuit is provided when the operation is settled after the input of the comparison input, the skew of the comparison input signal is increased. Don't worry about

In the above example, for modulo normalization, 2
Although it has been described that a margin of bits is provided, it is needless to say that a margin of 3 bits reduces the probability of occurrence of overflow in modulo normalization. However, even when a margin of three bits is provided, the above-described comparison order is effective in the sense of further reducing the influence of overflow.

In the above example, the case of EPR4 equalization is shown. However, in other PR equalization systems, if two clock systems are used, basically four metrics are compared in each state. The present invention applies as it needs to be selected. Note that, depending on the conditions of recording and encoding, there is a case where one of the four trellises is prohibited. At this time, a case occurs in which three metrics are compared and selected. Even in such a case, the concept of the present invention in which the difference in the metrics is expected to be small is first compared, and then the second comparison is performed, so that it is within the scope of the present invention. Further, although the preferred method of the present invention has been described in the case of hardware processing called a circuit, the present invention can be similarly applied to a case where this processing is equivalently software-processed. Although the example of the recording device is shown here,
The present invention is also applicable to high-speed transmission receivers.

[0041]

According to the present invention, modulo normalization with a small circuit size can be applied to Viterbi processing of two clocks suitable for high-speed operation, and a low power consumption and low cost read channel LSI can be provided. Become. Further, the use of this LSI makes it possible to realize a magnetic disk device requiring a high transfer rate.

[Brief description of the drawings]

FIG. 1 is a diagram comparing a trellis diagram of a PR channel in a case of one-clock processing with a case of two-clock processing.

FIG. 2 is a view for explaining a two's complement binary code (4 bits) and its modulo normalization.

FIG. 3 is a signal system diagram of the magnetic disk drive in the embodiment of the present invention.

FIG. 4 is a trellis diagram in EPR4 equalization.

FIG. 5 shows E in two-clock processing targeted in the embodiment.
Trellis diagram of PR4 equalization.

FIG. 6 is a comparison circuit in a modulo-normalized two's complement binary code used in the embodiment.

FIG. 7 is a diagram illustrating overflow in modulo normalization by several circles.

FIG. 8 is a diagram in which a trellis of two-clock processing is disassembled into processing for each clock.

FIG. 9 is a comparison and selection circuit according to the embodiment of the present invention.

[Explanation of symbols]

1. Interface circuit 2. Check code insertion circuit 3. Randomization circuit 4. Recording coding circuit 5.
..Recording amplifier circuit, 7 recording medium, 8 reproduction amplifier circuit, 9 digital filter circuit for EPR4 equalization, 10 Viterbi identification circuit, 11 decoding circuit, 12
..Inverse randomizing circuit, 13-Error correcting circuit, 17-
A comparison circuit for a two's complement binary code using modulo normalization, 21... A switch circuit.

Continued on the front page F term (reference) 5D044 BC01 CC04 5J065 AA03 AB01 AC03 AD10 AE06 AF01 AG05 AH04 AH09 AH15 5K014 AA01 BA10 EA01

Claims (5)

[Claims] In a Viterbi identification having a plurality of states,
Processing is performed every two clocks, a plurality of modulo-normalized metrics are compared in each state, and a minimum value is selected. In each state, a combination of metrics whose difference in metrics is estimated to be small in each state is first determined. A Viterbi identification method characterized by using comparison means and second means for selecting a minimum metric with reference to a result of the comparison means. 2. A combination of metrics whose difference in metrics described in the first item is estimated to be small is a time T (n +
In the state transition to each state in 1), the time T (n
-1) A Viterbi identification method characterized by combining metrics corresponding to a state transition from a state where the Hamming distance of a recording code representing a state in which the state is small is small. 3. A read channel semiconductor device using signal processing combining Viterbi identification and various PR equalization methods according to claim 1 or 2. 4. A read channel semiconductor device according to claim 3, wherein said PR equalization is EPR4 equalization. 5. A magnetic disk drive incorporating the read channel semiconductor device according to claim 3 or 4.